Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	323668884	214238	0	0
ctrl_regwen_rd_A	323668884	2619	0	0
exec_rd_A	323668884	2361	0	0
exec_regwen_rd_A	323668884	2582	0	0
readback_rd_A	323668884	1347	0	0
readback_regwen_rd_A	323668884	1180	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323668884	214238	0	0
T18	0	7834	0	0
T19	0	7918	0	0
T22	139086	5257	0	0
T23	0	7906	0	0
T24	0	3480	0	0
T27	8190	0	0	0
T36	0	5875	0	0
T41	8231	0	0	0
T43	22386	0	0	0
T47	0	6201	0	0
T53	0	1320	0	0
T59	0	2219	0	0
T60	0	4418	0	0
T61	9719	0	0	0
T62	51113	0	0	0
T63	1067	0	0	0
T64	12293	0	0	0
T65	8761	0	0	0
T66	11358	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323668884	2619	0	0
T36	211241	466	0	0
T46	16761	0	0	0
T53	24574	0	0	0
T60	0	216	0	0
T67	0	5	0	0
T68	0	21	0	0
T69	0	9	0	0
T101	160927	0	0	0
T102	251292	0	0	0
T107	0	122	0	0
T108	0	263	0	0
T109	0	301	0	0
T110	0	106	0	0
T111	0	42	0	0
T112	11003	0	0	0
T113	2772	0	0	0
T114	12908	0	0	0
T115	928	0	0	0
T116	2298	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323668884	2361	0	0
T36	211241	432	0	0
T46	16761	0	0	0
T53	24574	0	0	0
T60	0	237	0	0
T67	0	1	0	0
T68	0	15	0	0
T69	0	5	0	0
T101	160927	0	0	0
T102	251292	0	0	0
T107	0	108	0	0
T108	0	153	0	0
T109	0	249	0	0
T110	0	59	0	0
T111	0	27	0	0
T112	11003	0	0	0
T113	2772	0	0	0
T114	12908	0	0	0
T115	928	0	0	0
T116	2298	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323668884	2582	0	0
T36	211241	488	0	0
T46	16761	0	0	0
T53	24574	0	0	0
T60	0	229	0	0
T67	0	5	0	0
T68	0	23	0	0
T69	0	9	0	0
T101	160927	0	0	0
T102	251292	0	0	0
T107	0	146	0	0
T108	0	218	0	0
T109	0	272	0	0
T110	0	61	0	0
T111	0	30	0	0
T112	11003	0	0	0
T113	2772	0	0	0
T114	12908	0	0	0
T115	928	0	0	0
T116	2298	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323668884	1347	0	0
T36	211241	405	0	0
T46	16761	0	0	0
T53	24574	0	0	0
T60	0	208	0	0
T101	160927	0	0	0
T102	251292	0	0	0
T107	0	124	0	0
T108	0	129	0	0
T109	0	285	0	0
T110	0	63	0	0
T111	0	29	0	0
T112	11003	0	0	0
T113	2772	0	0	0
T114	12908	0	0	0
T115	928	0	0	0
T116	2298	0	0	0
T117	0	23	0	0
T118	0	21	0	0
T119	0	18	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323668884	1180	0	0
T36	211241	306	0	0
T46	16761	0	0	0
T53	24574	0	0	0
T60	0	146	0	0
T101	160927	0	0	0
T102	251292	0	0	0
T107	0	131	0	0
T108	0	227	0	0
T109	0	260	0	0
T110	0	25	0	0
T111	0	10	0	0
T112	11003	0	0	0
T113	2772	0	0	0
T114	12908	0	0	0
T115	928	0	0	0
T116	2298	0	0	0
T117	0	16	0	0
T118	0	15	0	0
T120	0	30	0	0