Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13517839

1

T2

2426

T3

358

T4

99

full_word

53447612

1

T2

517

T3

3542

T4

958

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66965141	1			T2	2943		T3	3900		T4	1057
auto[TlIntgErrCmd]	84	1			T53	5		T54	5		T121	2
auto[TlIntgErrData]	110	1			T52	6		T53	9		T54	6
auto[TlIntgErrBoth]	116	1			T52	4		T53	6		T54	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30696266

1

T2

1496

T3

1993

T4

530

auto[1]

36269185

1

T2

1447

T3

1907

T4

527

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6468950	1			T2	1234		T3	183		T4	52
auto[TlIntgErrNone]	partial	auto[1]	7048605	1			T2	1192		T3	175		T4	47
auto[TlIntgErrNone]	full_word	auto[0]	24227183	1			T2	262		T3	1810		T4	478
auto[TlIntgErrNone]	full_word	auto[1]	29220403	1			T2	255		T3	1732		T4	480
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T53	3		T54	2		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T53	2		T54	2		T121	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T54	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T127	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1			T52	4		T53	4		T54	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T52	1		T53	4		T54	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T54	1		T115	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T52	1		T53	1		T54	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T52	1		T53	4		T54	5
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T52	3		T53	2		T54	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T128	1		T125	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T54	1		T127	1		T130	2