Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
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Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mem_bkdr_scb 100.00 1 100 1 64 64




Group Instance : mem_bkdr_scb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mem_bkdr_scb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group Instance mem_bkdr_scb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
b2b_access_types_cp 4 0 4 100.00 100 1 1 4
b2b_partial_types_cp 4 0 4 100.00 100 1 1 4
raw_hazard_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance mem_bkdr_scb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_cross 32 0 32 100.00 100 1 1 0


Summary for Variable b2b_access_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_access_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 599959 1 T3 12 T8 7 T9 17
auto[1] 11232557 1 T2 21 T3 109 T7 123
auto[2] 493270 1 T3 14 T8 6 T9 4
auto[3] 11140303 1 T2 16 T3 98 T7 121



Summary for Variable b2b_partial_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_partial_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14905315 1 T3 155 T7 178 T8 13
auto[1] 2273739 1 T2 7 T3 26 T7 36
auto[2] 2284936 1 T2 3 T3 48 T7 27
auto[3] 4002099 1 T2 27 T3 4 T7 3



Summary for Variable raw_hazard_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for raw_hazard_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9702766 1 T2 37 T3 233 T7 244
auto[1] 13763323 1 T28 1 T33 1 T67 1



Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for all_cross

Bins
raw_hazard_cpb2b_access_types_cpb2b_partial_types_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 233862 1 T3 9 T8 5 T9 16
auto[0] auto[0] auto[1] 23890 1 T3 2 T145 8 T113 18
auto[0] auto[0] auto[2] 23896 1 T3 1 T8 2 T9 1
auto[0] auto[0] auto[3] 5691 1 T41 15 T145 46 T113 81
auto[0] auto[1] auto[0] 3773066 1 T3 83 T7 83 T8 2
auto[0] auto[1] auto[1] 381083 1 T2 5 T3 20 T7 23
auto[0] auto[1] auto[2] 379671 1 T2 1 T3 6 T7 14
auto[0] auto[1] auto[3] 68457 1 T2 15 T7 3 T33 36
auto[0] auto[2] auto[0] 198683 1 T8 3 T9 3 T67 3
auto[0] auto[2] auto[1] 20244 1 T8 1 T118 2 T81 21
auto[0] auto[2] auto[2] 21869 1 T3 13 T8 2 T9 1
auto[0] auto[2] auto[3] 4984 1 T3 1 T10 1 T41 10
auto[0] auto[3] auto[0] 3740478 1 T3 63 T7 95 T8 3
auto[0] auto[3] auto[1] 375630 1 T2 2 T3 4 T7 13
auto[0] auto[3] auto[2] 381167 1 T2 2 T3 28 T7 13
auto[0] auto[3] auto[3] 70095 1 T2 12 T3 3 T33 31
auto[1] auto[0] auto[0] 10397 1 T99 113 T144 127 T146 2
auto[1] auto[0] auto[1] 46551 1 T99 562 T144 501 T147 280
auto[1] auto[0] auto[2] 46323 1 T99 476 T144 543 T147 265
auto[1] auto[0] auto[3] 209349 1 T41 1 T81 3 T99 2394
auto[1] auto[1] auto[0] 3469195 1 T50 2 T51 3 T111 3
auto[1] auto[1] auto[1] 703902 1 T148 1 T149 1 T150 1
auto[1] auto[1] auto[2] 698788 1 T151 1 T149 1 T152 1
auto[1] auto[1] auto[3] 1758395 1 T148 1 T80 1 T153 2
auto[1] auto[2] auto[0] 7958 1 T67 1 T146 5 T154 2
auto[1] auto[2] auto[1] 35062 1 T146 1 T155 1 T156 2375
auto[1] auto[2] auto[2] 37091 1 T99 508 T144 509 T147 247
auto[1] auto[2] auto[3] 167379 1 T81 1 T99 2109 T144 2146
auto[1] auto[3] auto[0] 3471676 1 T28 1 T51 3 T111 3
auto[1] auto[3] auto[1] 687377 1 T151 1 T80 2 T150 2
auto[1] auto[3] auto[2] 696131 1 T148 1 T152 1 T150 1
auto[1] auto[3] auto[3] 1717749 1 T33 1 T80 3 T81 1

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