Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	283203573	163185	0	0
ctrl_regwen_rd_A	283203573	2968	0	0
exec_rd_A	283203573	2913	0	0
exec_regwen_rd_A	283203573	3368	0	0
readback_rd_A	283203573	1958	0	0
readback_regwen_rd_A	283203573	1688	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283203573	163185	0	0
T10	63521	0	0	0
T16	195645	0	0	0
T18	0	9339	0	0
T22	19289	1017	0	0
T23	0	1287	0	0
T24	0	1781	0	0
T37	33579	0	0	0
T40	5242	0	0	0
T46	0	2667	0	0
T47	0	4837	0	0
T59	0	3893	0	0
T60	0	3758	0	0
T61	0	3696	0	0
T62	0	1654	0	0
T63	13468	0	0	0
T64	101976	0	0	0
T65	49452	0	0	0
T66	2890	0	0	0
T67	52644	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283203573	2968	0	0
T23	22499	95	0	0
T24	24428	0	0	0
T30	10871	0	0	0
T38	0	505	0	0
T51	8278	0	0	0
T52	0	2	0	0
T58	0	9	0	0
T68	0	4	0	0
T103	0	84	0	0
T104	0	473	0	0
T105	0	246	0	0
T106	0	254	0	0
T107	0	72	0	0
T108	34781	0	0	0
T109	95183	0	0	0
T110	2659	0	0	0
T111	9723	0	0	0
T112	958	0	0	0
T113	26527	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283203573	2913	0	0
T23	22499	91	0	0
T24	24428	0	0	0
T30	10871	0	0	0
T38	0	492	0	0
T51	8278	0	0	0
T52	0	24	0	0
T58	0	3	0	0
T103	0	98	0	0
T104	0	460	0	0
T105	0	209	0	0
T106	0	217	0	0
T107	0	138	0	0
T108	34781	0	0	0
T109	95183	0	0	0
T110	2659	0	0	0
T111	9723	0	0	0
T112	958	0	0	0
T113	26527	0	0	0
T114	0	60	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283203573	3368	0	0
T23	22499	151	0	0
T24	24428	0	0	0
T30	10871	0	0	0
T38	0	503	0	0
T51	8278	0	0	0
T52	0	28	0	0
T58	0	8	0	0
T68	0	6	0	0
T103	0	81	0	0
T104	0	661	0	0
T105	0	191	0	0
T106	0	267	0	0
T107	0	138	0	0
T108	34781	0	0	0
T109	95183	0	0	0
T110	2659	0	0	0
T111	9723	0	0	0
T112	958	0	0	0
T113	26527	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283203573	1958	0	0
T23	22499	84	0	0
T24	24428	0	0	0
T30	10871	0	0	0
T38	0	516	0	0
T51	8278	0	0	0
T103	0	77	0	0
T104	0	461	0	0
T105	0	173	0	0
T106	0	273	0	0
T107	0	85	0	0
T108	34781	0	0	0
T109	95183	0	0	0
T110	2659	0	0	0
T111	9723	0	0	0
T112	958	0	0	0
T113	26527	0	0	0
T114	0	50	0	0
T115	0	3	0	0
T116	0	56	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283203573	1688	0	0
T23	22499	97	0	0
T24	24428	0	0	0
T30	10871	0	0	0
T38	0	451	0	0
T51	8278	0	0	0
T103	0	60	0	0
T104	0	388	0	0
T105	0	171	0	0
T106	0	185	0	0
T107	0	114	0	0
T108	34781	0	0	0
T109	95183	0	0	0
T110	2659	0	0	0
T111	9723	0	0	0
T112	958	0	0	0
T113	26527	0	0	0
T114	0	48	0	0
T116	0	87	0	0
T117	0	32	0	0