Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14374993

1

T2

6

T4

114

T5

1780

full_word

56169614

1

T2

43

T4

931

T5

113

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70544317	1			T2	49		T4	1045		T5	1893
auto[TlIntgErrCmd]	91	1			T54	3		T55	4		T56	4
auto[TlIntgErrData]	102	1			T54	5		T55	4		T56	8
auto[TlIntgErrBoth]	97	1			T54	2		T55	12		T56	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32247192

1

T2

26

T4

518

T5

848

auto[1]

38297415

1

T2

23

T4

527

T5

1045

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6864976	1			T2	3		T4	56		T5	841
auto[TlIntgErrNone]	partial	auto[1]	7509754	1			T2	3		T4	58		T5	939
auto[TlIntgErrNone]	full_word	auto[0]	25382079	1			T2	23		T4	462		T5	7
auto[TlIntgErrNone]	full_word	auto[1]	30787508	1			T2	20		T4	469		T5	106
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T54	3		T55	2		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T55	1		T56	2		T119	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T123	1		T125	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T55	1		T122	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T54	3		T55	1		T56	4
auto[TlIntgErrData]	partial	auto[1]	42	1			T54	2		T55	3		T56	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T123	1		T121	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T56	1		T120	2		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T54	1		T55	1		T56	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T54	1		T55	9		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T55	1		T56	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T55	1		T56	1		T122	2