Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	812346	1			T8	1		T34	29		T35	103
auto[1]	10490115	1			T6	6		T9	766		T29	1726
auto[2]	685375	1			T8	2		T34	7		T35	92
auto[3]	10367006	1			T2	1		T6	6		T9	1025

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14094351	1			T6	8		T9	9		T8	3
auto[1]	2159361	1			T6	2		T9	89		T37	103
auto[2]	2185119	1			T2	1		T6	2		T9	145
auto[3]	3916011	1			T9	1548		T37	1530		T47	4091

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8457599

1

T2

1

T6

12

T9

1790

auto[1]

13897243

1

T9

1

T29

2

T37

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	344429	1			T8	1		T34	19		T44	42
auto[0]	auto[0]	auto[1]	35302	1			T34	4		T35	2		T44	148
auto[0]	auto[0]	auto[2]	35243	1			T34	4		T35	2		T44	145
auto[0]	auto[0]	auto[3]	9771	1			T34	2		T35	96		T44	682
auto[0]	auto[1]	auto[0]	3149709	1			T6	4		T29	1724		T47	86
auto[0]	auto[1]	auto[1]	332376	1			T9	10		T37	7		T47	442
auto[0]	auto[1]	auto[2]	318488	1			T6	2		T9	71		T37	76
auto[0]	auto[1]	auto[3]	69427	1			T9	685		T37	694		T47	2015
auto[0]	auto[2]	auto[0]	287849	1			T8	2		T44	27		T26	1190
auto[0]	auto[2]	auto[1]	29700	1			T35	16		T44	156		T26	116
auto[0]	auto[2]	auto[2]	32025	1			T34	5		T35	1		T44	136
auto[0]	auto[2]	auto[3]	7994	1			T34	2		T35	75		T44	564
auto[0]	auto[3]	auto[0]	3093131	1			T6	4		T9	9		T29	1750
auto[0]	auto[3]	auto[1]	311638	1			T6	2		T9	79		T37	96
auto[0]	auto[3]	auto[2]	330527	1			T2	1		T9	74		T37	86
auto[0]	auto[3]	auto[3]	69990	1			T9	862		T37	835		T47	2072
auto[1]	auto[0]	auto[0]	13207	1			T26	1		T141	5		T139	146
auto[1]	auto[0]	auto[1]	57546	1			T26	1		T139	694		T140	523
auto[1]	auto[0]	auto[2]	57955	1			T141	1		T139	720		T140	498
auto[1]	auto[0]	auto[3]	258893	1			T35	3		T139	3179		T140	2321
auto[1]	auto[1]	auto[0]	3600017	1			T29	2		T28	3		T142	3
auto[1]	auto[1]	auto[1]	693691	1			T47	1		T143	1		T144	2
auto[1]	auto[1]	auto[2]	674674	1			T143	1		T144	2		T72	3637
auto[1]	auto[1]	auto[3]	1651733	1			T47	2		T143	2		T44	1
auto[1]	auto[2]	auto[0]	9378	1			T26	2		T141	8		T145	1
auto[1]	auto[2]	auto[1]	40932	1			T44	1		T141	1		T146	1750
auto[1]	auto[2]	auto[2]	50770	1			T44	1		T139	659		T140	452
auto[1]	auto[2]	auto[3]	226727	1			T147	1		T139	2814		T140	2167
auto[1]	auto[3]	auto[0]	3596631	1			T34	1		T28	4		T142	2
auto[1]	auto[3]	auto[1]	658176	1			T68	1		T72	3873		T74	1
auto[1]	auto[3]	auto[2]	685437	1			T47	2		T143	1		T25	1
auto[1]	auto[3]	auto[3]	1621476	1			T9	1		T37	1		T47	2