Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	327398182	200968	0	0
ctrl_regwen_rd_A	327398182	3923	0	0
exec_rd_A	327398182	3816	0	0
exec_regwen_rd_A	327398182	4033	0	0
readback_rd_A	327398182	2614	0	0
readback_regwen_rd_A	327398182	2193	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327398182	200968	0	0
T20	0	3243	0	0
T21	0	7003	0	0
T22	34373	0	0	0
T25	100111	4770	0	0
T26	0	3736	0	0
T45	0	2362	0	0
T52	0	5973	0	0
T63	0	2795	0	0
T64	0	1058	0	0
T65	0	5325	0	0
T66	0	9459	0	0
T67	32351	0	0	0
T68	20617	0	0	0
T69	12749	0	0	0
T70	4338	0	0	0
T71	546096	0	0	0
T72	133081	0	0	0
T73	2949	0	0	0
T74	7161	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327398182	3923	0	0
T20	0	179	0	0
T23	43992	0	0	0
T26	211325	340	0	0
T45	0	228	0	0
T49	6505	0	0	0
T50	44727	0	0	0
T64	0	90	0	0
T101	186488	0	0	0
T106	0	103	0	0
T107	0	226	0	0
T108	0	366	0	0
T109	0	203	0	0
T110	0	139	0	0
T111	0	39	0	0
T112	8151	0	0	0
T113	3062	0	0	0
T114	8708	0	0	0
T115	33936	0	0	0
T116	1398	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327398182	3816	0	0
T20	0	259	0	0
T23	43992	0	0	0
T26	211325	282	0	0
T45	0	171	0	0
T49	6505	0	0	0
T50	44727	0	0	0
T64	0	67	0	0
T101	186488	0	0	0
T106	0	71	0	0
T107	0	296	0	0
T108	0	270	0	0
T109	0	152	0	0
T110	0	141	0	0
T111	0	78	0	0
T112	8151	0	0	0
T113	3062	0	0	0
T114	8708	0	0	0
T115	33936	0	0	0
T116	1398	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327398182	4033	0	0
T20	0	345	0	0
T23	43992	0	0	0
T26	211325	253	0	0
T45	0	219	0	0
T49	6505	0	0	0
T50	44727	0	0	0
T64	0	57	0	0
T101	186488	0	0	0
T106	0	149	0	0
T107	0	203	0	0
T108	0	314	0	0
T109	0	185	0	0
T110	0	164	0	0
T111	0	38	0	0
T112	8151	0	0	0
T113	3062	0	0	0
T114	8708	0	0	0
T115	33936	0	0	0
T116	1398	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327398182	2614	0	0
T20	0	271	0	0
T23	43992	0	0	0
T26	211325	252	0	0
T45	0	203	0	0
T49	6505	0	0	0
T50	44727	0	0	0
T64	0	40	0	0
T101	186488	0	0	0
T106	0	67	0	0
T107	0	227	0	0
T108	0	358	0	0
T109	0	166	0	0
T110	0	79	0	0
T111	0	36	0	0
T112	8151	0	0	0
T113	3062	0	0	0
T114	8708	0	0	0
T115	33936	0	0	0
T116	1398	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327398182	2193	0	0
T20	0	260	0	0
T23	43992	0	0	0
T26	211325	245	0	0
T45	0	175	0	0
T49	6505	0	0	0
T50	44727	0	0	0
T64	0	60	0	0
T101	186488	0	0	0
T106	0	101	0	0
T107	0	155	0	0
T108	0	275	0	0
T109	0	133	0	0
T110	0	107	0	0
T111	0	26	0	0
T112	8151	0	0	0
T113	3062	0	0	0
T114	8708	0	0	0
T115	33936	0	0	0
T116	1398	0	0	0