Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14024034

1

T1

21

T2

4927

T4

10

full_word

56336800

1

T1

234

T2

50185

T4

46

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70360554	1			T1	255		T2	55112		T4	56
auto[TlIntgErrCmd]	104	1			T103	5		T104	6		T105	4
auto[TlIntgErrData]	91	1			T103	3		T104	5		T105	6
auto[TlIntgErrBoth]	85	1			T103	2		T104	9		T128	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32310745

1

T1

120

T2

27445

T4

25

auto[1]

38050089

1

T1

135

T2

27667

T4

31

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6706866	1			T1	7		T2	2460		T4	6
auto[TlIntgErrNone]	partial	auto[1]	7316910	1			T1	14		T2	2467		T4	4
auto[TlIntgErrNone]	full_word	auto[0]	25603758	1			T1	113		T2	24985		T4	19
auto[TlIntgErrNone]	full_word	auto[1]	30733020	1			T1	121		T2	25200		T4	27
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T103	1		T104	2		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T103	3		T104	4		T105	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T103	1		T132	2		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T133	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T103	1		T104	3		T105	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T103	2		T104	2		T105	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T134	1		T130	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T129	1		T136	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T104	4		T128	1		T129	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T103	2		T104	4		T128	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T126	1		T134	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T104	1		T134	1		T132	1