Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	678581	1			T2	1295		T26	119		T16	4
auto[1]	10899072	1			T1	111		T2	969		T4	25
auto[2]	558889	1			T2	838		T26	95		T16	3
auto[3]	10785296	1			T1	124		T2	425		T4	30

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14816576	1			T1	200		T2	2758		T4	38
auto[1]	2191693	1			T1	19		T2	331		T4	7
auto[2]	2208620	1			T1	16		T2	393		T4	8
auto[3]	3704949	1			T2	45		T4	2		T26	462

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9188003

1

T1

235

T2

3526

T4

55

auto[1]

13733835

1

T2

1

T26

2

T28

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	254733	1			T2	1068		T16	4		T8	4
auto[0]	auto[0]	auto[1]	26788	1			T2	109		T26	1		T8	2
auto[0]	auto[0]	auto[2]	26827	1			T2	103		T26	1		T150	32
auto[0]	auto[0]	auto[3]	9771	1			T2	14		T26	117		T150	130
auto[0]	auto[1]	auto[0]	3522329	1			T1	97		T2	742		T4	16
auto[0]	auto[1]	auto[1]	367203	1			T1	7		T2	128		T4	3
auto[0]	auto[1]	auto[2]	354693	1			T1	7		T2	89		T4	4
auto[0]	auto[1]	auto[3]	74297	1			T2	10		T4	2		T26	101
auto[0]	auto[2]	auto[0]	216482	1			T2	664		T16	2		T8	4
auto[0]	auto[2]	auto[1]	22369	1			T2	67		T26	6		T8	3
auto[0]	auto[2]	auto[2]	26009	1			T2	93		T26	2		T16	1
auto[0]	auto[2]	auto[3]	7698	1			T2	14		T26	87		T150	88
auto[0]	auto[3]	auto[0]	3487004	1			T1	103		T2	283		T4	22
auto[0]	auto[3]	auto[1]	350448	1			T1	12		T2	27		T4	4
auto[0]	auto[3]	auto[2]	366889	1			T1	9		T2	108		T4	4
auto[0]	auto[3]	auto[3]	74463	1			T2	7		T26	155		T7	4
auto[1]	auto[0]	auto[0]	12030	1			T2	1		T93	348		T94	97
auto[1]	auto[0]	auto[1]	53454	1			T93	1415		T94	426		T151	1
auto[1]	auto[0]	auto[2]	53656	1			T152	1		T93	1416		T94	457
auto[1]	auto[0]	auto[3]	241322	1			T150	1		T117	1		T93	6174
auto[1]	auto[1]	auto[0]	3659673	1			T46	6		T153	3		T154	1
auto[1]	auto[1]	auto[1]	679559	1			T117	1		T155	1		T29	1
auto[1]	auto[1]	auto[2]	668102	1			T29	2		T156	2		T80	6000
auto[1]	auto[1]	auto[3]	1573216	1			T26	1		T28	1		T157	3
auto[1]	auto[2]	auto[0]	8833	1			T93	207		T151	3		T158	852
auto[1]	auto[2]	auto[1]	38304	1			T152	1		T93	788		T158	3946
auto[1]	auto[2]	auto[2]	43544	1			T93	1593		T94	370		T151	1
auto[1]	auto[2]	auto[3]	195650	1			T150	1		T117	2		T93	6679
auto[1]	auto[3]	auto[0]	3655492	1			T46	3		T159	1		T153	1
auto[1]	auto[3]	auto[1]	653568	1			T153	1		T160	1		T157	2
auto[1]	auto[3]	auto[2]	668900	1			T153	1		T80	5389		T81	5160
auto[1]	auto[3]	auto[3]	1528532	1			T26	1		T117	2		T157	4