Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	330874896	184141	0	0
ctrl_regwen_rd_A	330874896	3573	0	0
exec_rd_A	330874896	3355	0	0
exec_regwen_rd_A	330874896	3784	0	0
readback_rd_A	330874896	4964	0	0
readback_regwen_rd_A	330874896	2025	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874896	184141	0	0
T8	24669	0	0	0
T14	734	0	0	0
T16	22051	1179	0	0
T20	0	4132	0	0
T21	0	5436	0	0
T23	2222	0	0	0
T27	13283	0	0	0
T28	8847	0	0	0
T32	65362	0	0	0
T33	9661	0	0	0
T35	0	2762	0	0
T36	0	4144	0	0
T37	0	2235	0	0
T43	0	4336	0	0
T45	0	6551	0	0
T46	8311	0	0	0
T47	0	1994	0	0
T48	0	3633	0	0
T49	29478	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874896	3573	0	0
T20	109120	127	0	0
T37	0	80	0	0
T38	9398	0	0	0
T41	8802	0	0	0
T48	0	369	0	0
T107	0	113	0	0
T108	0	184	0	0
T109	0	357	0	0
T110	0	234	0	0
T111	0	281	0	0
T112	0	265	0	0
T113	0	80	0	0
T114	432001	0	0	0
T115	105780	0	0	0
T116	1974	0	0	0
T117	60631	0	0	0
T118	235430	0	0	0
T119	303077	0	0	0
T120	1348	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874896	3355	0	0
T20	109120	151	0	0
T37	0	67	0	0
T38	9398	0	0	0
T41	8802	0	0	0
T48	0	287	0	0
T107	0	89	0	0
T108	0	109	0	0
T109	0	297	0	0
T110	0	223	0	0
T111	0	284	0	0
T112	0	356	0	0
T113	0	66	0	0
T114	432001	0	0	0
T115	105780	0	0	0
T116	1974	0	0	0
T117	60631	0	0	0
T118	235430	0	0	0
T119	303077	0	0	0
T120	1348	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874896	3784	0	0
T20	109120	137	0	0
T37	0	137	0	0
T38	9398	0	0	0
T41	8802	0	0	0
T48	0	331	0	0
T107	0	149	0	0
T108	0	98	0	0
T109	0	357	0	0
T110	0	214	0	0
T111	0	262	0	0
T112	0	356	0	0
T113	0	58	0	0
T114	432001	0	0	0
T115	105780	0	0	0
T116	1974	0	0	0
T117	60631	0	0	0
T118	235430	0	0	0
T119	303077	0	0	0
T120	1348	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874896	4964	0	0
T17	0	3	0	0
T20	109120	119	0	0
T37	0	95	0	0
T38	9398	0	0	0
T41	8802	0	0	0
T48	0	421	0	0
T107	0	96	0	0
T108	0	174	0	0
T109	0	442	0	0
T114	432001	0	0	0
T115	105780	0	0	0
T116	1974	0	0	0
T117	60631	0	0	0
T118	235430	0	0	0
T119	303077	0	0	0
T120	1348	0	0	0
T121	0	98	0	0
T122	0	88	0	0
T123	0	118	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874896	2025	0	0
T20	109120	119	0	0
T37	0	74	0	0
T38	9398	0	0	0
T41	8802	0	0	0
T48	0	279	0	0
T107	0	94	0	0
T108	0	77	0	0
T109	0	278	0	0
T110	0	190	0	0
T111	0	187	0	0
T112	0	194	0	0
T113	0	37	0	0
T114	432001	0	0	0
T115	105780	0	0	0
T116	1974	0	0	0
T117	60631	0	0	0
T118	235430	0	0	0
T119	303077	0	0	0
T120	1348	0	0	0