Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14237796

1

T1

2

T4

46

T5

1895

full_word

55319490

1

T1

33

T4

465

T5

109

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69556936	1			T1	35		T4	511		T5	2004
auto[TlIntgErrCmd]	117	1			T108	4		T109	4		T110	9
auto[TlIntgErrData]	119	1			T108	3		T109	6		T110	5
auto[TlIntgErrBoth]	114	1			T108	3		T109	10		T110	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31942477

1

T1

16

T4

240

T5

875

auto[1]

37614809

1

T1

19

T4

271

T5

1129

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6812422	1			T4	25		T5	867		T9	150
auto[TlIntgErrNone]	partial	auto[1]	7425051	1			T1	2		T4	21		T5	1028
auto[TlIntgErrNone]	full_word	auto[0]	25129888	1			T1	16		T4	215		T5	8
auto[TlIntgErrNone]	full_word	auto[1]	30189575	1			T1	17		T4	250		T5	101
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T108	1		T110	2		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T108	2		T109	4		T110	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T110	2		T122	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T108	1		T110	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T108	1		T109	1		T110	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T108	2		T109	4		T110	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T109	1		T121	1		T129	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T130	2		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T108	1		T109	7		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T108	2		T109	3		T110	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T122	2		T129	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T133	1		-	-		-	-