Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	701464	1			T9	222		T8	10		T37	218
auto[1]	11206050	1			T1	1		T5	853		T9	153
auto[2]	573814	1			T9	143		T6	1		T8	10
auto[3]	11085463	1			T1	1		T5	1086		T9	82

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14952423	1			T1	1		T5	9		T9	445
auto[1]	2282857	1			T1	1		T5	99		T9	77
auto[2]	2292157	1			T5	155		T9	73		T6	79
auto[3]	4039354	1			T5	1676		T9	5		T6	4

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9640607

1

T1

2

T5

1937

T9

599

auto[1]

13926184

1

T5

2

T9

1

T6

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	292452	1			T9	180		T8	8		T37	5
auto[0]	auto[0]	auto[1]	29556	1			T9	25		T8	1		T37	31
auto[0]	auto[0]	auto[2]	29386	1			T9	16		T8	1		T37	43
auto[0]	auto[0]	auto[3]	5998	1			T37	139		T63	178		T151	11
auto[0]	auto[1]	auto[0]	3680533	1			T9	107		T6	454		T36	2499
auto[0]	auto[1]	auto[1]	380611	1			T1	1		T5	7		T9	31
auto[0]	auto[1]	auto[2]	372031	1			T5	69		T9	11		T6	42
auto[0]	auto[1]	auto[3]	79687	1			T5	776		T9	4		T54	23
auto[0]	auto[2]	auto[0]	246765	1			T9	115		T8	8		T24	4
auto[0]	auto[2]	auto[1]	24833	1			T9	11		T8	2		T63	34
auto[0]	auto[2]	auto[2]	27156	1			T9	16		T37	22		T63	28
auto[0]	auto[2]	auto[3]	4865	1			T9	1		T6	1		T37	130
auto[0]	auto[3]	auto[0]	3638781	1			T1	1		T5	9		T9	42
auto[0]	auto[3]	auto[1]	367389	1			T5	92		T9	10		T6	43
auto[0]	auto[3]	auto[2]	379259	1			T5	86		T9	30		T6	37
auto[0]	auto[3]	auto[3]	81305	1			T5	898		T6	3		T54	25
auto[1]	auto[0]	auto[0]	11606	1			T9	1		T148	116		T149	111
auto[1]	auto[0]	auto[1]	51260	1			T148	493		T149	484		T150	2793
auto[1]	auto[0]	auto[2]	51381	1			T148	490		T152	1		T149	515
auto[1]	auto[0]	auto[3]	229825	1			T148	2137		T149	2226		T150	12376
auto[1]	auto[1]	auto[0]	3538358	1			T6	2		T36	2		T31	1
auto[1]	auto[1]	auto[1]	707505	1			T54	1		T153	1		T63	1
auto[1]	auto[1]	auto[2]	696711	1			T55	1		T153	1		T25	1
auto[1]	auto[1]	auto[3]	1750614	1			T5	1		T37	1		T69	1
auto[1]	auto[2]	auto[0]	8560	1			T150	588		T154	1		T155	1
auto[1]	auto[2]	auto[1]	37198	1			T150	2459		T155	1		T116	1
auto[1]	auto[2]	auto[2]	40648	1			T148	455		T152	1		T149	469
auto[1]	auto[2]	auto[3]	183789	1			T148	2000		T152	1		T149	2063
auto[1]	auto[3]	auto[0]	3535368	1			T36	1		T31	2		T55	2
auto[1]	auto[3]	auto[1]	684505	1			T6	1		T55	1		T153	1
auto[1]	auto[3]	auto[2]	695585	1			T55	1		T66	2		T25	1
auto[1]	auto[3]	auto[3]	1703271	1			T5	1		T55	1		T101	32594