Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	315423803	195317	0	0
ctrl_regwen_rd_A	315423803	4049	0	0
exec_rd_A	315423803	3481	0	0
exec_regwen_rd_A	315423803	4206	0	0
readback_rd_A	315423803	5812	0	0
readback_regwen_rd_A	315423803	2554	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315423803	195317	0	0
T18	0	2782	0	0
T21	48628	0	0	0
T24	20878	1152	0	0
T25	0	5782	0	0
T26	0	5638	0	0
T49	0	6805	0	0
T57	0	2793	0	0
T59	0	4048	0	0
T60	0	3324	0	0
T61	0	5570	0	0
T62	0	2101	0	0
T63	16643	0	0	0
T64	7598	0	0	0
T65	475803	0	0	0
T66	8371	0	0	0
T67	1990	0	0	0
T68	12112	0	0	0
T69	5932	0	0	0
T70	9140	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315423803	4049	0	0
T21	48628	0	0	0
T24	20878	87	0	0
T49	0	536	0	0
T50	0	353	0	0
T51	0	383	0	0
T53	0	145	0	0
T63	16643	0	0	0
T64	7598	0	0	0
T65	475803	0	0	0
T66	8371	0	0	0
T67	1990	0	0	0
T68	12112	0	0	0
T69	5932	0	0	0
T70	9140	0	0	0
T111	0	224	0	0
T112	0	401	0	0
T113	0	34	0	0
T114	0	148	0	0
T115	0	119	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315423803	3481	0	0
T21	48628	0	0	0
T24	20878	70	0	0
T49	0	387	0	0
T50	0	293	0	0
T51	0	318	0	0
T53	0	81	0	0
T63	16643	0	0	0
T64	7598	0	0	0
T65	475803	0	0	0
T66	8371	0	0	0
T67	1990	0	0	0
T68	12112	0	0	0
T69	5932	0	0	0
T70	9140	0	0	0
T111	0	160	0	0
T112	0	304	0	0
T113	0	72	0	0
T114	0	125	0	0
T115	0	124	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315423803	4206	0	0
T21	48628	0	0	0
T24	20878	128	0	0
T49	0	583	0	0
T50	0	324	0	0
T51	0	405	0	0
T53	0	152	0	0
T63	16643	0	0	0
T64	7598	0	0	0
T65	475803	0	0	0
T66	8371	0	0	0
T67	1990	0	0	0
T68	12112	0	0	0
T69	5932	0	0	0
T70	9140	0	0	0
T111	0	240	0	0
T112	0	487	0	0
T113	0	68	0	0
T114	0	117	0	0
T115	0	172	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315423803	5812	0	0
T19	0	18	0	0
T20	0	35	0	0
T21	48628	0	0	0
T24	20878	63	0	0
T49	0	445	0	0
T50	0	311	0	0
T53	0	102	0	0
T63	16643	0	0	0
T64	7598	0	0	0
T65	475803	0	0	0
T66	8371	0	0	0
T67	1990	0	0	0
T68	12112	0	0	0
T69	5932	0	0	0
T70	9140	0	0	0
T116	0	151	0	0
T117	0	38	0	0
T118	0	136	0	0
T119	0	159	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315423803	2554	0	0
T21	48628	0	0	0
T24	20878	50	0	0
T49	0	446	0	0
T50	0	291	0	0
T51	0	293	0	0
T53	0	105	0	0
T63	16643	0	0	0
T64	7598	0	0	0
T65	475803	0	0	0
T66	8371	0	0	0
T67	1990	0	0	0
T68	12112	0	0	0
T69	5932	0	0	0
T70	9140	0	0	0
T111	0	194	0	0
T112	0	295	0	0
T113	0	37	0	0
T114	0	84	0	0
T115	0	139	0	0