Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13300419

1

T2

627

T5

874

T6

47

full_word

55539887

1

T2

6290

T4

13

T5

59

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68840006	1			T2	6917		T4	13		T5	933
auto[TlIntgErrCmd]	101	1			T104	3		T105	4		T106	9
auto[TlIntgErrData]	115	1			T104	5		T105	3		T106	7
auto[TlIntgErrBoth]	84	1			T104	2		T105	3		T106	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31406223

1

T2

3547

T4

13

T5

337

auto[1]

37434083

1

T2

3370

T5

596

T6

285

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6329181	1			T2	309		T5	332		T6	16
auto[TlIntgErrNone]	partial	auto[1]	6970964	1			T2	318		T5	542		T6	31
auto[TlIntgErrNone]	full_word	auto[0]	25076901	1			T2	3238		T4	13		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	30462960	1			T2	3052		T5	54		T6	254
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T104	3		T105	2		T106	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T105	1		T106	8		T115	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T115	2		T116	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T105	1		T115	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T104	4		T106	3		T115	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T105	3		T106	4		T115	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T114	1		T122	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T104	1		T113	1		T123	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T104	2		T106	2		T115	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T105	3		T106	2		T115	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T113	1		T124	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T114	1		T126	1		T127	1