Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	773879	1			T41	40		T24	7		T66	271
auto[1]	10160142	1			T6	234		T11	508		T8	532
auto[2]	648195	1			T41	23		T24	15		T66	193
auto[3]	10037489	1			T6	259		T11	467		T8	503

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14591324	1			T6	419		T11	630		T8	890
auto[1]	2009289	1			T6	35		T11	153		T8	68
auto[2]	2034006	1			T6	30		T11	149		T8	72
auto[3]	2985086	1			T6	9		T11	43		T8	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8613936

1

T6

493

T11

975

T8

1035

auto[1]

13005769

1

T22

1

T48

1

T49

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	335206	1			T41	36		T24	5		T25	11
auto[0]	auto[0]	auto[1]	34611	1			T41	1		T24	1		T66	3
auto[0]	auto[0]	auto[2]	34389	1			T41	3		T24	1		T66	3
auto[0]	auto[0]	auto[3]	8945	1			T66	263		T138	144		T139	616
auto[0]	auto[1]	auto[0]	3205919	1			T6	204		T11	330		T8	458
auto[0]	auto[1]	auto[1]	342582	1			T6	17		T11	80		T8	28
auto[0]	auto[1]	auto[2]	325619	1			T6	12		T11	75		T8	44
auto[0]	auto[1]	auto[3]	73582	1			T6	1		T11	23		T8	2
auto[0]	auto[2]	auto[0]	287762	1			T41	15		T24	12		T39	17
auto[0]	auto[2]	auto[1]	29701	1			T41	3		T66	27		T39	1
auto[0]	auto[2]	auto[2]	31670	1			T41	4		T24	3		T66	3
auto[0]	auto[2]	auto[3]	7489	1			T41	1		T66	163		T25	2
auto[0]	auto[3]	auto[0]	3158973	1			T6	215		T11	300		T8	432
auto[0]	auto[3]	auto[1]	320639	1			T6	18		T11	73		T8	40
auto[0]	auto[3]	auto[2]	342174	1			T6	18		T11	74		T8	28
auto[0]	auto[3]	auto[3]	74675	1			T6	8		T11	20		T8	3
auto[1]	auto[0]	auto[0]	12165	1			T92	311		T94	389		T95	111
auto[1]	auto[0]	auto[1]	53533	1			T138	1		T92	1338		T94	1821
auto[1]	auto[0]	auto[2]	53609	1			T92	1317		T94	1825		T95	534
auto[1]	auto[0]	auto[3]	241421	1			T66	2		T92	5950		T94	8185
auto[1]	auto[1]	auto[0]	3794631	1			T48	1		T49	2		T140	7
auto[1]	auto[1]	auto[1]	608426	1			T141	4		T142	1		T138	1
auto[1]	auto[1]	auto[2]	601989	1			T141	1		T143	2		T88	5529
auto[1]	auto[1]	auto[3]	1207394	1			T22	1		T141	1		T66	1
auto[1]	auto[2]	auto[0]	8220	1			T92	191		T94	242		T100	1
auto[1]	auto[2]	auto[1]	36160	1			T92	780		T94	1104		T144	3246
auto[1]	auto[2]	auto[2]	44365	1			T92	1286		T94	2038		T95	480
auto[1]	auto[2]	auto[3]	202828	1			T139	2		T92	5723		T94	8799
auto[1]	auto[3]	auto[0]	3788448	1			T49	5		T141	1		T140	6
auto[1]	auto[3]	auto[1]	583637	1			T140	2		T142	1		T143	1
auto[1]	auto[3]	auto[2]	600191	1			T143	2		T145	1		T88	4996
auto[1]	auto[3]	auto[3]	1168752	1			T141	5		T88	459		T89	541