Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	335801114	211570	0	0
ctrl_regwen_rd_A	335801114	5303	0	0
exec_rd_A	335801114	4961	0	0
exec_regwen_rd_A	335801114	5250	0	0
readback_rd_A	335801114	5813	0	0
readback_regwen_rd_A	335801114	3346	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335801114	211570	0	0
T8	44807	0	0	0
T12	25434	1169	0	0
T13	1813	0	0	0
T15	2928	0	0	0
T17	19610	0	0	0
T19	0	5232	0	0
T22	4437	0	0	0
T23	22689	0	0	0
T24	0	5621	0	0
T25	0	4420	0	0
T26	15889	0	0	0
T27	2691	0	0	0
T31	55617	0	0	0
T39	0	2940	0	0
T47	0	3207	0	0
T50	0	2023	0	0
T51	0	7419	0	0
T52	0	4644	0	0
T53	0	4826	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335801114	5303	0	0
T8	44807	0	0	0
T12	25434	131	0	0
T13	1813	0	0	0
T15	2928	0	0	0
T17	19610	0	0	0
T22	4437	0	0	0
T23	22689	0	0	0
T24	0	438	0	0
T25	0	377	0	0
T26	15889	0	0	0
T27	2691	0	0	0
T31	55617	0	0	0
T42	0	225	0	0
T51	0	243	0	0
T52	0	318	0	0
T107	0	244	0	0
T108	0	63	0	0
T109	0	239	0	0
T110	0	133	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335801114	4961	0	0
T8	44807	0	0	0
T12	25434	124	0	0
T13	1813	0	0	0
T15	2928	0	0	0
T17	19610	0	0	0
T22	4437	0	0	0
T23	22689	0	0	0
T24	0	331	0	0
T25	0	284	0	0
T26	15889	0	0	0
T27	2691	0	0	0
T31	55617	0	0	0
T42	0	199	0	0
T51	0	219	0	0
T52	0	301	0	0
T107	0	248	0	0
T108	0	86	0	0
T109	0	270	0	0
T110	0	112	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335801114	5250	0	0
T8	44807	0	0	0
T12	25434	129	0	0
T13	1813	0	0	0
T15	2928	0	0	0
T17	19610	0	0	0
T22	4437	0	0	0
T23	22689	0	0	0
T24	0	426	0	0
T25	0	322	0	0
T26	15889	0	0	0
T27	2691	0	0	0
T31	55617	0	0	0
T42	0	197	0	0
T51	0	248	0	0
T52	0	343	0	0
T107	0	277	0	0
T108	0	98	0	0
T109	0	261	0	0
T110	0	104	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335801114	5813	0	0
T8	44807	0	0	0
T12	25434	136	0	0
T13	1813	0	0	0
T15	2928	0	0	0
T17	19610	0	0	0
T20	0	140	0	0
T22	4437	0	0	0
T23	22689	0	0	0
T24	0	368	0	0
T25	0	219	0	0
T26	15889	0	0	0
T27	2691	0	0	0
T31	55617	0	0	0
T51	0	184	0	0
T52	0	379	0	0
T100	0	72	0	0
T101	0	78	0	0
T102	0	68	0	0
T111	0	109	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335801114	3346	0	0
T8	44807	0	0	0
T12	25434	106	0	0
T13	1813	0	0	0
T15	2928	0	0	0
T17	19610	0	0	0
T22	4437	0	0	0
T23	22689	0	0	0
T24	0	400	0	0
T25	0	322	0	0
T26	15889	0	0	0
T27	2691	0	0	0
T31	55617	0	0	0
T42	0	137	0	0
T51	0	204	0	0
T52	0	336	0	0
T107	0	214	0	0
T108	0	55	0	0
T109	0	241	0	0
T110	0	112	0	0