Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147531071	1			T1	1964		T2	1410		T3	7210
instr_valid_dis	112022678	1			T1	1964		T2	1410		T3	7210
instr_en	24592813	1			T38	81260		T20	14248		T42	41524

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11719009	1			T38	10666		T101	2952		T44	71752
sram_ifetch_valid_disable	111188648	1			T1	1964		T2	1410		T3	7210
sram_ifetch_enable	24623414	1			T25	22880		T38	77150		T42	40448

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147531071	1			T1	1964		T2	1410		T3	7210
hw_debug_en_valid_off	111098658	1			T1	1964		T2	1410		T3	7210
hw_debug_en_on	24672215	1			T25	22880		T38	92002		T42	4386

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111188648	1			T1	1964		T2	1410		T3	7210
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97318445	1			T1	1964		T2	1410		T3	7210
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9860857	1			T38	27976		T20	14248		T42	1076
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4490230	1			T38	10666		T44	71752		T123	4048
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1751234	1			T131	21442		T143	19968		T144	26518
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1898226	1			T38	10666		T44	71752		T127	19914
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4970909	1			T123	12866		T124	55056		T125	25800
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1750389	1			T123	12866		T124	23554		T125	25800
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2088438	1			T124	31502		T126	50934		T131	39286
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8970138	1			T38	33818		T42	342		T101	69098
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3465908	1			T38	22338		T22	19546		T130	14146
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3937320	1			T38	11480		T42	342		T101	69034

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9810626	1			T38	42618		T42	40448		T101	127872
lc_exec_en	10731168	1			T25	22880		T38	58184		T42	4044
valid_exec_dis	107490460	1			T1	1964		T2	1410		T3	7210
invalid_exec_dis	36342423	1			T25	22880		T38	87816		T42	40448