Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.63 99.48 96.05 99.72 100.00 97.29 99.12 98.72


Total tests in report: 1082
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
72.57 72.57 91.74 91.74 72.21 72.21 93.31 93.31 33.33 33.33 81.25 81.25 93.57 93.57 42.60 42.60 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4111822437
86.13 13.56 95.04 3.30 78.86 6.65 94.56 1.25 76.19 42.86 85.75 4.50 95.76 2.19 76.78 34.19 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3715670714
91.95 5.81 98.17 3.13 84.92 6.06 95.46 0.90 100.00 23.81 91.75 6.00 96.20 0.44 77.15 0.37 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.450197874
93.69 1.74 98.52 0.35 88.12 3.21 95.98 0.52 100.00 0.00 94.00 2.25 96.20 0.00 83.00 5.85 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.1484249544
94.77 1.08 98.87 0.35 90.14 2.02 98.16 2.18 100.00 0.00 95.50 1.50 96.78 0.58 83.91 0.91 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.131885442
95.53 0.76 98.87 0.00 90.74 0.59 98.16 0.00 100.00 0.00 95.50 0.00 96.78 0.00 88.67 4.75 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3089535293
95.93 0.40 99.13 0.26 91.69 0.95 98.54 0.38 100.00 0.00 96.50 1.00 96.78 0.00 88.85 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.2904389111
96.26 0.33 99.13 0.00 91.69 0.00 98.54 0.00 100.00 0.00 96.50 0.00 96.93 0.15 91.04 2.19 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3869153929
96.57 0.30 99.13 0.00 92.28 0.59 98.54 0.00 100.00 0.00 96.75 0.25 96.93 0.00 92.32 1.28 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2554366052
96.80 0.24 99.13 0.00 92.28 0.00 98.54 0.00 100.00 0.00 96.75 0.00 96.93 0.00 93.97 1.65 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.972147981
97.00 0.20 99.13 0.00 92.28 0.00 98.54 0.00 100.00 0.00 96.75 0.00 97.81 0.88 94.52 0.55 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.156473948
97.20 0.20 99.13 0.00 92.28 0.00 98.61 0.07 100.00 0.00 96.75 0.00 99.12 1.32 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2438582139
97.36 0.16 99.13 0.00 92.28 0.00 98.61 0.00 100.00 0.00 96.75 0.00 99.12 0.00 95.61 1.10 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3463561233
97.49 0.13 99.22 0.09 92.28 0.00 99.45 0.83 100.00 0.00 96.75 0.00 99.12 0.00 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2051196770
97.61 0.13 99.48 0.26 92.28 0.00 99.45 0.00 100.00 0.00 97.00 0.25 99.12 0.00 95.98 0.37 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1031770117
97.72 0.11 99.48 0.00 92.52 0.24 99.45 0.00 100.00 0.00 97.50 0.50 99.12 0.00 95.98 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3021173544
97.82 0.10 99.48 0.00 92.52 0.00 99.45 0.00 100.00 0.00 97.50 0.00 99.12 0.00 96.71 0.73 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3051751288
97.90 0.08 99.48 0.00 92.52 0.00 99.45 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.26 0.55 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3582832400
97.98 0.08 99.48 0.00 92.52 0.00 99.45 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.81 0.55 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.3405890915
98.04 0.06 99.48 0.00 92.87 0.36 99.51 0.07 100.00 0.00 97.50 0.00 99.12 0.00 97.81 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1394863923
98.09 0.04 99.48 0.00 92.99 0.12 99.51 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.99 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.3845907305
98.11 0.03 99.48 0.00 92.99 0.00 99.51 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.17 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.592308039
98.14 0.03 99.48 0.00 92.99 0.00 99.51 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1546248065
98.16 0.03 99.48 0.00 92.99 0.00 99.51 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2697345482
98.19 0.03 99.48 0.00 92.99 0.00 99.51 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.840848786
98.21 0.02 99.48 0.00 92.99 0.00 99.65 0.14 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.400549703
98.22 0.01 99.48 0.00 92.99 0.00 99.72 0.07 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1433918421

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1262218999
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4230808996
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1710384530
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3456367804
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1441552820
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1906429869
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3629404536
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2833804339
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2939732684
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1762089701
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2162585509
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.65954097
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3307968405
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3737261621
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.9912409
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.507571073
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3618888695
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1196476929
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3873235405
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2335350993
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3318179384
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1959935676
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3113996907
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3749553280
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2037336964
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.722095951
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1441967218
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1368631635
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1858331107
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.884520292
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4131667929
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.738066970
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1975970753
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1613444764
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1532162442
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2981310337
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1929028799
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.203627636
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.446709195
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.322366916
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3023139187
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1797734088
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.353349451
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.40527432
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.999045965
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2797924447
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1643847228
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2068534498
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4033492917
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3285016462
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2749519808
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2182402791
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3780910139
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3123388998
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3665749360
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1840860297
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3593030271
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3383787474
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1750237200
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.181963427
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.208881974
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3824204333
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1372084982
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2355624431
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2057115966
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3074333528
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.859513522
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2524702944
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1577526452
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3099907878
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.321674009
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2549492121
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.227975214
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3993129908
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1817082610
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2729812242
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1981751237
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.913179183
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4137488009
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/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2048985384



Total test records in report: 1082
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.1328475433 Oct 12 04:25:23 AM UTC 24 Oct 12 04:25:28 AM UTC 24 199818661 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3682235141 Oct 12 04:25:31 AM UTC 24 Oct 12 04:25:34 AM UTC 24 66641459 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.140935675 Oct 12 04:25:25 AM UTC 24 Oct 12 04:25:42 AM UTC 24 351245242 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4111822437 Oct 12 04:25:35 AM UTC 24 Oct 12 04:25:47 AM UTC 24 510617275 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2051196770 Oct 12 04:25:52 AM UTC 24 Oct 12 04:25:55 AM UTC 24 28141094 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1333396512 Oct 12 04:25:56 AM UTC 24 Oct 12 04:26:04 AM UTC 24 767804331 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.1592671871 Oct 12 04:26:02 AM UTC 24 Oct 12 04:26:04 AM UTC 24 31975718 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.400549703 Oct 12 04:25:24 AM UTC 24 Oct 12 04:26:07 AM UTC 24 4265860193 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1031770117 Oct 12 04:25:29 AM UTC 24 Oct 12 04:26:08 AM UTC 24 197524575 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1394863923 Oct 12 04:26:07 AM UTC 24 Oct 12 04:26:09 AM UTC 24 56664897 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3656877819 Oct 12 04:25:54 AM UTC 24 Oct 12 04:26:10 AM UTC 24 1754486097 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.4079021490 Oct 12 04:26:07 AM UTC 24 Oct 12 04:26:13 AM UTC 24 655517409 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.450197874 Oct 12 04:26:05 AM UTC 24 Oct 12 04:26:16 AM UTC 24 201590063 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3986646920 Oct 12 04:25:24 AM UTC 24 Oct 12 04:26:20 AM UTC 24 640004013 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.3333406335 Oct 12 04:26:07 AM UTC 24 Oct 12 04:26:22 AM UTC 24 507218156 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1061243687 Oct 12 04:26:15 AM UTC 24 Oct 12 04:26:26 AM UTC 24 121445866 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1657130253 Oct 12 04:26:21 AM UTC 24 Oct 12 04:26:32 AM UTC 24 1974214598 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.803508229 Oct 12 04:26:32 AM UTC 24 Oct 12 04:26:34 AM UTC 24 44361578 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.482410966 Oct 12 04:26:35 AM UTC 24 Oct 12 04:26:40 AM UTC 24 150528185 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.3035375289 Oct 12 04:26:33 AM UTC 24 Oct 12 04:26:42 AM UTC 24 443485258 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.3970673229 Oct 12 04:26:41 AM UTC 24 Oct 12 04:26:44 AM UTC 24 316758972 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2298093618 Oct 12 04:26:16 AM UTC 24 Oct 12 04:26:45 AM UTC 24 151949866 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2104681174 Oct 12 04:26:46 AM UTC 24 Oct 12 04:26:48 AM UTC 24 13595793 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2716767327 Oct 12 04:26:46 AM UTC 24 Oct 12 04:26:52 AM UTC 24 883584322 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.165261348 Oct 12 04:26:11 AM UTC 24 Oct 12 04:26:53 AM UTC 24 7596992142 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2866561046 Oct 12 04:26:50 AM UTC 24 Oct 12 04:27:12 AM UTC 24 699536776 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3387604448 Oct 12 04:27:13 AM UTC 24 Oct 12 04:27:17 AM UTC 24 143843968 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3268358925 Oct 12 04:26:13 AM UTC 24 Oct 12 04:27:17 AM UTC 24 699014457 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1988853158 Oct 12 04:27:18 AM UTC 24 Oct 12 04:27:29 AM UTC 24 220100998 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.3005153492 Oct 12 04:26:54 AM UTC 24 Oct 12 04:27:36 AM UTC 24 876483783 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2554366052 Oct 12 04:27:24 AM UTC 24 Oct 12 04:27:37 AM UTC 24 1598259888 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3273827489 Oct 12 04:27:38 AM UTC 24 Oct 12 04:27:40 AM UTC 24 82798877 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2456433608 Oct 12 04:27:41 AM UTC 24 Oct 12 04:27:52 AM UTC 24 1318920081 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.2904389111 Oct 12 04:27:53 AM UTC 24 Oct 12 04:27:55 AM UTC 24 53707660 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3903596616 Oct 12 04:27:53 AM UTC 24 Oct 12 04:28:01 AM UTC 24 120647408 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2522708367 Oct 12 04:26:11 AM UTC 24 Oct 12 04:28:05 AM UTC 24 1765995207 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1165961625 Oct 12 04:28:06 AM UTC 24 Oct 12 04:28:12 AM UTC 24 1820282283 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3015072975 Oct 12 04:27:20 AM UTC 24 Oct 12 04:28:15 AM UTC 24 381125477 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2148605443 Oct 12 04:28:13 AM UTC 24 Oct 12 04:28:15 AM UTC 24 27518760 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.4010367696 Oct 12 04:28:15 AM UTC 24 Oct 12 04:28:31 AM UTC 24 564573491 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2939074054 Oct 12 04:26:43 AM UTC 24 Oct 12 04:28:41 AM UTC 24 499249013 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2875055366 Oct 12 04:27:56 AM UTC 24 Oct 12 04:28:52 AM UTC 24 1659330758 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3178570002 Oct 12 04:28:53 AM UTC 24 Oct 12 04:28:59 AM UTC 24 179739707 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3362280039 Oct 12 04:28:19 AM UTC 24 Oct 12 04:29:03 AM UTC 24 2044386551 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3763352894 Oct 12 04:29:03 AM UTC 24 Oct 12 04:29:14 AM UTC 24 2579759565 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1184998772 Oct 12 04:28:32 AM UTC 24 Oct 12 04:29:15 AM UTC 24 397062576 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1397585909 Oct 12 04:25:24 AM UTC 24 Oct 12 04:29:19 AM UTC 24 1814039385 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.83247239 Oct 12 04:29:20 AM UTC 24 Oct 12 04:29:22 AM UTC 24 40100577 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.4268388471 Oct 12 04:29:23 AM UTC 24 Oct 12 04:29:40 AM UTC 24 445288267 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3326216742 Oct 12 04:29:41 AM UTC 24 Oct 12 04:29:50 AM UTC 24 388810864 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3776497703 Oct 12 04:29:51 AM UTC 24 Oct 12 04:29:54 AM UTC 24 28588290 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.1484249544 Oct 12 04:25:48 AM UTC 24 Oct 12 04:29:54 AM UTC 24 2441013159 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2578805201 Oct 12 04:27:30 AM UTC 24 Oct 12 04:30:22 AM UTC 24 2451122835 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1808275088 Oct 12 04:30:23 AM UTC 24 Oct 12 04:30:25 AM UTC 24 25406874 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.131885442 Oct 12 04:30:19 AM UTC 24 Oct 12 04:30:26 AM UTC 24 377220473 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.229328147 Oct 12 04:27:12 AM UTC 24 Oct 12 04:30:27 AM UTC 24 6611043497 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3924076752 Oct 12 04:29:00 AM UTC 24 Oct 12 04:30:44 AM UTC 24 176796824 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2414320188 Oct 12 04:30:26 AM UTC 24 Oct 12 04:30:45 AM UTC 24 2682707266 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2658928795 Oct 12 04:30:46 AM UTC 24 Oct 12 04:30:54 AM UTC 24 71029965 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3007846617 Oct 12 04:29:54 AM UTC 24 Oct 12 04:31:01 AM UTC 24 860829567 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3806521359 Oct 12 04:30:57 AM UTC 24 Oct 12 04:31:04 AM UTC 24 269557261 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.537110801 Oct 12 04:29:14 AM UTC 24 Oct 12 04:31:04 AM UTC 24 447136493 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2332616680 Oct 12 04:31:05 AM UTC 24 Oct 12 04:31:11 AM UTC 24 589439493 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.156473948 Oct 12 04:26:23 AM UTC 24 Oct 12 04:31:33 AM UTC 24 5519492901 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.174347554 Oct 12 04:31:34 AM UTC 24 Oct 12 04:31:36 AM UTC 24 89328272 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2909741178 Oct 12 04:30:28 AM UTC 24 Oct 12 04:31:42 AM UTC 24 11299435835 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.746647322 Oct 12 04:31:37 AM UTC 24 Oct 12 04:31:46 AM UTC 24 342636495 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3167039700 Oct 12 04:31:43 AM UTC 24 Oct 12 04:31:48 AM UTC 24 308390506 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_readback_err.669172798 Oct 12 04:31:47 AM UTC 24 Oct 12 04:31:50 AM UTC 24 74764120 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2759197376 Oct 12 04:31:52 AM UTC 24 Oct 12 04:31:55 AM UTC 24 339779769 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2396676579 Oct 12 04:26:14 AM UTC 24 Oct 12 04:31:56 AM UTC 24 18071851379 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.356782139 Oct 12 04:31:56 AM UTC 24 Oct 12 04:31:58 AM UTC 24 39636688 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2578292258 Oct 12 04:31:01 AM UTC 24 Oct 12 04:32:24 AM UTC 24 580866444 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.2333701622 Oct 12 04:31:57 AM UTC 24 Oct 12 04:32:36 AM UTC 24 3625439947 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.579218389 Oct 12 04:32:04 AM UTC 24 Oct 12 04:32:42 AM UTC 24 4267053583 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.155890155 Oct 12 04:32:38 AM UTC 24 Oct 12 04:32:45 AM UTC 24 55286014 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3534358315 Oct 12 04:32:42 AM UTC 24 Oct 12 04:32:47 AM UTC 24 870838446 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.857181024 Oct 12 04:33:19 AM UTC 24 Oct 12 04:33:46 AM UTC 24 94946762 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3809372802 Oct 12 04:31:49 AM UTC 24 Oct 12 04:32:47 AM UTC 24 745729853 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1502560720 Oct 12 04:31:13 AM UTC 24 Oct 12 04:32:54 AM UTC 24 1383029318 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3238164380 Oct 12 04:32:55 AM UTC 24 Oct 12 04:32:57 AM UTC 24 87427695 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3773980452 Oct 12 04:32:58 AM UTC 24 Oct 12 04:33:09 AM UTC 24 4109134621 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3869153929 Oct 12 04:25:25 AM UTC 24 Oct 12 04:33:11 AM UTC 24 39917784788 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3168123415 Oct 12 04:32:37 AM UTC 24 Oct 12 04:33:12 AM UTC 24 195143325 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_readback_err.3367671675 Oct 12 04:33:12 AM UTC 24 Oct 12 04:33:15 AM UTC 24 43606675 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2236845673 Oct 12 04:32:19 AM UTC 24 Oct 12 04:33:17 AM UTC 24 1171429255 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2883947043 Oct 12 04:33:10 AM UTC 24 Oct 12 04:33:18 AM UTC 24 464034826 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3196226600 Oct 12 04:33:18 AM UTC 24 Oct 12 04:33:20 AM UTC 24 39037321 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1987152491 Oct 12 04:30:45 AM UTC 24 Oct 12 04:33:40 AM UTC 24 1549714558 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2676941863 Oct 12 04:28:42 AM UTC 24 Oct 12 04:33:45 AM UTC 24 11288750468 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3715670714 Oct 12 04:33:13 AM UTC 24 Oct 12 04:33:53 AM UTC 24 1081127762 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.2078684113 Oct 12 04:28:26 AM UTC 24 Oct 12 04:34:18 AM UTC 24 16659095055 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3871453757 Oct 12 04:31:50 AM UTC 24 Oct 12 04:34:29 AM UTC 24 20259778776 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.134073639 Oct 12 04:34:30 AM UTC 24 Oct 12 04:34:36 AM UTC 24 684411988 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.4216189772 Oct 12 04:33:26 AM UTC 24 Oct 12 04:34:43 AM UTC 24 3586951212 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1648558722 Oct 12 04:34:19 AM UTC 24 Oct 12 04:34:45 AM UTC 24 338755554 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3189738824 Oct 12 04:33:54 AM UTC 24 Oct 12 04:34:46 AM UTC 24 114617843 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1315563388 Oct 12 04:34:47 AM UTC 24 Oct 12 04:34:49 AM UTC 24 91256359 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2517752171 Oct 12 04:33:46 AM UTC 24 Oct 12 04:34:55 AM UTC 24 1951332543 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2406471337 Oct 12 04:34:56 AM UTC 24 Oct 12 04:35:04 AM UTC 24 2072621344 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_readback_err.2239563586 Oct 12 04:35:04 AM UTC 24 Oct 12 04:35:07 AM UTC 24 31759431 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.877828565 Oct 12 04:34:50 AM UTC 24 Oct 12 04:35:09 AM UTC 24 4347600283 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2322779326 Oct 12 04:35:10 AM UTC 24 Oct 12 04:35:11 AM UTC 24 12357621 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.1363130786 Oct 12 04:35:13 AM UTC 24 Oct 12 04:35:38 AM UTC 24 7165261330 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.3405890915 Oct 12 04:26:29 AM UTC 24 Oct 12 04:36:07 AM UTC 24 2583230320 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2098456393 Oct 12 04:35:06 AM UTC 24 Oct 12 04:36:10 AM UTC 24 379534665 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.632496475 Oct 12 04:35:39 AM UTC 24 Oct 12 04:36:15 AM UTC 24 5233958633 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1080337181 Oct 12 04:36:11 AM UTC 24 Oct 12 04:36:31 AM UTC 24 1026307173 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2574447776 Oct 12 04:34:37 AM UTC 24 Oct 12 04:36:34 AM UTC 24 911675098 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3603757512 Oct 12 04:36:16 AM UTC 24 Oct 12 04:36:42 AM UTC 24 81029729 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2044675822 Oct 12 04:31:12 AM UTC 24 Oct 12 04:36:42 AM UTC 24 52423843668 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2075288408 Oct 12 04:36:49 AM UTC 24 Oct 12 04:36:52 AM UTC 24 115579776 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4256210178 Oct 12 04:36:35 AM UTC 24 Oct 12 04:36:52 AM UTC 24 973546592 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4101076629 Oct 12 04:36:52 AM UTC 24 Oct 12 04:37:01 AM UTC 24 347529646 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_readback_err.855562049 Oct 12 04:37:02 AM UTC 24 Oct 12 04:37:04 AM UTC 24 117201842 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2587366137 Oct 12 04:36:52 AM UTC 24 Oct 12 04:37:05 AM UTC 24 458570049 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.199498156 Oct 12 04:36:32 AM UTC 24 Oct 12 04:37:11 AM UTC 24 308586230 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3048312119 Oct 12 04:37:12 AM UTC 24 Oct 12 04:37:14 AM UTC 24 14652484 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2069340350 Oct 12 04:30:27 AM UTC 24 Oct 12 04:37:17 AM UTC 24 13416168668 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2606385291 Oct 12 04:27:18 AM UTC 24 Oct 12 04:37:19 AM UTC 24 18099451327 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2382471994 Oct 12 04:37:05 AM UTC 24 Oct 12 04:37:20 AM UTC 24 564707809 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3355539689 Oct 12 04:37:15 AM UTC 24 Oct 12 04:38:03 AM UTC 24 401937945 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.972147981 Oct 12 04:26:27 AM UTC 24 Oct 12 04:38:31 AM UTC 24 58764391348 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.4245686021 Oct 12 04:29:15 AM UTC 24 Oct 12 04:38:37 AM UTC 24 6298887766 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.1434119390 Oct 12 04:37:19 AM UTC 24 Oct 12 04:38:38 AM UTC 24 1264044902 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3876526327 Oct 12 04:30:55 AM UTC 24 Oct 12 04:38:39 AM UTC 24 13599873934 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2973069571 Oct 12 04:38:38 AM UTC 24 Oct 12 04:38:43 AM UTC 24 658594755 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.365823291 Oct 12 04:38:38 AM UTC 24 Oct 12 04:39:00 AM UTC 24 207551972 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1630969987 Oct 12 04:39:01 AM UTC 24 Oct 12 04:39:03 AM UTC 24 46184083 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2616192412 Oct 12 04:39:04 AM UTC 24 Oct 12 04:39:13 AM UTC 24 345868977 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1442036465 Oct 12 04:39:15 AM UTC 24 Oct 12 04:39:20 AM UTC 24 97745495 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1852988298 Oct 12 04:39:21 AM UTC 24 Oct 12 04:39:23 AM UTC 24 30445411 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1252362064 Oct 12 04:32:26 AM UTC 24 Oct 12 04:39:27 AM UTC 24 20428521036 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3602111892 Oct 12 04:39:24 AM UTC 24 Oct 12 04:39:32 AM UTC 24 396189214 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3402740017 Oct 12 04:39:33 AM UTC 24 Oct 12 04:39:36 AM UTC 24 21904303 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.69549614 Oct 12 04:34:45 AM UTC 24 Oct 12 04:39:47 AM UTC 24 1402477830 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1181030126 Oct 12 04:38:03 AM UTC 24 Oct 12 04:39:54 AM UTC 24 244929076 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2444239562 Oct 12 04:38:32 AM UTC 24 Oct 12 04:40:06 AM UTC 24 137013528 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2381338949 Oct 12 04:32:10 AM UTC 24 Oct 12 04:40:15 AM UTC 24 21485206359 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1324797394 Oct 12 04:36:48 AM UTC 24 Oct 12 04:40:22 AM UTC 24 5526824540 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1387146548 Oct 12 04:40:16 AM UTC 24 Oct 12 04:40:28 AM UTC 24 116868358 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3756924151 Oct 12 04:40:04 AM UTC 24 Oct 12 04:40:34 AM UTC 24 5172485195 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1227242015 Oct 12 04:40:28 AM UTC 24 Oct 12 04:40:38 AM UTC 24 1071299629 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2048985384 Oct 12 04:40:23 AM UTC 24 Oct 12 04:40:50 AM UTC 24 177184542 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1433918421 Oct 12 04:25:35 AM UTC 24 Oct 12 04:40:55 AM UTC 24 15090396750 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3298077067 Oct 12 04:40:56 AM UTC 24 Oct 12 04:40:58 AM UTC 24 188132941 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.976051335 Oct 12 04:39:33 AM UTC 24 Oct 12 04:41:02 AM UTC 24 665040454 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.253598013 Oct 12 04:26:53 AM UTC 24 Oct 12 04:41:08 AM UTC 24 3799517609 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3729312510 Oct 12 04:41:03 AM UTC 24 Oct 12 04:41:11 AM UTC 24 647558464 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1030873721 Oct 12 04:40:59 AM UTC 24 Oct 12 04:41:12 AM UTC 24 176365056 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3170763383 Oct 12 04:38:44 AM UTC 24 Oct 12 04:41:12 AM UTC 24 10379027118 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.3986608078 Oct 12 04:41:09 AM UTC 24 Oct 12 04:41:12 AM UTC 24 116926437 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3580874166 Oct 12 04:39:47 AM UTC 24 Oct 12 04:41:15 AM UTC 24 7689161846 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3084078148 Oct 12 04:41:13 AM UTC 24 Oct 12 04:41:15 AM UTC 24 33142486 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1118508635 Oct 12 04:33:41 AM UTC 24 Oct 12 04:41:23 AM UTC 24 19360544883 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.490771500 Oct 12 04:32:46 AM UTC 24 Oct 12 04:41:32 AM UTC 24 4436898457 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.480426181 Oct 12 04:35:21 AM UTC 24 Oct 12 04:41:48 AM UTC 24 14326547983 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3955495879 Oct 12 04:26:45 AM UTC 24 Oct 12 04:42:09 AM UTC 24 9876391299 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.2913907625 Oct 12 04:41:17 AM UTC 24 Oct 12 04:42:19 AM UTC 24 9790224593 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4244684125 Oct 12 04:31:06 AM UTC 24 Oct 12 04:42:19 AM UTC 24 10046330481 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3965665375 Oct 12 04:36:08 AM UTC 24 Oct 12 04:42:23 AM UTC 24 3821755437 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1813087177 Oct 12 04:28:02 AM UTC 24 Oct 12 04:42:24 AM UTC 24 67005033301 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2270828306 Oct 12 04:42:20 AM UTC 24 Oct 12 04:42:28 AM UTC 24 2259049960 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.535479612 Oct 12 04:42:20 AM UTC 24 Oct 12 04:42:28 AM UTC 24 64258172 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2399698797 Oct 12 04:42:29 AM UTC 24 Oct 12 04:42:31 AM UTC 24 86407680 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3946750666 Oct 12 04:33:47 AM UTC 24 Oct 12 04:42:35 AM UTC 24 149714371052 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4024967566 Oct 12 04:38:09 AM UTC 24 Oct 12 04:42:37 AM UTC 24 3218950510 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_readback_err.452107332 Oct 12 04:42:38 AM UTC 24 Oct 12 04:42:41 AM UTC 24 35964136 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1147796621 Oct 12 04:42:36 AM UTC 24 Oct 12 04:42:46 AM UTC 24 2429538739 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2379597576 Oct 12 04:42:32 AM UTC 24 Oct 12 04:42:46 AM UTC 24 335629655 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2180469402 Oct 12 04:41:33 AM UTC 24 Oct 12 04:42:48 AM UTC 24 724281595 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.976856446 Oct 12 04:42:47 AM UTC 24 Oct 12 04:42:50 AM UTC 24 20891612 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1892450761 Oct 12 04:36:11 AM UTC 24 Oct 12 04:42:51 AM UTC 24 43931491489 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.408639222 Oct 12 04:40:07 AM UTC 24 Oct 12 04:42:53 AM UTC 24 5657893547 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.168138542 Oct 12 04:41:13 AM UTC 24 Oct 12 04:42:59 AM UTC 24 738931908 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.3278438608 Oct 12 04:42:49 AM UTC 24 Oct 12 04:43:04 AM UTC 24 592828885 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3959130021 Oct 12 04:42:52 AM UTC 24 Oct 12 04:43:14 AM UTC 24 264100116 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2672848374 Oct 12 04:42:10 AM UTC 24 Oct 12 04:43:15 AM UTC 24 499023963 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1581730756 Oct 12 04:37:20 AM UTC 24 Oct 12 04:43:18 AM UTC 24 2887763359 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.4254138444 Oct 12 04:43:14 AM UTC 24 Oct 12 04:43:18 AM UTC 24 39420684 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2405609896 Oct 12 04:43:19 AM UTC 24 Oct 12 04:43:25 AM UTC 24 422822358 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2274269805 Oct 12 04:43:00 AM UTC 24 Oct 12 04:43:42 AM UTC 24 152082677 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1247496450 Oct 12 04:43:50 AM UTC 24 Oct 12 04:43:52 AM UTC 24 29368651 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.2617442630 Oct 12 04:27:38 AM UTC 24 Oct 12 04:44:04 AM UTC 24 21558419225 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3908596928 Oct 12 04:42:24 AM UTC 24 Oct 12 04:44:04 AM UTC 24 546594338 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3764890063 Oct 12 04:43:53 AM UTC 24 Oct 12 04:44:04 AM UTC 24 1707811694 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_readback_err.3384362055 Oct 12 04:44:05 AM UTC 24 Oct 12 04:44:07 AM UTC 24 31122864 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1405648613 Oct 12 04:44:04 AM UTC 24 Oct 12 04:44:10 AM UTC 24 582100961 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3769600519 Oct 12 04:44:11 AM UTC 24 Oct 12 04:44:13 AM UTC 24 19891582 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.258657059 Oct 12 04:43:16 AM UTC 24 Oct 12 04:44:40 AM UTC 24 432552292 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3069644239 Oct 12 04:33:22 AM UTC 24 Oct 12 04:44:41 AM UTC 24 47724031666 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.840848786 Oct 12 04:44:05 AM UTC 24 Oct 12 04:44:51 AM UTC 24 4773050162 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.469235324 Oct 12 04:39:55 AM UTC 24 Oct 12 04:44:52 AM UTC 24 31581515835 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1819007768 Oct 12 04:44:51 AM UTC 24 Oct 12 04:44:57 AM UTC 24 136658372 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2550192246 Oct 12 04:25:43 AM UTC 24 Oct 12 04:45:07 AM UTC 24 92786299587 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2871215381 Oct 12 04:44:58 AM UTC 24 Oct 12 04:45:11 AM UTC 24 129501782 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.242553547 Oct 12 04:41:11 AM UTC 24 Oct 12 04:45:12 AM UTC 24 2748191383 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2131658251 Oct 12 04:45:12 AM UTC 24 Oct 12 04:45:20 AM UTC 24 1080760399 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.3306614571 Oct 12 04:44:41 AM UTC 24 Oct 12 04:45:39 AM UTC 24 2077196325 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2114335092 Oct 12 04:45:39 AM UTC 24 Oct 12 04:45:42 AM UTC 24 94165829 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4081681969 Oct 12 04:45:08 AM UTC 24 Oct 12 04:45:45 AM UTC 24 101037093 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1108780394 Oct 12 04:45:46 AM UTC 24 Oct 12 04:45:50 AM UTC 24 64350723 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2540797377 Oct 12 04:44:14 AM UTC 24 Oct 12 04:45:51 AM UTC 24 739246304 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.69887692 Oct 12 04:45:43 AM UTC 24 Oct 12 04:45:52 AM UTC 24 227135976 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_readback_err.865133198 Oct 12 04:45:52 AM UTC 24 Oct 12 04:45:55 AM UTC 24 40303779 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1006111312 Oct 12 04:45:55 AM UTC 24 Oct 12 04:45:57 AM UTC 24 12045641 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3811785378 Oct 12 04:29:20 AM UTC 24 Oct 12 04:46:04 AM UTC 24 9848199254 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1222103034 Oct 12 04:27:37 AM UTC 24 Oct 12 04:46:18 AM UTC 24 28611458064 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2697345482 Oct 12 04:26:08 AM UTC 24 Oct 12 04:46:28 AM UTC 24 33691784151 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.2454512179 Oct 12 04:34:46 AM UTC 24 Oct 12 04:46:30 AM UTC 24 5268216052 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.1303532501 Oct 12 04:45:58 AM UTC 24 Oct 12 04:46:38 AM UTC 24 1415264108 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1465356698 Oct 12 04:44:41 AM UTC 24 Oct 12 04:46:50 AM UTC 24 21114097868 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.374602269 Oct 12 04:41:48 AM UTC 24 Oct 12 04:46:55 AM UTC 24 22587198424 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3792091950 Oct 12 04:46:31 AM UTC 24 Oct 12 04:46:56 AM UTC 24 1560368015 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3389575666 Oct 12 04:46:56 AM UTC 24 Oct 12 04:46:59 AM UTC 24 123254089 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2865888114 Oct 12 04:46:56 AM UTC 24 Oct 12 04:47:11 AM UTC 24 1314003249 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.57405142 Oct 12 04:40:35 AM UTC 24 Oct 12 04:47:23 AM UTC 24 7530021528 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3783706150 Oct 12 04:45:52 AM UTC 24 Oct 12 04:47:28 AM UTC 24 1793342990 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4007326296 Oct 12 04:47:29 AM UTC 24 Oct 12 04:47:31 AM UTC 24 117064584 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.722751750 Oct 12 04:41:24 AM UTC 24 Oct 12 04:47:36 AM UTC 24 3757816187 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2733679315 Oct 12 04:47:32 AM UTC 24 Oct 12 04:47:39 AM UTC 24 564799648 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1200973401 Oct 12 04:42:54 AM UTC 24 Oct 12 04:47:40 AM UTC 24 5235720944 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2146842114 Oct 12 04:47:37 AM UTC 24 Oct 12 04:47:41 AM UTC 24 224499246 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.845811879 Oct 12 04:46:20 AM UTC 24 Oct 12 04:47:42 AM UTC 24 3246582089 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.794907980 Oct 12 04:44:54 AM UTC 24 Oct 12 04:47:42 AM UTC 24 22165500151 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3722023693 Oct 12 04:47:40 AM UTC 24 Oct 12 04:47:43 AM UTC 24 47242105 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1104806058 Oct 12 04:47:42 AM UTC 24 Oct 12 04:47:44 AM UTC 24 12073672 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.788653266 Oct 12 04:47:44 AM UTC 24 Oct 12 04:47:52 AM UTC 24 804659523 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.787007921 Oct 12 04:36:43 AM UTC 24 Oct 12 04:47:59 AM UTC 24 16315520710 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1118721786 Oct 12 04:46:51 AM UTC 24 Oct 12 04:48:03 AM UTC 24 432074432 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3043140517 Oct 12 04:40:39 AM UTC 24 Oct 12 04:48:05 AM UTC 24 2401516563 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2794995322 Oct 12 04:48:05 AM UTC 24 Oct 12 04:48:36 AM UTC 24 96058313 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2808934460 Oct 12 04:47:46 AM UTC 24 Oct 12 04:48:46 AM UTC 24 1848276150 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2637657553 Oct 12 04:48:37 AM UTC 24 Oct 12 04:48:51 AM UTC 24 3871378580 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1797940740 Oct 12 04:48:00 AM UTC 24 Oct 12 04:49:00 AM UTC 24 1056651826 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.781605065 Oct 12 04:48:14 AM UTC 24 Oct 12 04:49:24 AM UTC 24 126579071 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2604240438 Oct 12 04:49:24 AM UTC 24 Oct 12 04:49:27 AM UTC 24 44227383 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1799092202 Oct 12 04:37:18 AM UTC 24 Oct 12 04:49:34 AM UTC 24 10116490544 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3624553889 Oct 12 04:49:28 AM UTC 24 Oct 12 04:49:43 AM UTC 24 443572086 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.121630064 Oct 12 04:49:35 AM UTC 24 Oct 12 04:49:43 AM UTC 24 512571680 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_readback_err.536914925 Oct 12 04:49:44 AM UTC 24 Oct 12 04:49:46 AM UTC 24 27676780 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3489067668 Oct 12 04:49:49 AM UTC 24 Oct 12 04:49:51 AM UTC 24 49923416 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1956306336 Oct 12 04:49:44 AM UTC 24 Oct 12 04:49:56 AM UTC 24 1099070694 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1910187191 Oct 12 04:42:25 AM UTC 24 Oct 12 04:50:00 AM UTC 24 7351409438 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1419539922 Oct 12 04:31:59 AM UTC 24 Oct 12 04:50:04 AM UTC 24 165823959044 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.1872231760 Oct 12 04:42:29 AM UTC 24 Oct 12 04:50:15 AM UTC 24 1207048482 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.3913733415 Oct 12 04:49:53 AM UTC 24 Oct 12 04:50:16 AM UTC 24 249771704 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3022273165 Oct 12 04:47:40 AM UTC 24 Oct 12 04:50:22 AM UTC 24 1300352513 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2148157382 Oct 12 04:50:15 AM UTC 24 Oct 12 04:50:39 AM UTC 24 1034407704 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.3393954015 Oct 12 04:50:01 AM UTC 24 Oct 12 04:50:53 AM UTC 24 1930821091 ps