Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	341014846	186221	0	0
ctrl_regwen_rd_A	341014846	2402	0	0
exec_rd_A	341014846	2281	0	0
exec_regwen_rd_A	341014846	2348	0	0
readback_rd_A	341014846	4048	0	0
readback_regwen_rd_A	341014846	856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341014846	186221	0	0
T9	7048	0	0	0
T21	0	7262	0	0
T28	128791	3507	0	0
T29	0	2154	0	0
T30	0	2314	0	0
T33	2782	0	0	0
T46	0	1735	0	0
T47	28783	0	0	0
T50	0	2046	0	0
T51	70875	0	0	0
T56	0	6213	0	0
T61	9322	0	0	0
T62	4470	0	0	0
T64	0	9857	0	0
T66	0	1977	0	0
T67	0	3170	0	0
T68	19338	0	0	0
T69	8348	0	0	0
T70	84178	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341014846	2402	0	0
T74	0	13	0	0
T81	0	2	0	0
T122	0	126	0	0
T127	25963	112	0	0
T128	0	288	0	0
T129	0	118	0	0
T130	0	247	0	0
T131	0	180	0	0
T132	0	77	0	0
T133	0	28	0	0
T134	53160	0	0	0
T135	159949	0	0	0
T136	15805	0	0	0
T137	452859	0	0	0
T138	98229	0	0	0
T139	960837	0	0	0
T140	390148	0	0	0
T141	286969	0	0	0
T142	8048	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341014846	2281	0	0
T74	0	16	0	0
T81	0	1	0	0
T122	0	148	0	0
T127	25963	50	0	0
T128	0	238	0	0
T129	0	77	0	0
T130	0	218	0	0
T131	0	191	0	0
T132	0	124	0	0
T133	0	21	0	0
T134	53160	0	0	0
T135	159949	0	0	0
T136	15805	0	0	0
T137	452859	0	0	0
T138	98229	0	0	0
T139	960837	0	0	0
T140	390148	0	0	0
T141	286969	0	0	0
T142	8048	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341014846	2348	0	0
T74	0	6	0	0
T81	0	3	0	0
T122	0	109	0	0
T127	25963	99	0	0
T128	0	246	0	0
T129	0	94	0	0
T130	0	292	0	0
T131	0	157	0	0
T132	0	51	0	0
T133	0	40	0	0
T134	53160	0	0	0
T135	159949	0	0	0
T136	15805	0	0	0
T137	452859	0	0	0
T138	98229	0	0	0
T139	960837	0	0	0
T140	390148	0	0	0
T141	286969	0	0	0
T142	8048	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341014846	4048	0	0
T20	0	44	0	0
T24	55972	0	0	0
T65	10735	0	0	0
T127	0	61	0	0
T143	191759	58	0	0
T144	0	110	0	0
T145	0	7	0	0
T146	0	14	0	0
T147	0	159	0	0
T148	0	41	0	0
T149	0	9	0	0
T150	0	40	0	0
T151	105152	0	0	0
T152	302085	0	0	0
T153	1954	0	0	0
T154	3925	0	0	0
T155	15102	0	0	0
T156	13035	0	0	0
T157	742	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341014846	856	0	0
T127	25963	75	0	0
T128	0	227	0	0
T129	0	46	0	0
T130	0	194	0	0
T131	0	93	0	0
T132	0	52	0	0
T134	53160	0	0	0
T135	159949	0	0	0
T136	15805	0	0	0
T137	452859	0	0	0
T138	98229	0	0	0
T139	960837	0	0	0
T140	390148	0	0	0
T141	286969	0	0	0
T142	8048	0	0	0
T158	0	34	0	0
T159	0	32	0	0
T160	0	10	0	0
T161	0	24	0	0