Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	152656714	1			T2	184		T4	6142		T5	3996
instr_valid_dis	116039707	1			T2	184		T4	6142		T5	3996
instr_en	28763069	1			T19	77244		T31	55826		T123	270144

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12485008	1			T28	19278		T19	9712		T123	39170
sram_ifetch_valid_disable	114237399	1			T2	184		T4	6142		T5	3996
sram_ifetch_enable	25934307	1			T19	32334		T31	20000		T123	93472

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	152656714	1			T2	184		T4	6142		T5	3996
hw_debug_en_valid_off	114636029	1			T2	184		T4	6142		T5	3996
hw_debug_en_on	26039645	1			T19	95624		T31	84392		T123	101210

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114237399	1			T2	184		T4	6142		T5	3996
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99685347	1			T2	184		T4	6142		T5	3996
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11690647	1			T19	59064		T31	55826		T123	137502
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5027746	1			T123	34974		T176	374		T44	20394
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2160266	1			T176	374		T45	50382		T177	68100
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2329128	1			T123	34974		T44	20394		T184	4778
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5059612	1			T19	9712		T123	4196		T44	22222
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2291934	1			T19	9712		T45	12378		T185	53464
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2117644	1			T123	4196		T44	22222		T45	11222
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10203805	1			T19	70272		T31	64392		T123	67430
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4172566	1			T19	11306		T31	8566		T176	31076
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4736207	1			T19	58966		T31	55826		T123	67430

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11612046	1			T19	18180		T123	93472		T176	101778
lc_exec_en	10776228	1			T19	15640		T31	20000		T123	29584
valid_exec_dis	110045184	1			T2	184		T4	6142		T5	3996
invalid_exec_dis	38419315	1			T28	19278		T19	42046		T31	20000