Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148780808	1			T1	74		T4	1256		T5	1870
instr_valid_dis	114325117	1			T1	74		T4	1256		T5	1870
instr_en	23514091	1			T28	12168		T29	104278		T30	62

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Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11834342	1			T29	81084		T30	38682		T20	43032
sram_ifetch_valid_disable	115854661	1			T1	74		T4	1256		T5	1870
sram_ifetch_enable	21091805	1			T28	7074		T31	34798		T29	94952

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148780808	1			T1	74		T4	1256		T5	1870
hw_debug_en_valid_off	114893219	1			T1	74		T4	1256		T5	1870
hw_debug_en_on	22806171	1			T31	1808		T29	18818		T30	62

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115854661	1			T1	74		T4	1256		T5	1870
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102049211	1			T1	74		T4	1256		T5	1870
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9684723	1			T28	8826		T29	20000		T20	123798
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4775746	1			T29	69834		T126	59598		T132	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1914844	1			T132	20000		T146	11250		T147	4204
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1822400	1			T29	69834		T126	59598		T133	105164
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4783970	1			T20	9294		T63	71832		T21	52020
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1642784	1			T134	68		T127	17374		T135	25250
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1911680	1			T20	9294		T63	71832		T21	52020
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9608284	1			T20	13472		T68	16122		T63	96362
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3689404	1			T68	16122		T126	37536		T134	23440
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4381958	1			T20	12478		T63	96362		T125	73076

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9227642	1			T28	3342		T29	14444		T30	62
lc_exec_en	8413917	1			T31	1808		T29	18818		T30	62
valid_exec_dis	108899981	1			T1	74		T4	1256		T5	1870
invalid_exec_dis	32926147	1			T28	7074		T31	34798		T29	176036