Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.98 99.16 94.49 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1024
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.47 83.47 96.95 96.95 83.14 83.14 91.47 91.47 80.95 80.95 89.37 89.37 94.69 94.69 47.71 47.71 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.851908330
87.83 4.36 98.47 1.53 85.51 2.38 92.82 1.35 95.24 14.29 92.75 3.38 95.13 0.44 54.84 7.13 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3953752583
91.94 4.11 98.56 0.08 86.22 0.71 94.49 1.66 100.00 4.76 93.72 0.97 95.43 0.29 75.14 20.29 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1232858980
93.25 1.31 98.90 0.34 88.24 2.02 95.60 1.11 100.00 0.00 95.17 1.45 96.61 1.18 78.24 3.11 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2143557783
94.39 1.14 99.07 0.17 89.90 1.66 95.67 0.07 100.00 0.00 96.14 0.97 96.61 0.00 83.36 5.12 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.1202055391
95.12 0.73 99.07 0.00 90.26 0.36 95.67 0.00 100.00 0.00 96.14 0.00 96.61 0.00 88.12 4.75 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2451314622
95.60 0.48 99.07 0.00 90.26 0.00 96.53 0.87 100.00 0.00 96.14 0.00 97.64 1.03 89.58 1.46 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2550474902
95.97 0.36 99.07 0.00 90.50 0.24 98.47 1.94 100.00 0.00 96.14 0.00 97.64 0.00 89.95 0.37 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.759660118
96.31 0.34 99.07 0.00 90.50 0.00 98.47 0.00 100.00 0.00 96.14 0.00 97.64 0.00 92.32 2.38 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3815227630
96.57 0.26 99.07 0.00 90.74 0.24 98.54 0.07 100.00 0.00 96.14 0.00 98.82 1.18 92.69 0.37 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2718891129
96.77 0.20 99.07 0.00 90.86 0.12 98.54 0.00 100.00 0.00 96.14 0.00 98.82 0.00 93.97 1.28 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3840063225
96.91 0.14 99.15 0.08 90.86 0.00 99.45 0.90 100.00 0.00 96.14 0.00 98.82 0.00 93.97 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3543619052
97.03 0.12 99.15 0.00 90.97 0.12 99.58 0.14 100.00 0.00 96.14 0.00 98.82 0.00 94.52 0.55 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.2134342351
97.13 0.10 99.15 0.00 90.97 0.00 99.58 0.00 100.00 0.00 96.14 0.00 98.82 0.00 95.25 0.73 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3931444002
97.22 0.09 99.15 0.00 91.33 0.36 99.65 0.07 100.00 0.00 96.14 0.00 98.82 0.00 95.43 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1829394964
97.30 0.08 99.15 0.00 91.33 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.82 0.00 95.98 0.55 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.182994878
97.37 0.08 99.15 0.00 91.33 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.82 0.00 96.53 0.55 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2683552823
97.43 0.05 99.15 0.00 91.33 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.82 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2390300940
97.46 0.04 99.15 0.00 91.33 0.00 99.72 0.07 100.00 0.00 96.14 0.00 98.82 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4105015455
97.49 0.03 99.15 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.82 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.686163307
97.51 0.03 99.15 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.82 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1575066244
97.54 0.02 99.15 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2347560794
97.56 0.02 99.15 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3415147694

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1281376111
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.195801551
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.119992164
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.148997704
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3408614355
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1398861245
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3089599395
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3457701861
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.638358473
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3549703247
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1559928772
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2167305625
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3375988967
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1764242042
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.878410272
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1405738668
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2841488074
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2230064948
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2853229974
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3380578176
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2761672994
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1764952584
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1276111095
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2140299491
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1440512379
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3266411522
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2366469359
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.670034533
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2341729163
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.65352362
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4071828169
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3465725410
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4028574806
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2472600930
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2864414562
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2308264243
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1220492584
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2440333161
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2805238177
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3634407232
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4002229923
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3805672929
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1826601915
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.324280758
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.895675493
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.653636015
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3730337364
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4012536299
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.830947339
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2824567773
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3754940031
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.815838527
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4211845501
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.681254766
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.310747470
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3293105110
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1283948529
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2924297612
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3344274919
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4045987412
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3939706321
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1847961234
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3188456627
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.549785744
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3561462290
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1784071875
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2191778657
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2683975300
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3808281670
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3547137771
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3475860445
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1738576236
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.468526221
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1235775570
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2304281792
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.856520892
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2854881639
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4018169975
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3331350321
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1529531365
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2721853702
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1335284795
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2307977598
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3508293086
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1547783789
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1788878745
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3558839029
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2286636387
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3003139249
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.925801806
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1465124158
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.26968303
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2617222028
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3916770715
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1933702891
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.736992399
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2503869395
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2440543801
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1330972394
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/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1318156832
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2097001509
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1868373646
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2898873716
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3581354173
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3984857710
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.641638310
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1811371936
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3452665456
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1582612166
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.43230243
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1187978459
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1089995200
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3930662875
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.4062205602
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.1735954414
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2874941910
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3052706157
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.57600358
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.560082957
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3207274056
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.342373124
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.149187131
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.118817499
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3601361990
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3898319345
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2291977351
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2642495905
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1153967385
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4060722567
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2641411590
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.510289507
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2095663440
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2281124
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1877095070
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3928416920
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3819838791
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1675445614
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.855872578
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1658582281
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2595379636
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2380617489
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1932813702
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.4189025624
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.475879863
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4014100661
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1867388124
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.362157241
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3489490217
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.54606371
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.911889546
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1300555938
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3068416226
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3546240823
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1023650836
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3078844271
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2161259565
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2032277054
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4254705199
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2533466344
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1684354893
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3165500875
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.478238729
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3332744241
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2170413628
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2298266574
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.409281974
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1413117401
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.144411144
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1396619905
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2168345980
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1913842309
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2500158636
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1214852513
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.839432264
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2134333510
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.65073485
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1914322935
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2739407674
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1089411772
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1507275582
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4294248486
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3486837416
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1018533294



Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3510788219 Feb 08 11:36:45 AM UTC 25 Feb 08 11:36:48 AM UTC 25 30123917 ps
T2 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2650964618 Feb 08 11:36:46 AM UTC 25 Feb 08 11:36:49 AM UTC 25 32300978 ps
T3 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3415147694 Feb 08 11:36:48 AM UTC 25 Feb 08 11:36:50 AM UTC 25 16702111 ps
T4 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3699137770 Feb 08 11:36:46 AM UTC 25 Feb 08 11:36:51 AM UTC 25 153636539 ps
T5 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2550474902 Feb 08 11:36:47 AM UTC 25 Feb 08 11:36:53 AM UTC 25 61527357 ps
T12 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.418131009 Feb 08 11:36:46 AM UTC 25 Feb 08 11:36:54 AM UTC 25 291619860 ps
T6 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2143557783 Feb 08 11:36:48 AM UTC 25 Feb 08 11:36:54 AM UTC 25 691049542 ps
T10 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1461834259 Feb 08 11:36:45 AM UTC 25 Feb 08 11:36:56 AM UTC 25 333406562 ps
T11 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.851908330 Feb 08 11:36:48 AM UTC 25 Feb 08 11:36:57 AM UTC 25 3751476038 ps
T13 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2813625930 Feb 08 11:36:53 AM UTC 25 Feb 08 11:36:59 AM UTC 25 427924351 ps
T7 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3587481184 Feb 08 11:36:55 AM UTC 25 Feb 08 11:37:00 AM UTC 25 198611717 ps
T32 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3454292424 Feb 08 11:36:57 AM UTC 25 Feb 08 11:37:00 AM UTC 25 25292222 ps
T36 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3164987795 Feb 08 11:36:51 AM UTC 25 Feb 08 11:37:01 AM UTC 25 117710734 ps
T37 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.625587641 Feb 08 11:36:54 AM UTC 25 Feb 08 11:37:03 AM UTC 25 166295159 ps
T14 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3319886168 Feb 08 11:37:02 AM UTC 25 Feb 08 11:37:04 AM UTC 25 33324117 ps
T38 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3535764521 Feb 08 11:36:59 AM UTC 25 Feb 08 11:37:05 AM UTC 25 463662702 ps
T17 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.565506347 Feb 08 11:37:01 AM UTC 25 Feb 08 11:37:05 AM UTC 25 586803767 ps
T40 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.89116546 Feb 08 11:36:58 AM UTC 25 Feb 08 11:37:06 AM UTC 25 392969339 ps
T41 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3692006688 Feb 08 11:37:02 AM UTC 25 Feb 08 11:37:14 AM UTC 25 187671602 ps
T39 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.2421760538 Feb 08 11:36:49 AM UTC 25 Feb 08 11:37:16 AM UTC 25 936945866 ps
T139 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1809939690 Feb 08 11:36:46 AM UTC 25 Feb 08 11:37:17 AM UTC 25 245797423 ps
T156 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2425178271 Feb 08 11:37:15 AM UTC 25 Feb 08 11:37:18 AM UTC 25 36914820 ps
T19 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.348572765 Feb 08 11:36:50 AM UTC 25 Feb 08 11:37:20 AM UTC 25 377730143 ps
T8 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3953752583 Feb 08 11:37:16 AM UTC 25 Feb 08 11:37:23 AM UTC 25 920186935 ps
T33 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3401470576 Feb 08 11:37:22 AM UTC 25 Feb 08 11:37:25 AM UTC 25 28658861 ps
T46 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1888126378 Feb 08 11:37:06 AM UTC 25 Feb 08 11:37:28 AM UTC 25 2226746067 ps
T47 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.6673696 Feb 08 11:37:25 AM UTC 25 Feb 08 11:37:31 AM UTC 25 116145823 ps
T152 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1403511878 Feb 08 11:36:44 AM UTC 25 Feb 08 11:37:32 AM UTC 25 4502902115 ps
T52 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3338394202 Feb 08 11:37:23 AM UTC 25 Feb 08 11:37:33 AM UTC 25 229460754 ps
T153 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3611254851 Feb 08 11:36:44 AM UTC 25 Feb 08 11:37:33 AM UTC 25 10820393380 ps
T15 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4285809442 Feb 08 11:37:33 AM UTC 25 Feb 08 11:37:35 AM UTC 25 49281592 ps
T18 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2945425743 Feb 08 11:37:32 AM UTC 25 Feb 08 11:37:37 AM UTC 25 238111353 ps
T48 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2885458847 Feb 08 11:36:44 AM UTC 25 Feb 08 11:37:38 AM UTC 25 2970849534 ps
T155 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.265692684 Feb 08 11:37:15 AM UTC 25 Feb 08 11:37:45 AM UTC 25 96139069 ps
T157 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2881782334 Feb 08 11:37:38 AM UTC 25 Feb 08 11:37:51 AM UTC 25 793164627 ps
T64 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.1752301149 Feb 08 11:37:34 AM UTC 25 Feb 08 11:37:53 AM UTC 25 1477654575 ps
T154 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3543619052 Feb 08 11:38:05 AM UTC 25 Feb 08 11:38:08 AM UTC 25 85457371 ps
T9 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.759660118 Feb 08 11:37:54 AM UTC 25 Feb 08 11:38:08 AM UTC 25 678810982 ps
T26 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4105015455 Feb 08 11:36:59 AM UTC 25 Feb 08 11:38:17 AM UTC 25 1791350649 ps
T83 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1529481775 Feb 08 11:38:10 AM UTC 25 Feb 08 11:38:19 AM UTC 25 163850638 ps
T53 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.915324400 Feb 08 11:38:10 AM UTC 25 Feb 08 11:38:25 AM UTC 25 1757445731 ps
T142 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1857314149 Feb 08 11:37:53 AM UTC 25 Feb 08 11:38:28 AM UTC 25 219431477 ps
T149 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.952466249 Feb 08 11:37:36 AM UTC 25 Feb 08 11:38:30 AM UTC 25 7574524460 ps
T34 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.336283098 Feb 08 11:38:26 AM UTC 25 Feb 08 11:38:30 AM UTC 25 173981773 ps
T16 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1829394964 Feb 08 11:38:29 AM UTC 25 Feb 08 11:38:31 AM UTC 25 15864886 ps
T27 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.986446021 Feb 08 11:38:18 AM UTC 25 Feb 08 11:38:32 AM UTC 25 2306769475 ps
T42 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2683552823 Feb 08 11:36:55 AM UTC 25 Feb 08 11:38:41 AM UTC 25 6023037974 ps
T158 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.281336505 Feb 08 11:37:52 AM UTC 25 Feb 08 11:38:43 AM UTC 25 458945227 ps
T151 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.3602431053 Feb 08 11:38:31 AM UTC 25 Feb 08 11:38:57 AM UTC 25 1330617409 ps
T159 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.1841092181 Feb 08 11:37:05 AM UTC 25 Feb 08 11:39:03 AM UTC 25 19220089903 ps
T28 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1232858980 Feb 08 11:37:25 AM UTC 25 Feb 08 11:39:06 AM UTC 25 1590317579 ps
T23 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3119315699 Feb 08 11:39:04 AM UTC 25 Feb 08 11:39:18 AM UTC 25 3744191106 ps
T144 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1852675830 Feb 08 11:38:41 AM UTC 25 Feb 08 11:39:40 AM UTC 25 183972188 ps
T160 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1691510398 Feb 08 11:39:41 AM UTC 25 Feb 08 11:39:44 AM UTC 25 89997981 ps
T97 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3803729485 Feb 08 11:37:07 AM UTC 25 Feb 08 11:39:48 AM UTC 25 8325645014 ps
T54 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1914906421 Feb 08 11:39:49 AM UTC 25 Feb 08 11:39:58 AM UTC 25 168601899 ps
T45 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1784975548 Feb 08 11:39:45 AM UTC 25 Feb 08 11:40:00 AM UTC 25 2729025132 ps
T150 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2843594502 Feb 08 11:38:32 AM UTC 25 Feb 08 11:40:00 AM UTC 25 1113203405 ps
T161 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2184909035 Feb 08 11:40:02 AM UTC 25 Feb 08 11:40:04 AM UTC 25 84645081 ps
T35 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.232927301 Feb 08 11:40:01 AM UTC 25 Feb 08 11:40:05 AM UTC 25 240929584 ps
T143 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4178464145 Feb 08 11:38:58 AM UTC 25 Feb 08 11:40:10 AM UTC 25 128459821 ps
T162 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3464093495 Feb 08 11:38:43 AM UTC 25 Feb 08 11:40:40 AM UTC 25 898406957 ps
T31 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3200188787 Feb 08 11:39:31 AM UTC 25 Feb 08 11:40:43 AM UTC 25 2394558573 ps
T98 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2594101120 Feb 08 11:36:52 AM UTC 25 Feb 08 11:40:45 AM UTC 25 11768287703 ps
T163 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3452665456 Feb 08 11:40:05 AM UTC 25 Feb 08 11:40:59 AM UTC 25 105665822 ps
T164 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1318156832 Feb 08 11:40:46 AM UTC 25 Feb 08 11:41:09 AM UTC 25 80337128 ps
T99 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3983845052 Feb 08 11:36:50 AM UTC 25 Feb 08 11:41:15 AM UTC 25 9508464654 ps
T165 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.423570410 Feb 08 11:41:10 AM UTC 25 Feb 08 11:41:22 AM UTC 25 1219310810 ps
T100 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2633981846 Feb 08 11:36:45 AM UTC 25 Feb 08 11:41:25 AM UTC 25 13751278218 ps
T166 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2657760200 Feb 08 11:40:10 AM UTC 25 Feb 08 11:41:27 AM UTC 25 3706964841 ps
T167 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.641638310 Feb 08 11:41:28 AM UTC 25 Feb 08 11:41:31 AM UTC 25 98552294 ps
T55 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1868373646 Feb 08 11:41:32 AM UTC 25 Feb 08 11:41:42 AM UTC 25 345035071 ps
T56 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2097001509 Feb 08 11:41:36 AM UTC 25 Feb 08 11:41:42 AM UTC 25 193781344 ps
T29 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2758472443 Feb 08 11:36:46 AM UTC 25 Feb 08 11:41:56 AM UTC 25 4315914125 ps
T140 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3581354173 Feb 08 11:40:40 AM UTC 25 Feb 08 11:41:59 AM UTC 25 686104414 ps
T168 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3669895384 Feb 08 11:41:57 AM UTC 25 Feb 08 11:42:00 AM UTC 25 14686228 ps
T30 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.2794794524 Feb 08 11:41:23 AM UTC 25 Feb 08 11:42:02 AM UTC 25 1692358437 ps
T169 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1187978459 Feb 08 11:41:00 AM UTC 25 Feb 08 11:42:18 AM UTC 25 303025313 ps
T170 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3898319345 Feb 08 11:41:59 AM UTC 25 Feb 08 11:42:22 AM UTC 25 334409455 ps
T101 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2296668531 Feb 08 11:37:06 AM UTC 25 Feb 08 11:42:26 AM UTC 25 5310675367 ps
T171 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.342373124 Feb 08 11:42:19 AM UTC 25 Feb 08 11:42:27 AM UTC 25 298664185 ps
T102 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3815227630 Feb 08 11:38:43 AM UTC 25 Feb 08 11:42:31 AM UTC 25 18024868397 ps
T24 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2874941910 Feb 08 11:42:32 AM UTC 25 Feb 08 11:42:46 AM UTC 25 765135334 ps
T172 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.4062205602 Feb 08 11:42:03 AM UTC 25 Feb 08 11:42:51 AM UTC 25 1970871521 ps
T173 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.118817499 Feb 08 11:42:51 AM UTC 25 Feb 08 11:42:54 AM UTC 25 79224719 ps
T103 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.3853308490 Feb 08 11:36:45 AM UTC 25 Feb 08 11:43:01 AM UTC 25 6672987868 ps
T174 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.560082957 Feb 08 11:42:54 AM UTC 25 Feb 08 11:43:05 AM UTC 25 4465949378 ps
T84 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.57600358 Feb 08 11:43:01 AM UTC 25 Feb 08 11:43:07 AM UTC 25 47097662 ps
T175 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3930662875 Feb 08 11:43:18 AM UTC 25 Feb 08 11:43:20 AM UTC 25 14514337 ps
T176 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3052706157 Feb 08 11:42:27 AM UTC 25 Feb 08 11:43:21 AM UTC 25 119093767 ps
T104 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2137174710 Feb 08 11:38:33 AM UTC 25 Feb 08 11:43:24 AM UTC 25 8532997884 ps
T20 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.2134342351 Feb 08 11:38:04 AM UTC 25 Feb 08 11:43:35 AM UTC 25 11211265362 ps
T177 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4060722567 Feb 08 11:42:28 AM UTC 25 Feb 08 11:43:36 AM UTC 25 132330661 ps
T178 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.4189025624 Feb 08 11:43:21 AM UTC 25 Feb 08 11:43:44 AM UTC 25 661765905 ps
T43 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4180803751 Feb 08 11:39:06 AM UTC 25 Feb 08 11:43:46 AM UTC 25 4830450707 ps
T179 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2095663440 Feb 08 11:43:25 AM UTC 25 Feb 08 11:43:56 AM UTC 25 441758788 ps
T148 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1877095070 Feb 08 11:43:51 AM UTC 25 Feb 08 11:44:03 AM UTC 25 471480058 ps
T180 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.362157241 Feb 08 11:43:47 AM UTC 25 Feb 08 11:44:12 AM UTC 25 450284579 ps
T181 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2380617489 Feb 08 11:44:13 AM UTC 25 Feb 08 11:44:16 AM UTC 25 32555039 ps
T67 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2642495905 Feb 08 11:43:06 AM UTC 25 Feb 08 11:44:17 AM UTC 25 1554142239 ps
T57 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3819838791 Feb 08 11:44:18 AM UTC 25 Feb 08 11:44:24 AM UTC 25 110048851 ps
T182 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1675445614 Feb 08 11:44:17 AM UTC 25 Feb 08 11:44:28 AM UTC 25 894153721 ps
T183 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1658582281 Feb 08 11:43:37 AM UTC 25 Feb 08 11:44:29 AM UTC 25 186863930 ps
T184 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.510289507 Feb 08 11:44:29 AM UTC 25 Feb 08 11:44:32 AM UTC 25 12992529 ps
T51 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4014100661 Feb 08 11:44:22 AM UTC 25 Feb 08 11:44:33 AM UTC 25 274589635 ps
T68 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2037271201 Feb 08 11:39:58 AM UTC 25 Feb 08 11:44:35 AM UTC 25 2920786300 ps
T185 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.43230243 Feb 08 11:40:28 AM UTC 25 Feb 08 11:44:50 AM UTC 25 4349187281 ps
T186 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3165500875 Feb 08 11:44:30 AM UTC 25 Feb 08 11:44:55 AM UTC 25 3736087269 ps
T187 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2032277054 Feb 08 11:44:51 AM UTC 25 Feb 08 11:45:05 AM UTC 25 182942377 ps
T188 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.911889546 Feb 08 11:44:34 AM UTC 25 Feb 08 11:45:10 AM UTC 25 1660258090 ps
T63 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.1202055391 Feb 08 11:36:46 AM UTC 25 Feb 08 11:45:11 AM UTC 25 19739164826 ps
T189 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3928416920 Feb 08 11:43:46 AM UTC 25 Feb 08 11:45:12 AM UTC 25 135989622 ps
T190 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3717897572 Feb 08 11:37:38 AM UTC 25 Feb 08 11:45:17 AM UTC 25 3395203921 ps
T191 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3068416226 Feb 08 11:45:12 AM UTC 25 Feb 08 11:45:22 AM UTC 25 2307187655 ps
T192 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2533466344 Feb 08 11:45:23 AM UTC 25 Feb 08 11:45:26 AM UTC 25 28957667 ps
T138 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3984857710 Feb 08 11:40:44 AM UTC 25 Feb 08 11:45:32 AM UTC 25 70563524485 ps
T193 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3078844271 Feb 08 11:45:26 AM UTC 25 Feb 08 11:45:35 AM UTC 25 357681437 ps
T58 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1023650836 Feb 08 11:45:32 AM UTC 25 Feb 08 11:45:41 AM UTC 25 376907346 ps
T125 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.2730091274 Feb 08 11:37:21 AM UTC 25 Feb 08 11:45:44 AM UTC 25 9829468508 ps
T194 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.54606371 Feb 08 11:45:42 AM UTC 25 Feb 08 11:45:44 AM UTC 25 19900407 ps
T195 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1089411772 Feb 08 11:45:45 AM UTC 25 Feb 08 11:45:49 AM UTC 25 67279769 ps
T49 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3332744241 Feb 08 11:45:36 AM UTC 25 Feb 08 11:45:53 AM UTC 25 368728412 ps
T196 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2298266574 Feb 08 11:45:11 AM UTC 25 Feb 08 11:46:19 AM UTC 25 155231329 ps
T197 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2134333510 Feb 08 11:46:20 AM UTC 25 Feb 08 11:46:40 AM UTC 25 294239122 ps
T198 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3546240823 Feb 08 11:45:06 AM UTC 25 Feb 08 11:46:45 AM UTC 25 420131969 ps
T141 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.149187131 Feb 08 11:42:23 AM UTC 25 Feb 08 11:46:46 AM UTC 25 9440065635 ps
T25 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2168345980 Feb 08 11:46:46 AM UTC 25 Feb 08 11:46:57 AM UTC 25 1840859123 ps
T199 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.318252361 Feb 08 11:37:05 AM UTC 25 Feb 08 11:47:07 AM UTC 25 7094224981 ps
T200 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1867388124 Feb 08 11:43:35 AM UTC 25 Feb 08 11:47:12 AM UTC 25 8268444743 ps
T201 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1914322935 Feb 08 11:47:13 AM UTC 25 Feb 08 11:47:15 AM UTC 25 85347722 ps
T202 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1018533294 Feb 08 11:46:46 AM UTC 25 Feb 08 11:47:18 AM UTC 25 466911525 ps
T203 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.144411144 Feb 08 11:45:50 AM UTC 25 Feb 08 11:47:21 AM UTC 25 5260138307 ps
T204 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1214852513 Feb 08 11:47:16 AM UTC 25 Feb 08 11:47:24 AM UTC 25 754320035 ps
T205 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1413117401 Feb 08 11:47:24 AM UTC 25 Feb 08 11:47:26 AM UTC 25 67312183 ps
T206 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2500158636 Feb 08 11:47:18 AM UTC 25 Feb 08 11:47:27 AM UTC 25 633237744 ps
T207 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2898873716 Feb 08 11:40:06 AM UTC 25 Feb 08 11:47:32 AM UTC 25 9495577062 ps
T21 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.693210968 Feb 08 11:36:56 AM UTC 25 Feb 08 11:47:43 AM UTC 25 17915066209 ps
T208 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.251089951 Feb 08 11:47:27 AM UTC 25 Feb 08 11:47:50 AM UTC 25 1942964243 ps
T209 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1913842309 Feb 08 11:46:45 AM UTC 25 Feb 08 11:47:58 AM UTC 25 750605623 ps
T145 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.588536852 Feb 08 11:37:46 AM UTC 25 Feb 08 11:47:59 AM UTC 25 55024337086 ps
T22 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4294248486 Feb 08 11:47:19 AM UTC 25 Feb 08 11:48:01 AM UTC 25 1016872965 ps
T126 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.782096999 Feb 08 11:39:19 AM UTC 25 Feb 08 11:48:05 AM UTC 25 78435669780 ps
T210 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4254705199 Feb 08 11:44:56 AM UTC 25 Feb 08 11:48:07 AM UTC 25 9095078123 ps
T211 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.516536074 Feb 08 11:47:32 AM UTC 25 Feb 08 11:48:09 AM UTC 25 439288354 ps
T212 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.444760350 Feb 08 11:48:06 AM UTC 25 Feb 08 11:48:09 AM UTC 25 152798185 ps
T213 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3434868844 Feb 08 11:48:17 AM UTC 25 Feb 08 11:48:20 AM UTC 25 96875591 ps
T214 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1154394922 Feb 08 11:37:35 AM UTC 25 Feb 08 11:48:24 AM UTC 25 2573420946 ps
T215 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.3246000372 Feb 08 11:48:10 AM UTC 25 Feb 08 11:48:26 AM UTC 25 234637714 ps
T59 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.89638165 Feb 08 11:48:24 AM UTC 25 Feb 08 11:48:30 AM UTC 25 374158816 ps
T216 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3737208081 Feb 08 11:48:31 AM UTC 25 Feb 08 11:48:33 AM UTC 25 16884177 ps
T217 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2595379636 Feb 08 11:43:44 AM UTC 25 Feb 08 11:48:33 AM UTC 25 16157538770 ps
T218 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1763122565 Feb 08 11:48:20 AM UTC 25 Feb 08 11:48:34 AM UTC 25 2836587875 ps
T69 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1950570749 Feb 08 11:48:26 AM UTC 25 Feb 08 11:48:39 AM UTC 25 538083518 ps
T219 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.74016608 Feb 08 11:48:34 AM UTC 25 Feb 08 11:48:46 AM UTC 25 1371025667 ps
T220 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.441495830 Feb 08 11:48:02 AM UTC 25 Feb 08 11:48:47 AM UTC 25 441313757 ps
T221 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.3952203683 Feb 08 11:48:47 AM UTC 25 Feb 08 11:48:55 AM UTC 25 286442456 ps
T222 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1493656548 Feb 08 11:47:51 AM UTC 25 Feb 08 11:48:55 AM UTC 25 1100790198 ps
T134 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.1735954414 Feb 08 11:42:47 AM UTC 25 Feb 08 11:48:57 AM UTC 25 12090962744 ps
T223 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.252198147 Feb 08 11:48:56 AM UTC 25 Feb 08 11:49:03 AM UTC 25 355363790 ps
T224 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1153967385 Feb 08 11:42:09 AM UTC 25 Feb 08 11:49:09 AM UTC 25 6608044131 ps
T225 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.365480903 Feb 08 11:49:15 AM UTC 25 Feb 08 11:49:17 AM UTC 25 40927930 ps
T226 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3486837416 Feb 08 11:45:54 AM UTC 25 Feb 08 11:49:18 AM UTC 25 1560603174 ps
T227 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.1524171904 Feb 08 11:48:35 AM UTC 25 Feb 08 11:49:24 AM UTC 25 746524918 ps
T228 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.928070486 Feb 08 11:49:19 AM UTC 25 Feb 08 11:49:27 AM UTC 25 91658934 ps
T229 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1455066573 Feb 08 11:48:00 AM UTC 25 Feb 08 11:49:28 AM UTC 25 958057131 ps
T230 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.302175060 Feb 08 11:48:55 AM UTC 25 Feb 08 11:49:30 AM UTC 25 176449875 ps
T231 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2291655382 Feb 08 11:49:29 AM UTC 25 Feb 08 11:49:32 AM UTC 25 164629581 ps
T132 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2114921340 Feb 08 11:38:02 AM UTC 25 Feb 08 11:49:32 AM UTC 25 9361767111 ps
T232 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1161596287 Feb 08 11:49:18 AM UTC 25 Feb 08 11:49:35 AM UTC 25 2741126687 ps
T233 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2275265713 Feb 08 11:48:56 AM UTC 25 Feb 08 11:49:36 AM UTC 25 102154923 ps
T44 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2641411590 Feb 08 11:43:57 AM UTC 25 Feb 08 11:49:44 AM UTC 25 52540035893 ps
T234 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2333767072 Feb 08 11:49:46 AM UTC 25 Feb 08 11:49:49 AM UTC 25 52463992 ps
T235 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1912887076 Feb 08 11:36:46 AM UTC 25 Feb 08 11:49:50 AM UTC 25 11803842899 ps
T236 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2275225684 Feb 08 11:49:31 AM UTC 25 Feb 08 11:49:50 AM UTC 25 2980510757 ps
T237 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1958355058 Feb 08 11:49:51 AM UTC 25 Feb 08 11:50:03 AM UTC 25 774518440 ps
T238 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2465693884 Feb 08 11:49:50 AM UTC 25 Feb 08 11:50:04 AM UTC 25 301826578 ps
T239 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2170413628 Feb 08 11:44:35 AM UTC 25 Feb 08 11:50:07 AM UTC 25 2924261710 ps
T240 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1574084020 Feb 08 11:50:08 AM UTC 25 Feb 08 11:50:11 AM UTC 25 30597186 ps
T241 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2264523595 Feb 08 11:48:10 AM UTC 25 Feb 08 11:50:15 AM UTC 25 4312302451 ps
T242 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1471381039 Feb 08 11:50:14 AM UTC 25 Feb 08 11:50:23 AM UTC 25 1976506125 ps
T243 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.4267488847 Feb 08 11:50:11 AM UTC 25 Feb 08 11:50:23 AM UTC 25 1681676723 ps
T244 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3673816257 Feb 08 11:50:23 AM UTC 25 Feb 08 11:50:26 AM UTC 25 20331610 ps
T133 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3601361990 Feb 08 11:42:49 AM UTC 25 Feb 08 11:50:26 AM UTC 25 9227552695 ps
T245 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3492852652 Feb 08 11:50:24 AM UTC 25 Feb 08 11:50:34 AM UTC 25 3939329437 ps
T246 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.598856218 Feb 08 11:49:36 AM UTC 25 Feb 08 11:50:48 AM UTC 25 1242526927 ps
T247 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1231106508 Feb 08 11:49:33 AM UTC 25 Feb 08 11:50:51 AM UTC 25 1076579319 ps
T248 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.65073485 Feb 08 11:46:41 AM UTC 25 Feb 08 11:50:53 AM UTC 25 3345178926 ps
T249 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4257064088 Feb 08 11:49:25 AM UTC 25 Feb 08 11:50:56 AM UTC 25 275090938 ps
T250 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1397749030 Feb 08 11:50:57 AM UTC 25 Feb 08 11:51:00 AM UTC 25 135418509 ps
T251 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1536769731 Feb 08 11:49:28 AM UTC 25 Feb 08 11:51:11 AM UTC 25 8246789725 ps
T252 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2768043949 Feb 08 11:51:01 AM UTC 25 Feb 08 11:51:13 AM UTC 25 572060742 ps
T128 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3840063225 Feb 08 11:40:01 AM UTC 25 Feb 08 11:51:22 AM UTC 25 12169284496 ps
T127 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1300555938 Feb 08 11:45:17 AM UTC 25 Feb 08 11:51:33 AM UTC 25 3326032160 ps
T253 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3919632944 Feb 08 11:51:34 AM UTC 25 Feb 08 11:51:36 AM UTC 25 46144664 ps
T254 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.3404411379 Feb 08 11:50:27 AM UTC 25 Feb 08 11:51:41 AM UTC 25 9851571538 ps
T255 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3509918789 Feb 08 11:51:37 AM UTC 25 Feb 08 11:51:45 AM UTC 25 680979054 ps
T256 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3350631997 Feb 08 11:51:42 AM UTC 25 Feb 08 11:51:47 AM UTC 25 50318615 ps
T257 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.261813179 Feb 08 11:48:39 AM UTC 25 Feb 08 11:52:13 AM UTC 25 8961263875 ps
T258 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3203354304 Feb 08 11:50:54 AM UTC 25 Feb 08 11:52:15 AM UTC 25 149930829 ps
T259 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1360848687 Feb 08 11:52:14 AM UTC 25 Feb 08 11:52:16 AM UTC 25 13854459 ps
T260 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1811371936 Feb 08 11:41:26 AM UTC 25 Feb 08 11:52:26 AM UTC 25 13044529275 ps
T261 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.276317910 Feb 08 11:52:15 AM UTC 25 Feb 08 11:52:36 AM UTC 25 2132462857 ps
T262 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.4206415324 Feb 08 11:38:31 AM UTC 25 Feb 08 11:52:39 AM UTC 25 64322662105 ps
T263 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1140544843 Feb 08 11:52:28 AM UTC 25 Feb 08 11:52:50 AM UTC 25 1109720726 ps
T264 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.243956495 Feb 08 11:52:51 AM UTC 25 Feb 08 11:53:03 AM UTC 25 71369673 ps
T265 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3173971660 Feb 08 11:52:40 AM UTC 25 Feb 08 11:53:06 AM UTC 25 93335140 ps
T266 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2206542253 Feb 08 11:52:52 AM UTC 25 Feb 08 11:53:08 AM UTC 25 705490210 ps
T267 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2566907740 Feb 08 11:47:59 AM UTC 25 Feb 08 11:53:12 AM UTC 25 18062361739 ps
T268 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3701045816 Feb 08 11:53:12 AM UTC 25 Feb 08 11:53:15 AM UTC 25 45530217 ps
T269 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.712032276 Feb 08 11:53:24 AM UTC 25 Feb 08 11:53:33 AM UTC 25 171093989 ps
T270 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.691066217 Feb 08 11:53:15 AM UTC 25 Feb 08 11:53:33 AM UTC 25 2372480562 ps
T271 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1328710134 Feb 08 11:52:17 AM UTC 25 Feb 08 11:53:36 AM UTC 25 463642367 ps
T272 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1972256459 Feb 08 11:53:37 AM UTC 25 Feb 08 11:53:39 AM UTC 25 15447702 ps
T273 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1932813702 Feb 08 11:44:12 AM UTC 25 Feb 08 11:53:41 AM UTC 25 10608695240 ps
T274 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.893097731 Feb 08 11:47:44 AM UTC 25 Feb 08 11:53:42 AM UTC 25 14144977135 ps
T275 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2960450625 Feb 08 11:53:40 AM UTC 25 Feb 08 11:53:44 AM UTC 25 175886601 ps
T276 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.857219890 Feb 08 11:52:17 AM UTC 25 Feb 08 11:53:45 AM UTC 25 10045496620 ps
T277 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.4277436821 Feb 08 11:48:58 AM UTC 25 Feb 08 11:53:45 AM UTC 25 4485315040 ps
T278 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1589391393 Feb 08 11:53:46 AM UTC 25 Feb 08 11:53:53 AM UTC 25 112972608 ps
T279 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.502115743 Feb 08 11:48:47 AM UTC 25 Feb 08 11:53:56 AM UTC 25 49993081682 ps
T280 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3548678709 Feb 08 11:53:59 AM UTC 25 Feb 08 11:54:10 AM UTC 25 5593124425 ps
T281 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2298857970 Feb 08 11:53:54 AM UTC 25 Feb 08 11:54:18 AM UTC 25 91030568 ps
T282 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1328391732 Feb 08 11:54:11 AM UTC 25 Feb 08 11:54:27 AM UTC 25 220834074 ps
T283 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3866531797 Feb 08 11:54:28 AM UTC 25 Feb 08 11:54:31 AM UTC 25 29783239 ps
T284 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2192602901 Feb 08 11:53:43 AM UTC 25 Feb 08 11:54:32 AM UTC 25 15656112497 ps
T285 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.4218145428 Feb 08 11:54:29 AM UTC 25 Feb 08 11:54:38 AM UTC 25 608185540 ps
T286 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3033177549 Feb 08 11:54:32 AM UTC 25 Feb 08 11:54:41 AM UTC 25 150347906 ps
T287 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.4069766311 Feb 08 11:54:42 AM UTC 25 Feb 08 11:54:44 AM UTC 25 35580200 ps
T288 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2321095520 Feb 08 11:37:17 AM UTC 25 Feb 08 11:54:45 AM UTC 25 46428948539 ps
T289 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2037597767 Feb 08 11:54:33 AM UTC 25 Feb 08 11:54:48 AM UTC 25 320312960 ps
T290 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2499963957 Feb 08 11:49:36 AM UTC 25 Feb 08 11:55:09 AM UTC 25 43583260138 ps
T291 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3920410835 Feb 08 11:53:56 AM UTC 25 Feb 08 11:55:01 AM UTC 25 447907209 ps
T292 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1540709840 Feb 08 11:55:01 AM UTC 25 Feb 08 11:55:19 AM UTC 25 209633912 ps
T129 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.475879863 Feb 08 11:44:25 AM UTC 25 Feb 08 11:55:20 AM UTC 25 66413966786 ps
T131 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1622408051 Feb 08 11:36:55 AM UTC 25 Feb 08 11:55:24 AM UTC 25 4536046424 ps
T293 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1780043631 Feb 08 11:54:49 AM UTC 25 Feb 08 11:55:25 AM UTC 25 3062784423 ps
T294 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4005317015 Feb 08 11:55:25 AM UTC 25 Feb 08 11:55:39 AM UTC 25 743133542 ps
T295 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1862199212 Feb 08 11:36:49 AM UTC 25 Feb 08 11:55:41 AM UTC 25 45110046109 ps
T296 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.793694195 Feb 08 11:54:45 AM UTC 25 Feb 08 11:55:49 AM UTC 25 1068637314 ps
T297 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.725050128 Feb 08 11:55:50 AM UTC 25 Feb 08 11:55:53 AM UTC 25 27537582 ps
T130 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3727654913 Feb 08 11:54:14 AM UTC 25 Feb 08 11:55:54 AM UTC 25 1880070576 ps
T298 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.445031525 Feb 08 11:55:55 AM UTC 25 Feb 08 11:56:02 AM UTC 25 98750508 ps
T299 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.2345991191 Feb 08 11:55:53 AM UTC 25 Feb 08 11:56:03 AM UTC 25 2055791936 ps
T300 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2204968573 Feb 08 11:55:21 AM UTC 25 Feb 08 11:56:06 AM UTC 25 379367183 ps
T301 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3020020953 Feb 08 11:56:07 AM UTC 25 Feb 08 11:56:09 AM UTC 25 67867008 ps
T106 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3193544469 Feb 08 11:56:02 AM UTC 25 Feb 08 11:56:11 AM UTC 25 296171561 ps
T302 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2473886611 Feb 08 11:56:10 AM UTC 25 Feb 08 11:56:15 AM UTC 25 299361888 ps
T135 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1575066244 Feb 08 11:37:00 AM UTC 25 Feb 08 11:56:17 AM UTC 25 29060984566 ps
T303 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.695358340 Feb 08 11:49:51 AM UTC 25 Feb 08 11:56:19 AM UTC 25 4714268131 ps
T304 /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.847271039 Feb 08 11:50:35 AM UTC 25 Feb 08 11:56:24 AM UTC 25 40587233399 ps