SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_key_intr_status_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ac_present_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst_l_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst_l_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_flash_wp_l_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_flash_wp_l_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1103 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 117 | 1 | T36 | 1 | T17 | 3 | T51 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1073 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 147 | 1 | T12 | 9 | T17 | 4 | T50 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1110 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 110 | 1 | T12 | 3 | T16 | 2 | T17 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1122 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 98 | 1 | T12 | 3 | T17 | 4 | T51 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1096 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 124 | 1 | T36 | 1 | T12 | 3 | T16 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1123 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 97 | 1 | T12 | 1 | T16 | 1 | T17 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1121 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 99 | 1 | T12 | 5 | T16 | 1 | T17 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1096 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 124 | 1 | T12 | 7 | T16 | 2 | T17 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1107 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 113 | 1 | T36 | 1 | T12 | 3 | T50 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1088 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 132 | 1 | T16 | 1 | T50 | 3 | T45 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1155 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 65 | 1 | T17 | 3 | T45 | 1 | T47 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1095 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 125 | 1 | T12 | 4 | T16 | 2 | T17 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1116 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 104 | 1 | T36 | 1 | T12 | 4 | T16 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1127 | 1 | T38 | 1 | T335 | 1 | T288 | 1 | ||||
auto[1] | 93 | 1 | T50 | 3 | T46 | 2 | T45 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |