Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T144 |
2 |
|
T100 |
1 |
auto[1] |
2 |
1 |
|
|
T100 |
2 |
|
- |
- |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2 |
1 |
|
|
T144 |
1 |
|
T100 |
1 |
auto[1] |
3 |
1 |
|
|
T144 |
1 |
|
T100 |
2 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T144 |
1 |
|
T100 |
2 |
auto[1] |
2 |
1 |
|
|
T144 |
1 |
|
T100 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4 |
1 |
|
|
T144 |
2 |
|
T100 |
2 |
auto[1] |
1 |
1 |
|
|
T100 |
1 |
|
- |
- |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4 |
1 |
|
|
T144 |
1 |
|
T100 |
3 |
auto[1] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T144 |
2 |
|
T100 |
1 |
auto[1] |
2 |
1 |
|
|
T100 |
2 |
|
- |
- |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
auto[0] |
auto[1] |
1 |
1 |
|
|
T100 |
1 |
|
- |
- |
auto[1] |
auto[0] |
2 |
1 |
|
|
T144 |
1 |
|
T100 |
1 |
auto[1] |
auto[1] |
1 |
1 |
|
|
T100 |
1 |
|
- |
- |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cross_key1_out_sel_value
Uncovered bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
3 |
1 |
|
|
T144 |
1 |
|
T100 |
2 |
auto[0] |
auto[1] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
auto[1] |
auto[1] |
1 |
1 |
|
|
T100 |
1 |
|
- |
- |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cross_key2_out_sel_value
Uncovered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2 |
1 |
|
|
T144 |
1 |
|
T100 |
1 |
auto[0] |
auto[1] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
auto[1] |
auto[0] |
2 |
1 |
|
|
T100 |
2 |
|
- |
- |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
121 |
1 |
|
|
T12 |
2 |
|
T25 |
2 |
|
T83 |
2 |
auto[1] |
124 |
1 |
|
|
T69 |
3 |
|
T12 |
1 |
|
T25 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
123 |
1 |
|
|
T69 |
1 |
|
T25 |
2 |
|
T26 |
1 |
auto[1] |
122 |
1 |
|
|
T69 |
2 |
|
T12 |
3 |
|
T25 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
121 |
1 |
|
|
T69 |
2 |
|
T12 |
1 |
|
T25 |
2 |
auto[1] |
124 |
1 |
|
|
T69 |
1 |
|
T12 |
2 |
|
T25 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
119 |
1 |
|
|
T69 |
3 |
|
T12 |
3 |
|
T25 |
2 |
auto[1] |
126 |
1 |
|
|
T25 |
1 |
|
T83 |
1 |
|
T84 |
2 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
125 |
1 |
|
|
T69 |
2 |
|
T12 |
2 |
|
T25 |
1 |
auto[1] |
120 |
1 |
|
|
T69 |
1 |
|
T12 |
1 |
|
T25 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
115 |
1 |
|
|
T12 |
1 |
|
T25 |
3 |
|
T26 |
1 |
auto[1] |
130 |
1 |
|
|
T69 |
3 |
|
T12 |
2 |
|
T26 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
60 |
1 |
|
|
T25 |
1 |
|
T297 |
1 |
|
T85 |
1 |
auto[0] |
auto[1] |
63 |
1 |
|
|
T69 |
1 |
|
T25 |
1 |
|
T26 |
1 |
auto[1] |
auto[0] |
61 |
1 |
|
|
T12 |
2 |
|
T25 |
1 |
|
T83 |
2 |
auto[1] |
auto[1] |
61 |
1 |
|
|
T69 |
2 |
|
T12 |
1 |
|
T26 |
2 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
63 |
1 |
|
|
T69 |
2 |
|
T12 |
1 |
|
T25 |
2 |
auto[0] |
auto[1] |
56 |
1 |
|
|
T69 |
1 |
|
T12 |
2 |
|
T26 |
2 |
auto[1] |
auto[0] |
58 |
1 |
|
|
T83 |
1 |
|
T85 |
1 |
|
T86 |
1 |
auto[1] |
auto[1] |
68 |
1 |
|
|
T25 |
1 |
|
T84 |
2 |
|
T297 |
2 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55 |
1 |
|
|
T25 |
1 |
|
T83 |
1 |
|
T87 |
3 |
auto[0] |
auto[1] |
60 |
1 |
|
|
T12 |
1 |
|
T25 |
2 |
|
T26 |
1 |
auto[1] |
auto[0] |
70 |
1 |
|
|
T69 |
2 |
|
T12 |
2 |
|
T83 |
1 |
auto[1] |
auto[1] |
60 |
1 |
|
|
T69 |
1 |
|
T26 |
2 |
|
T83 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
17 |
1 |
|
|
T48 |
2 |
|
T78 |
2 |
|
T205 |
1 |
auto[1] |
19 |
1 |
|
|
T48 |
1 |
|
T205 |
2 |
|
T159 |
2 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
17 |
1 |
|
|
T48 |
1 |
|
T205 |
2 |
|
T159 |
2 |
auto[1] |
19 |
1 |
|
|
T48 |
2 |
|
T78 |
2 |
|
T205 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T205 |
3 |
auto[1] |
12 |
1 |
|
|
T48 |
2 |
|
T78 |
1 |
|
T343 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T48 |
2 |
|
T78 |
1 |
|
T205 |
2 |
auto[1] |
16 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T205 |
1 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
19 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T205 |
3 |
auto[1] |
17 |
1 |
|
|
T48 |
2 |
|
T78 |
1 |
|
T159 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T205 |
1 |
auto[1] |
16 |
1 |
|
|
T48 |
2 |
|
T78 |
1 |
|
T205 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
10 |
1 |
|
|
T48 |
1 |
|
T205 |
1 |
|
T159 |
1 |
auto[0] |
auto[1] |
7 |
1 |
|
|
T205 |
1 |
|
T159 |
1 |
|
T343 |
1 |
auto[1] |
auto[0] |
7 |
1 |
|
|
T48 |
1 |
|
T78 |
2 |
|
T343 |
1 |
auto[1] |
auto[1] |
12 |
1 |
|
|
T48 |
1 |
|
T205 |
1 |
|
T159 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
14 |
1 |
|
|
T48 |
1 |
|
T205 |
2 |
|
T159 |
2 |
auto[0] |
auto[1] |
6 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T343 |
1 |
auto[1] |
auto[0] |
10 |
1 |
|
|
T78 |
1 |
|
T205 |
1 |
|
T159 |
1 |
auto[1] |
auto[1] |
6 |
1 |
|
|
T48 |
1 |
|
T344 |
2 |
|
T345 |
2 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
9 |
1 |
|
|
T205 |
1 |
|
T159 |
1 |
|
T343 |
1 |
auto[0] |
auto[1] |
11 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T159 |
1 |
auto[1] |
auto[0] |
10 |
1 |
|
|
T48 |
1 |
|
T78 |
1 |
|
T205 |
2 |
auto[1] |
auto[1] |
6 |
1 |
|
|
T48 |
1 |
|
T159 |
1 |
|
T346 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15 |
1 |
|
|
T78 |
1 |
|
T144 |
1 |
|
T343 |
1 |
auto[1] |
14 |
1 |
|
|
T78 |
2 |
|
T144 |
2 |
|
T343 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15 |
1 |
|
|
T78 |
1 |
|
T144 |
1 |
|
T343 |
1 |
auto[1] |
14 |
1 |
|
|
T78 |
2 |
|
T144 |
2 |
|
T343 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T78 |
2 |
|
T144 |
2 |
|
T343 |
1 |
auto[1] |
9 |
1 |
|
|
T78 |
1 |
|
T144 |
1 |
|
T343 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T78 |
1 |
|
T144 |
2 |
|
T346 |
1 |
auto[1] |
21 |
1 |
|
|
T78 |
2 |
|
T144 |
1 |
|
T343 |
2 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13 |
1 |
|
|
T78 |
1 |
|
T144 |
2 |
|
T346 |
1 |
auto[1] |
16 |
1 |
|
|
T78 |
2 |
|
T144 |
1 |
|
T343 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15 |
1 |
|
|
T78 |
2 |
|
T144 |
3 |
|
T343 |
1 |
auto[1] |
14 |
1 |
|
|
T78 |
1 |
|
T343 |
1 |
|
T346 |
3 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
8 |
1 |
|
|
T78 |
1 |
|
T144 |
1 |
|
T346 |
1 |
auto[0] |
auto[1] |
7 |
1 |
|
|
T343 |
1 |
|
T201 |
1 |
|
T192 |
2 |
auto[1] |
auto[0] |
7 |
1 |
|
|
T343 |
1 |
|
T346 |
1 |
|
T162 |
2 |
auto[1] |
auto[1] |
7 |
1 |
|
|
T78 |
2 |
|
T144 |
2 |
|
T346 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
4 |
1 |
|
|
T144 |
1 |
|
T346 |
1 |
|
T347 |
1 |
auto[0] |
auto[1] |
4 |
1 |
|
|
T78 |
1 |
|
T144 |
1 |
|
T162 |
1 |
auto[1] |
auto[0] |
16 |
1 |
|
|
T78 |
2 |
|
T144 |
1 |
|
T343 |
1 |
auto[1] |
auto[1] |
5 |
1 |
|
|
T343 |
1 |
|
T162 |
2 |
|
T201 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
6 |
1 |
|
|
T78 |
1 |
|
T144 |
2 |
|
T201 |
2 |
auto[0] |
auto[1] |
9 |
1 |
|
|
T78 |
1 |
|
T144 |
1 |
|
T343 |
1 |
auto[1] |
auto[0] |
7 |
1 |
|
|
T346 |
1 |
|
T162 |
2 |
|
T347 |
1 |
auto[1] |
auto[1] |
7 |
1 |
|
|
T78 |
1 |
|
T343 |
1 |
|
T346 |
2 |