Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1843

1

T15

9

T29

36

T20

41

auto[1]

696

1

T13

7

T15

3

T20

23

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T13

7

T15

12

T29

28

auto[1]

596

1

T29

8

T20

28

T21

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1963

1

T13

5

T15

12

T29

35

auto[1]

576

1

T13

2

T29

1

T20

16

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T13

2

T15

3

T29

30

auto[1]

604

1

T13

5

T15

9

T29

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2373

1

T13

7

T15

12

T29

23

auto[1]

166

1

T29

13

T20

5

T44

15

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2370

1

T13

7

T15

12

T29

35

auto[1]

169

1

T29

1

T44

5

T116

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2293

1

T13

7

T15

12

T29

31

auto[1]

246

1

T29

5

T20

24

T44

8

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2309

1

T13

7

T15

12

T29

36

auto[1]

230

1

T20

16

T40

3

T53

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2338

1

T13

7

T15

12

T29

30

auto[1]

201

1

T29

6

T20

5

T44

12

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1987

1

T13

5

T15

9

T29

36

auto[1]

552

1

T13

2

T15

3

T20

12

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	933	1			T13	7		T15	12		T21	7
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	35	1			T29	6		T116	5		T313	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	68	1			T40	1		T116	1		T72	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T44	3		T314	1		T315	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	78	1			T20	11		T40	2		T71	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	21	1			T236	1		T232	1		T316	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	17	1			T317	1		T318	9		T319	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	7	1			T20	5		T307	2		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	59	1			T20	24		T116	6		T71	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	20	1			T44	2		T72	3		T318	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	15	1			T320	1		T181	4		T321	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	7	1			T29	3		T308	4		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	23	1			T72	4		T316	3		T298	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T53	3		T322	2		T323	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	19	1			T65	5		T324	2		T325	5
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	1	1			T248	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	44	1			T116	5		T115	4		T322	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	23	1			T317	1		T73	2		T326	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	14	1			T29	1		T44	2		T234	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T304	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	26	1			T319	3		T327	3		T328	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T329	1		T304	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	48	1			T65	24		T248	9		T313	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T304	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T317	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T330	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

97

1

T52

12

T116

1

T71

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

108

1

T20

12

T116

6

T234

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

51

1

T15

3

T52

5

T129

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

153

1

T15

9

T29

3

T44

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

86

1

T13

5

T48

2

T167

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T44

2

T43

7

T193

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T66

2

T300

1

T298

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

95

1

T71

2

T234

2

T112

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

98

1

T42

8

T320

2

T319

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T54

2

T41

9

T239

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T13

2

T43

5

T237

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T29

1

T44

2

T54

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T167

3

T78

2

T72

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T42

3

T317

1

T305

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T112

3

T299

3

T126

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

97

1

T29

6

T40

1

T45

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

98

1

T20

12

T40

2

T247

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T53

3

T45

1

T108

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T129

3

T247

1

T331

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T21

4

T238

1

T70

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T108

5

T331

4

T320

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T78

4

T72

3

T216

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T108

2

T332

2

T333

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T20

5

T112

6

T203

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T20

11

T21

3

T331

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T236

1

T240

8

T302

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T43

3

T239

2

T334

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T129

1

T193

2

T239

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T42

1

T149

1

T329

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T247

1

T41

2

T167

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T66

1

T243

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded