Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T13

9

T19

27

T120

9

auto[1]

1052

1

T13

11

T19

13

T120

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

503

1

T13

5

T19

6

T120

6

from_0to1

501

1

T13

6

T19

6

T120

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T13

13

T19

21

T120

8

auto[1]

1095

1

T13

7

T19

19

T120

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T13

4

T19

17

T120

8

auto[1]

1129

1

T13

16

T19

23

T120

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T13

2

T19

1

T120

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T19

1

T50

2

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T19

1

T50

2

T351

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T13

1

T19

2

T120

2

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T19

1

T50

1

T352

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T13

3

T50

1

T351

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T120

3

T50

3

T351

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T50

1

T135

2

T351

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T19

1

T50

2

T351

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T13

2

T120

1

T50

2

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T50

1

T135

1

T351

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T120

1

T50

3

T351

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T19

2

T120

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T13

1

T120

1

T351

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T50

2

T45

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T13

2

T19

3

T120

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T13

6

T19

23

T120

6

auto[1]

1107

1

T13

14

T19

17

T120

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T13

7

T19

10

T120

4

from_0to1

536

1

T13

7

T19

10

T120

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T13

6

T19

21

T120

12

auto[1]

1087

1

T13

14

T19

19

T120

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T13

8

T19

16

T120

10

auto[1]

1071

1

T13

12

T19

24

T120

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T19

1

T50

1

T352

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T19

2

T50

3

T104

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T19

1

T351

1

T352

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T13

2

T19

1

T120

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T120

1

T50

1

T351

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T19

3

T50

2

T351

1

auto[0]

from_0to1

auto[1]

auto[0]

81

1

T19

3

T120

1

T50

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T19

2

T50

1

T352

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T13

1

T19

2

T120

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T19

1

T120

1

T50

2

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T13

2

T19

2

T120

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T13

2

T351

1

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T13

2

T19

1

T120

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T50

2

T135

2

T351

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T13

1

T50

1

T135

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T13

4

T19

1

T120

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T13

8

T19

20

T120

7

auto[1]

1115

1

T13

12

T19

20

T120

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T13

6

T19

11

T120

6

from_0to1

520

1

T13

6

T19

11

T120

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T13

11

T19

21

T120

10

auto[1]

1065

1

T13

9

T19

19

T120

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T13

14

T19

21

T120

11

auto[1]

1065

1

T13

6

T19

19

T120

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T13

1

T19

1

T120

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T13

1

T19

2

T50

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T13

1

T50

2

T351

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T19

4

T120

2

T50

3

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T13

1

T19

2

T50

4

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T19

1

T50

2

T352

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T13

3

T19

1

T50

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T50

3

T353

1

T354

2

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T13

2

T19

1

T50

3

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T13

1

T19

1

T50

2

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T19

1

T120

2

T50

3

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T19

1

T50

1

T135

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T13

1

T19

1

T120

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T19

3

T120

2

T352

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T19

1

T120

1

T50

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T13

1

T19

2

T50

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T13

14

T19

23

T120

6

auto[1]

1070

1

T13

6

T19

17

T120

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T13

7

T19

8

T120

7

from_0to1

529

1

T13

6

T19

8

T120

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T13

11

T19

18

T120

7

auto[1]

1045

1

T13

9

T19

22

T120

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T13

9

T19

22

T120

7

auto[1]

1061

1

T13

11

T19

18

T120

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T13

1

T50

1

T135

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T13

1

T50

2

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T19

2

T120

1

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T13

1

T19

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T120

1

T50

3

T351

2

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T13

2

T50

3

T135

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T19

3

T120

1

T50

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T13

2

T19

1

T120

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T13

1

T19

1

T120

2

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T19

2

T120

1

T50

3

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T13

2

T120

1

T50

3

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T13

1

T19

1

T120

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T19

1

T351

1

T352

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T13

1

T19

2

T120

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T351

1

T352

1

T353

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T13

1

T19

1

T120

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T13

6

T19

18

T120

11

auto[1]

1082

1

T13

14

T19

22

T120

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

534

1

T13

5

T19

9

T120

6

from_0to1

542

1

T13

5

T19

10

T120

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T13

9

T19

18

T120

9

auto[1]

1107

1

T13

11

T19

22

T120

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T13

13

T19

16

T120

11

auto[1]

1111

1

T13

7

T19

24

T120

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T13

1

T19

1

T120

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T120

2

T50

2

T135

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T19

1

T120

1

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T13

1

T19

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T13

1

T50

2

T351

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T19

1

T50

3

T135

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T19

1

T120

1

T50

3

auto[0]

from_0to1

auto[1]

auto[1]

90

1

T19

3

T120

1

T50

3

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T19

1

T120

1

T50

6

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T19

2

T135

1

T351

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T13

2

T19

1

T120

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T13

1

T19

1

T50

3

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T50

3

T135

1

T353

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T13

2

T19

1

T120

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T13

2

T19

3

T120

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T19

1

T120

1

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T13

9

T19

17

T120

8

auto[1]

1074

1

T13

11

T19

23

T120

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T13

5

T19

10

T120

2

from_0to1

541

1

T13

5

T19

10

T120

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T13

12

T19

14

T120

11

auto[1]

1072

1

T13

8

T19

26

T120

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T13

11

T19

22

T120

9

auto[1]

1094

1

T13

9

T19

18

T120

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T13

2

T50

5

T352

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T19

1

T50

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T19

2

T50

2

T135

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T13

1

T19

1

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T19

1

T50

4

T351

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T13

1

T19

1

T50

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T13

1

T19

2

T50

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T120

1

T351

2

T352

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T19

2

T50

1

T351

2

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T19

1

T120

1

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T13

1

T19

1

T50

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T13

1

T19

2

T120

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T13

1

T19

1

T50

3

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T13

1

T19

1

T120

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T19

3

T135

1

T352

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T13

1

T19

1

T50

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T13

9

T19

22

T120

10

auto[1]

1072

1

T13

11

T19

18

T120

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T13

5

T19

10

T120

5

from_0to1

527

1

T13

6

T19

9

T120

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T13

13

T19

18

T120

12

auto[1]

1080

1

T13

7

T19

22

T120

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T13

11

T19

17

T120

11

auto[1]

1103

1

T13

9

T19

23

T120

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T13

1

T19

1

T120

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T120

2

T50

3

T135

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T13

1

T19

1

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T13

1

T120

1

T50

5

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T13

2

T120

2

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T13

1

T19

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T50

4

T135

1

T351

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T19

3

T50

3

T351

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T13

1

T19

2

T120

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T13

1

T19

3

T351

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T19

1

T50

2

T353

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T19

2

T50

1

T135

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T13

2

T19

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T19

1

T120

1

T50

3

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T19

1

T50

1

T135

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T13

1

T19

2

T120

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T13

7

T19

21

T120

10

auto[1]

1097

1

T13

13

T19

19

T120

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

546

1

T13

4

T19

10

T120

7

from_0to1

541

1

T13

4

T19

10

T120

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T13

9

T19

22

T120

9

auto[1]

1062

1

T13

11

T19

18

T120

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T13

10

T19

20

T120

8

auto[1]

1074

1

T13

10

T19

20

T120

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T19

1

T120

1

T50

3

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T19

2

T120

1

T50

4

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T19

3

T50

3

T135

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T13

1

T120

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T13

1

T19

1

T50

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T19

1

T50

1

T135

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T50

2

T353

1

T45

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T19

2

T120

3

T50

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T13

2

T19

2

T120

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T19

1

T50

1

T351

4

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T19

1

T50

2

T351

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T13

1

T120

2

T50

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T120

2

T50

3

T135

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T19

2

T120

1

T50

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T13

3

T19

2

T120

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T19

2

T120

1

T50

2