Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120755

1

T1

32

T2

637

T6

341

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141177	1			T1	87		T2	1604		T6	83
values[0x0]	66694	1			T1	17		T2	385		T6	136
values[0x1]	67804	1			T1	24		T2	443		T6	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125853	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149822

1

T1

64

T2

1147

T6

375

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	855	1			T2	8		T6	1		T3	1
valid_sources[0x01]	1026	1			T2	9		T3	2		T7	12
valid_sources[0x02]	817	1			T2	15		T6	2		T3	7
valid_sources[0x03]	1544	1			T2	8		T3	5		T7	8
valid_sources[0x04]	1113	1			T2	5		T6	1		T3	5
valid_sources[0x05]	886	1			T2	17		T6	5		T3	3
valid_sources[0x06]	797	1			T2	7		T6	3		T3	2
valid_sources[0x07]	830	1			T2	4		T6	4		T3	6
valid_sources[0x08]	985	1			T2	7		T3	1		T7	11
valid_sources[0x09]	1326	1			T2	8		T6	1		T3	3
valid_sources[0x0a]	2715	1			T2	9		T6	3		T3	2
valid_sources[0x0b]	868	1			T2	14		T6	1		T3	4
valid_sources[0x0c]	1031	1			T2	9		T6	4		T3	2
valid_sources[0x0d]	1297	1			T2	18		T6	3		T3	6
valid_sources[0x0e]	807	1			T2	13		T6	2		T3	4
valid_sources[0x0f]	1180	1			T2	11		T6	1		T3	3
valid_sources[0x10]	1862	1			T2	5		T6	2		T3	7
valid_sources[0x11]	1141	1			T2	9		T6	2		T3	3
valid_sources[0x12]	829	1			T2	7		T6	2		T7	11
valid_sources[0x13]	902	1			T2	7		T6	2		T3	4
valid_sources[0x14]	976	1			T2	18		T6	2		T3	2
valid_sources[0x15]	1293	1			T2	8		T6	1		T3	2
valid_sources[0x16]	919	1			T2	6		T6	4		T3	5
valid_sources[0x17]	846	1			T2	4		T6	1		T3	4
valid_sources[0x18]	724	1			T2	10		T6	2		T3	2
valid_sources[0x19]	846	1			T2	14		T6	4		T3	6
valid_sources[0x1a]	769	1			T2	13		T3	3		T7	2
valid_sources[0x1b]	805	1			T2	10		T6	2		T3	1
valid_sources[0x1c]	780	1			T2	12		T3	4		T7	4
valid_sources[0x1d]	958	1			T2	7		T6	1		T3	3
valid_sources[0x1e]	1338	1			T1	2		T2	12		T6	2
valid_sources[0x1f]	833	1			T1	1		T2	12		T6	1
valid_sources[0x20]	848	1			T2	5		T6	1		T3	5
valid_sources[0x21]	959	1			T1	5		T2	9		T6	1
valid_sources[0x22]	739	1			T1	5		T2	4		T3	5
valid_sources[0x23]	914	1			T2	9		T6	3		T3	2
valid_sources[0x24]	1122	1			T2	9		T6	2		T3	5
valid_sources[0x25]	832	1			T2	6		T3	3		T7	13
valid_sources[0x26]	1137	1			T2	7		T6	1		T7	9
valid_sources[0x27]	976	1			T2	8		T6	2		T3	3
valid_sources[0x28]	990	1			T2	7		T3	5		T7	17
valid_sources[0x29]	1253	1			T2	4		T6	2		T3	1
valid_sources[0x2a]	729	1			T2	8		T6	1		T3	5
valid_sources[0x2b]	1080	1			T2	12		T6	1		T3	1
valid_sources[0x2c]	1193	1			T1	1		T2	16		T6	2
valid_sources[0x2d]	1101	1			T2	6		T6	2		T3	2
valid_sources[0x2e]	1366	1			T2	9		T6	1		T3	2
valid_sources[0x2f]	1194	1			T2	8		T6	1		T3	7
valid_sources[0x30]	893	1			T2	11		T6	1		T7	2
valid_sources[0x31]	1032	1			T2	11		T7	6		T8	8
valid_sources[0x32]	853	1			T1	3		T2	17		T3	7
valid_sources[0x33]	1061	1			T1	1		T2	13		T6	2
valid_sources[0x34]	1158	1			T2	6		T6	1		T3	6
valid_sources[0x35]	1026	1			T2	8		T6	2		T3	1
valid_sources[0x36]	1307	1			T2	9		T6	2		T3	2
valid_sources[0x37]	805	1			T2	9		T3	5		T7	18
valid_sources[0x38]	840	1			T1	1		T2	7		T6	1
valid_sources[0x39]	1015	1			T2	14		T6	3		T3	4
valid_sources[0x3a]	1026	1			T2	8		T3	7		T7	12
valid_sources[0x3b]	1208	1			T2	6		T6	1		T3	7
valid_sources[0x3c]	715	1			T2	7		T6	4		T3	6
valid_sources[0x3d]	990	1			T2	16		T6	4		T3	3
valid_sources[0x3e]	1112	1			T2	21		T3	5		T7	3
valid_sources[0x3f]	1568	1			T2	12		T6	3		T7	5
valid_sources[0x40]	891	1			T2	7		T6	5		T3	2
valid_sources[0x41]	974	1			T2	8		T6	2		T3	3
valid_sources[0x42]	913	1			T2	12		T3	2		T7	6
valid_sources[0x43]	1505	1			T2	6		T3	4		T7	10
valid_sources[0x44]	975	1			T2	7		T6	1		T3	3
valid_sources[0x45]	1891	1			T2	15		T6	1		T3	6
valid_sources[0x46]	1219	1			T1	4		T2	12		T6	3
valid_sources[0x47]	1001	1			T1	2		T2	18		T6	2
valid_sources[0x48]	837	1			T2	8		T6	1		T3	1
valid_sources[0x49]	767	1			T2	14		T6	2		T3	6
valid_sources[0x4a]	1450	1			T2	8		T6	3		T3	5
valid_sources[0x4b]	822	1			T2	10		T6	2		T3	1
valid_sources[0x4c]	1665	1			T1	1		T2	9		T3	3
valid_sources[0x4d]	1057	1			T2	12		T6	2		T3	6
valid_sources[0x4e]	820	1			T2	6		T3	2		T7	3
valid_sources[0x4f]	864	1			T2	7		T6	1		T3	5
valid_sources[0x50]	872	1			T2	8		T7	9		T8	4
valid_sources[0x51]	1082	1			T1	6		T2	7		T6	2
valid_sources[0x52]	1155	1			T1	3		T2	7		T6	1
valid_sources[0x53]	915	1			T1	4		T2	7		T6	4
valid_sources[0x54]	2253	1			T1	1		T2	13		T3	4
valid_sources[0x55]	857	1			T2	10		T6	1		T3	5
valid_sources[0x56]	1199	1			T2	12		T6	3		T3	2
valid_sources[0x57]	900	1			T2	4		T6	2		T3	3
valid_sources[0x58]	940	1			T2	8		T6	4		T3	5
valid_sources[0x59]	1072	1			T2	13		T3	1		T7	7
valid_sources[0x5a]	1020	1			T1	1		T2	12		T6	1
valid_sources[0x5b]	721	1			T2	11		T6	2		T3	6
valid_sources[0x5c]	1100	1			T2	8		T6	1		T3	2
valid_sources[0x5d]	704	1			T2	1		T3	1		T7	7
valid_sources[0x5e]	1193	1			T2	8		T6	1		T3	3
valid_sources[0x5f]	1037	1			T1	2		T2	5		T6	2
valid_sources[0x60]	1025	1			T1	4		T2	8		T3	4
valid_sources[0x61]	1108	1			T2	6		T6	1		T3	4
valid_sources[0x62]	996	1			T2	15		T6	1		T3	1
valid_sources[0x63]	985	1			T2	14		T6	1		T3	3
valid_sources[0x64]	1010	1			T2	10		T6	1		T3	8
valid_sources[0x65]	2151	1			T2	23		T6	1		T3	1
valid_sources[0x66]	866	1			T2	7		T6	2		T3	2
valid_sources[0x67]	1040	1			T2	8		T3	3		T7	7
valid_sources[0x68]	910	1			T2	9		T6	6		T3	9
valid_sources[0x69]	911	1			T2	8		T3	1		T7	9
valid_sources[0x6a]	1177	1			T2	15		T6	1		T3	1
valid_sources[0x6b]	726	1			T1	1		T2	10		T6	2
valid_sources[0x6c]	1651	1			T2	13		T6	1		T7	7
valid_sources[0x6d]	1003	1			T2	3		T6	2		T3	1
valid_sources[0x6e]	1072	1			T2	7		T6	2		T3	3
valid_sources[0x6f]	750	1			T2	4		T6	2		T3	6
valid_sources[0x70]	1110	1			T2	10		T6	2		T3	5
valid_sources[0x71]	1098	1			T2	8		T3	2		T7	7
valid_sources[0x72]	986	1			T2	15		T6	3		T3	4
valid_sources[0x73]	938	1			T2	15		T6	1		T3	4
valid_sources[0x74]	953	1			T2	15		T3	3		T7	16
valid_sources[0x75]	784	1			T2	10		T3	3		T7	8
valid_sources[0x76]	991	1			T2	15		T6	3		T3	3
valid_sources[0x77]	952	1			T1	1		T2	15		T6	1
valid_sources[0x78]	889	1			T2	7		T6	2		T3	8
valid_sources[0x79]	815	1			T2	17		T7	7		T8	6
valid_sources[0x7a]	989	1			T1	2		T2	5		T3	3
valid_sources[0x7b]	1298	1			T1	2		T2	12		T6	1
valid_sources[0x7c]	1166	1			T2	7		T6	1		T3	6
valid_sources[0x7d]	869	1			T2	15		T3	3		T7	10
valid_sources[0x7e]	965	1			T2	5		T6	2		T3	2
valid_sources[0x7f]	1632	1			T2	8		T3	2		T7	10
valid_sources[0x80]	1077	1			T1	2		T2	6		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64875

1

T1

14

T2

245

T6

75

values[0x0]

all_enables

biggest_size

32590

1

T1

6

T2

216

T6

130

values[0x1]

all_enables

biggest_size

23290

1

T1

12

T2

176

T6

136