Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
229392 |
0 |
0 |
T1 |
1330388 |
70 |
0 |
0 |
T2 |
3844153 |
1393 |
0 |
0 |
T3 |
27029675 |
783 |
0 |
0 |
T4 |
7333897 |
829 |
0 |
0 |
T5 |
7599297 |
339 |
0 |
0 |
T6 |
5420584 |
0 |
0 |
0 |
T7 |
4021345 |
1391 |
0 |
0 |
T8 |
7198164 |
514 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T10 |
0 |
353 |
0 |
0 |
T11 |
0 |
140 |
0 |
0 |
T22 |
965211 |
0 |
0 |
0 |
T23 |
3509070 |
0 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
233523 |
0 |
0 |
T1 |
1488092 |
70 |
0 |
0 |
T2 |
4237557 |
1396 |
0 |
0 |
T3 |
30292135 |
783 |
0 |
0 |
T4 |
8207293 |
829 |
0 |
0 |
T5 |
8511973 |
340 |
0 |
0 |
T6 |
6073976 |
0 |
0 |
0 |
T7 |
4435565 |
1391 |
0 |
0 |
T8 |
8032996 |
698 |
0 |
0 |
T9 |
0 |
70 |
0 |
0 |
T10 |
0 |
670 |
0 |
0 |
T11 |
0 |
140 |
0 |
0 |
T22 |
1078719 |
0 |
0 |
0 |
T23 |
3930670 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1959 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
2066 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
2042 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
2042 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
975 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
4 |
0 |
0 |
T4 |
1834 |
6 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1085 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
4 |
0 |
0 |
T4 |
220183 |
6 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1063 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
4 |
0 |
0 |
T4 |
220183 |
6 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1063 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
4 |
0 |
0 |
T4 |
1834 |
6 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
984 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
14 |
0 |
0 |
T4 |
1834 |
22 |
0 |
0 |
T5 |
996 |
9 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1093 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
14 |
0 |
0 |
T4 |
220183 |
22 |
0 |
0 |
T5 |
229165 |
9 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1067 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
14 |
0 |
0 |
T4 |
220183 |
22 |
0 |
0 |
T5 |
229165 |
9 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1067 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
14 |
0 |
0 |
T4 |
1834 |
22 |
0 |
0 |
T5 |
996 |
9 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
998 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1104 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
9 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1081 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
9 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1081 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
9 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
972 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1082 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1059 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1059 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T5,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
489 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
1 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
601 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
1 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1049 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
5 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1170 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
5 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
2915 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
14 |
0 |
0 |
T5 |
996 |
10 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
3023 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
14 |
0 |
0 |
T5 |
229165 |
10 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
2997 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
14 |
0 |
0 |
T5 |
229165 |
10 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
2997 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
14 |
0 |
0 |
T5 |
996 |
10 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6316 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
6431 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
6403 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6403 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7424 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
15 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7541 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
15 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7515 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
15 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7515 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
15 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6184 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
7 |
0 |
0 |
T4 |
1834 |
9 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
6303 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
7 |
0 |
0 |
T4 |
220183 |
9 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
6276 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
7 |
0 |
0 |
T4 |
220183 |
9 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6276 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
7 |
0 |
0 |
T4 |
1834 |
9 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1015 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1124 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1101 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1101 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1930 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
2037 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
2011 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
2011 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1333 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
7 |
0 |
0 |
T4 |
1834 |
6 |
0 |
0 |
T5 |
996 |
9 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1446 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
7 |
0 |
0 |
T4 |
220183 |
6 |
0 |
0 |
T5 |
229165 |
9 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1423 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
7 |
0 |
0 |
T4 |
220183 |
6 |
0 |
0 |
T5 |
229165 |
9 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1423 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
7 |
0 |
0 |
T4 |
1834 |
6 |
0 |
0 |
T5 |
996 |
9 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1165 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
21 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1272 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
21 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1249 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
21 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1249 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
21 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6926 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7034 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7011 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7011 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6940 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7055 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7031 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7031 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7150 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
14 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7264 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
14 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7242 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
14 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7242 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
14 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
6991 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
15 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
2 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7106 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
15 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
2 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7081 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
15 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
2 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7081 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
15 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
2 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1227 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
19 |
0 |
0 |
T4 |
1834 |
11 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1337 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
19 |
0 |
0 |
T4 |
220183 |
11 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1313 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
19 |
0 |
0 |
T4 |
220183 |
11 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1313 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
19 |
0 |
0 |
T4 |
1834 |
11 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1200 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
15 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
7 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1311 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
15 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
7 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1287 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
15 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
7 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1287 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
15 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
7 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1204 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
22 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1315 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
22 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1291 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
22 |
0 |
0 |
T4 |
220183 |
10 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1291 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
22 |
0 |
0 |
T4 |
1834 |
10 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1192 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1303 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1280 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1280 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7620 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
18 |
0 |
0 |
T3 |
1634 |
23 |
0 |
0 |
T4 |
1834 |
11 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7733 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
19 |
0 |
0 |
T3 |
817249 |
23 |
0 |
0 |
T4 |
220183 |
11 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7709 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
19 |
0 |
0 |
T3 |
817249 |
23 |
0 |
0 |
T4 |
220183 |
11 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7709 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
19 |
0 |
0 |
T3 |
1634 |
23 |
0 |
0 |
T4 |
1834 |
11 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7489 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7603 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7580 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
12 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7580 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
12 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7681 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
10 |
0 |
0 |
T4 |
1834 |
8 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7794 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
10 |
0 |
0 |
T4 |
220183 |
8 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7769 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
10 |
0 |
0 |
T4 |
220183 |
8 |
0 |
0 |
T5 |
229165 |
3 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7769 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
10 |
0 |
0 |
T4 |
1834 |
8 |
0 |
0 |
T5 |
996 |
3 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7598 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
23 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7715 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
23 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
7691 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
6 |
0 |
0 |
T4 |
220183 |
23 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
7691 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
6 |
0 |
0 |
T4 |
1834 |
23 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1816 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
19 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
8 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1924 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
8 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1904 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
8 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1904 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
8 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1794 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
20 |
0 |
0 |
T5 |
996 |
2 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1904 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
20 |
0 |
0 |
T5 |
229165 |
2 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1884 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
20 |
0 |
0 |
T5 |
229165 |
2 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1884 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
20 |
0 |
0 |
T5 |
996 |
2 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1777 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
10 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1888 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
11 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1868 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
8 |
0 |
0 |
T4 |
220183 |
7 |
0 |
0 |
T5 |
229165 |
11 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1868 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
8 |
0 |
0 |
T4 |
1834 |
7 |
0 |
0 |
T5 |
996 |
11 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1761 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
16 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1870 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
16 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1845 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
16 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1845 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
16 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1849 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
19 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1960 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1935 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
12 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
5 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1935 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
12 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
5 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
9 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1753 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
3 |
0 |
0 |
T4 |
1834 |
5 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1864 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
3 |
0 |
0 |
T4 |
220183 |
5 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1840 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
3 |
0 |
0 |
T4 |
220183 |
5 |
0 |
0 |
T5 |
229165 |
4 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1840 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
3 |
0 |
0 |
T4 |
1834 |
5 |
0 |
0 |
T5 |
996 |
4 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1775 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
19 |
0 |
0 |
T3 |
1634 |
17 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1890 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
19 |
0 |
0 |
T3 |
817249 |
17 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1863 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
19 |
0 |
0 |
T3 |
817249 |
17 |
0 |
0 |
T4 |
220183 |
19 |
0 |
0 |
T5 |
229165 |
1 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1863 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
19 |
0 |
0 |
T3 |
1634 |
17 |
0 |
0 |
T4 |
1834 |
19 |
0 |
0 |
T5 |
996 |
1 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1772 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
21 |
0 |
0 |
T4 |
1834 |
4 |
0 |
0 |
T5 |
996 |
8 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1884 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
21 |
0 |
0 |
T4 |
220183 |
4 |
0 |
0 |
T5 |
229165 |
8 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1861 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
21 |
0 |
0 |
T4 |
220183 |
4 |
0 |
0 |
T5 |
229165 |
8 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1861 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
21 |
0 |
0 |
T4 |
1834 |
4 |
0 |
0 |
T5 |
996 |
8 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
1008 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
11 |
0 |
0 |
T4 |
1834 |
14 |
0 |
0 |
T5 |
996 |
6 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
19 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
1121 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
11 |
0 |
0 |
T4 |
220183 |
14 |
0 |
0 |
T5 |
229165 |
6 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
19 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T6 |
0 |
Covered |
T1,T2,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8207905 |
589 |
0 |
0 |
T1 |
419 |
1 |
0 |
0 |
T2 |
8551 |
20 |
0 |
0 |
T3 |
1634 |
13 |
0 |
0 |
T4 |
1834 |
6 |
0 |
0 |
T5 |
996 |
7 |
0 |
0 |
T6 |
430 |
0 |
0 |
0 |
T7 |
8629 |
20 |
0 |
0 |
T8 |
4440 |
5 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
411 |
0 |
0 |
0 |
T23 |
441 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1235371660 |
698 |
0 |
0 |
T1 |
39845 |
1 |
0 |
0 |
T2 |
106902 |
20 |
0 |
0 |
T3 |
817249 |
13 |
0 |
0 |
T4 |
220183 |
6 |
0 |
0 |
T5 |
229165 |
7 |
0 |
0 |
T6 |
163778 |
0 |
0 |
0 |
T7 |
112184 |
20 |
0 |
0 |
T8 |
213148 |
10 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T22 |
28788 |
0 |
0 |
0 |
T23 |
105841 |
0 |
0 |
0 |