Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.31 96.35 100.00 96.15 98.68 99.44 94.29


Total test records in report: 916
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T171 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.807667630 Oct 08 01:27:44 PM PDT 23 Oct 08 01:27:53 PM PDT 23 2864293495 ps
T75 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1110712484 Oct 08 01:22:28 PM PDT 23 Oct 08 01:22:35 PM PDT 23 5118524891 ps
T143 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1090003375 Oct 08 01:23:02 PM PDT 23 Oct 08 01:23:12 PM PDT 23 3640428864 ps
T144 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3595134407 Oct 08 01:19:26 PM PDT 23 Oct 08 01:21:55 PM PDT 23 60070076937 ps
T145 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4151216362 Oct 08 01:34:44 PM PDT 23 Oct 08 01:34:48 PM PDT 23 2516582870 ps
T146 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.4220265147 Oct 08 01:21:01 PM PDT 23 Oct 08 01:21:08 PM PDT 23 2451798406 ps
T235 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3253477378 Oct 08 01:24:11 PM PDT 23 Oct 08 01:24:42 PM PDT 23 48018144480 ps
T90 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.848835485 Oct 08 01:20:42 PM PDT 23 Oct 08 01:21:24 PM PDT 23 31042377918 ps
T438 /workspace/coverage/default/38.sysrst_ctrl_stress_all.1000679409 Oct 08 01:31:06 PM PDT 23 Oct 08 01:31:11 PM PDT 23 13599379090 ps
T439 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.535139687 Oct 08 01:24:32 PM PDT 23 Oct 08 01:24:38 PM PDT 23 3179250365 ps
T236 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2361504131 Oct 08 01:23:09 PM PDT 23 Oct 08 01:23:55 PM PDT 23 63614454312 ps
T440 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3803024858 Oct 08 01:25:17 PM PDT 23 Oct 08 01:25:19 PM PDT 23 2259276813 ps
T441 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2153688377 Oct 08 01:28:36 PM PDT 23 Oct 08 01:28:38 PM PDT 23 2539238949 ps
T91 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3705915816 Oct 08 01:21:07 PM PDT 23 Oct 08 01:22:12 PM PDT 23 100185868027 ps
T92 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3203045988 Oct 08 01:30:09 PM PDT 23 Oct 08 01:31:25 PM PDT 23 28827719556 ps
T65 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1703863545 Oct 08 01:32:15 PM PDT 23 Oct 08 01:40:06 PM PDT 23 180038707238 ps
T442 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2242118847 Oct 08 01:43:51 PM PDT 23 Oct 08 01:43:55 PM PDT 23 2522920334 ps
T443 /workspace/coverage/default/19.sysrst_ctrl_smoke.3913317652 Oct 08 01:25:47 PM PDT 23 Oct 08 01:25:53 PM PDT 23 2112363190 ps
T444 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1453749067 Oct 08 01:26:24 PM PDT 23 Oct 08 01:26:32 PM PDT 23 2714390410 ps
T445 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4211539758 Oct 08 01:24:03 PM PDT 23 Oct 08 01:25:49 PM PDT 23 41484951190 ps
T239 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3799182023 Oct 08 01:24:01 PM PDT 23 Oct 08 01:26:28 PM PDT 23 106663554799 ps
T446 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.2549645406 Oct 08 01:21:31 PM PDT 23 Oct 08 01:21:34 PM PDT 23 2482634729 ps
T447 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.844000869 Oct 08 01:40:12 PM PDT 23 Oct 08 01:40:25 PM PDT 23 4753350702 ps
T448 /workspace/coverage/default/12.sysrst_ctrl_smoke.3054011336 Oct 08 01:21:39 PM PDT 23 Oct 08 01:21:41 PM PDT 23 2134121851 ps
T80 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.311819062 Oct 08 01:26:48 PM PDT 23 Oct 08 01:26:50 PM PDT 23 3454821052 ps
T449 /workspace/coverage/default/18.sysrst_ctrl_stress_all.1514608526 Oct 08 01:26:52 PM PDT 23 Oct 08 01:40:15 PM PDT 23 1379476339626 ps
T450 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1827491221 Oct 08 01:21:39 PM PDT 23 Oct 08 01:21:42 PM PDT 23 2522534804 ps
T451 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.735599163 Oct 08 01:21:27 PM PDT 23 Oct 08 01:21:28 PM PDT 23 2785074414 ps
T452 /workspace/coverage/default/37.sysrst_ctrl_smoke.63195448 Oct 08 01:23:15 PM PDT 23 Oct 08 01:23:17 PM PDT 23 2123065859 ps
T233 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.810914579 Oct 08 01:26:36 PM PDT 23 Oct 08 01:26:48 PM PDT 23 25613609450 ps
T453 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2304960981 Oct 08 01:20:17 PM PDT 23 Oct 08 01:20:23 PM PDT 23 2452767429 ps
T454 /workspace/coverage/default/41.sysrst_ctrl_alert_test.3120214655 Oct 08 01:28:55 PM PDT 23 Oct 08 01:28:56 PM PDT 23 2067876633 ps
T455 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1477245653 Oct 08 01:22:10 PM PDT 23 Oct 08 01:22:15 PM PDT 23 3046267823 ps
T130 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.103593540 Oct 08 01:30:31 PM PDT 23 Oct 08 01:30:59 PM PDT 23 13621504983 ps
T175 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1942823505 Oct 08 01:32:41 PM PDT 23 Oct 08 01:32:43 PM PDT 23 3201801904 ps
T202 /workspace/coverage/default/15.sysrst_ctrl_stress_all.2835867725 Oct 08 01:21:09 PM PDT 23 Oct 08 01:21:13 PM PDT 23 6803364515 ps
T203 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2291631485 Oct 08 01:33:44 PM PDT 23 Oct 08 01:37:48 PM PDT 23 90552568643 ps
T81 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2688261429 Oct 08 01:23:45 PM PDT 23 Oct 08 01:23:51 PM PDT 23 165284368430 ps
T197 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.579059314 Oct 08 01:32:47 PM PDT 23 Oct 08 01:32:49 PM PDT 23 2680362605 ps
T204 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1546892827 Oct 08 01:23:15 PM PDT 23 Oct 08 01:23:21 PM PDT 23 2830174033 ps
T205 /workspace/coverage/default/13.sysrst_ctrl_stress_all.4175875299 Oct 08 01:23:23 PM PDT 23 Oct 08 01:24:07 PM PDT 23 16234703228 ps
T206 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.538266632 Oct 08 01:31:13 PM PDT 23 Oct 08 01:31:16 PM PDT 23 3520738708 ps
T207 /workspace/coverage/default/48.sysrst_ctrl_stress_all.1045534743 Oct 08 01:33:51 PM PDT 23 Oct 08 01:34:00 PM PDT 23 13721383161 ps
T156 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.627645698 Oct 08 01:32:56 PM PDT 23 Oct 08 01:33:09 PM PDT 23 4731726304 ps
T456 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1957451862 Oct 08 01:21:57 PM PDT 23 Oct 08 01:32:42 PM PDT 23 261451079973 ps
T457 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1040360750 Oct 08 01:40:28 PM PDT 23 Oct 08 01:40:30 PM PDT 23 2474772500 ps
T458 /workspace/coverage/default/19.sysrst_ctrl_alert_test.4254042653 Oct 08 01:22:34 PM PDT 23 Oct 08 01:22:42 PM PDT 23 2016844514 ps
T459 /workspace/coverage/default/38.sysrst_ctrl_alert_test.1414138051 Oct 08 01:25:20 PM PDT 23 Oct 08 01:25:22 PM PDT 23 2028206815 ps
T460 /workspace/coverage/default/28.sysrst_ctrl_alert_test.3415855637 Oct 08 01:27:46 PM PDT 23 Oct 08 01:27:52 PM PDT 23 2011535777 ps
T322 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2183526577 Oct 08 01:26:20 PM PDT 23 Oct 08 01:26:50 PM PDT 23 61301402788 ps
T151 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.3977028574 Oct 08 01:20:05 PM PDT 23 Oct 08 01:20:21 PM PDT 23 6122077230 ps
T331 /workspace/coverage/default/17.sysrst_ctrl_stress_all.554585783 Oct 08 01:21:48 PM PDT 23 Oct 08 01:22:53 PM PDT 23 95928307586 ps
T461 /workspace/coverage/default/25.sysrst_ctrl_smoke.3766538758 Oct 08 01:24:48 PM PDT 23 Oct 08 01:24:49 PM PDT 23 2143989038 ps
T462 /workspace/coverage/default/2.sysrst_ctrl_alert_test.3360837526 Oct 08 01:20:23 PM PDT 23 Oct 08 01:20:27 PM PDT 23 2020395615 ps
T463 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3768234678 Oct 08 01:24:24 PM PDT 23 Oct 08 01:26:04 PM PDT 23 77452751735 ps
T464 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3182570609 Oct 08 01:24:32 PM PDT 23 Oct 08 01:24:35 PM PDT 23 3543057533 ps
T240 /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1602694618 Oct 08 01:26:16 PM PDT 23 Oct 08 01:29:08 PM PDT 23 69734034239 ps
T72 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.4214158210 Oct 08 01:28:07 PM PDT 23 Oct 08 01:33:35 PM PDT 23 132445534556 ps
T465 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3088352211 Oct 08 01:23:43 PM PDT 23 Oct 08 01:23:49 PM PDT 23 2039639990 ps
T466 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3288726652 Oct 08 01:24:29 PM PDT 23 Oct 08 01:24:33 PM PDT 23 2518234266 ps
T467 /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.127977026 Oct 08 01:30:42 PM PDT 23 Oct 08 01:30:45 PM PDT 23 3679471442 ps
T468 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1160236573 Oct 08 01:32:45 PM PDT 23 Oct 08 01:32:53 PM PDT 23 2658231291 ps
T469 /workspace/coverage/default/47.sysrst_ctrl_stress_all.1719340666 Oct 08 01:37:44 PM PDT 23 Oct 08 01:38:09 PM PDT 23 10728523293 ps
T470 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2410229778 Oct 08 01:25:13 PM PDT 23 Oct 08 01:25:21 PM PDT 23 2510460027 ps
T471 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3195406397 Oct 08 01:23:53 PM PDT 23 Oct 08 01:24:00 PM PDT 23 2172536944 ps
T472 /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2114627535 Oct 08 01:25:52 PM PDT 23 Oct 08 01:25:55 PM PDT 23 2621511594 ps
T473 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1270120457 Oct 08 01:19:37 PM PDT 23 Oct 08 01:19:46 PM PDT 23 3450036821 ps
T474 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.10148266 Oct 08 01:20:17 PM PDT 23 Oct 08 01:20:21 PM PDT 23 2476467758 ps
T475 /workspace/coverage/default/37.sysrst_ctrl_stress_all.2965684246 Oct 08 01:26:22 PM PDT 23 Oct 08 01:26:56 PM PDT 23 12608433990 ps
T476 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1058710197 Oct 08 01:32:13 PM PDT 23 Oct 08 01:32:19 PM PDT 23 2610884966 ps
T477 /workspace/coverage/default/22.sysrst_ctrl_smoke.2334517074 Oct 08 01:23:10 PM PDT 23 Oct 08 01:23:16 PM PDT 23 2108148413 ps
T478 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.4276345770 Oct 08 01:40:41 PM PDT 23 Oct 08 01:40:47 PM PDT 23 3326185002 ps
T232 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.447687185 Oct 08 01:22:50 PM PDT 23 Oct 08 01:23:12 PM PDT 23 32753014122 ps
T93 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2312100620 Oct 08 01:32:49 PM PDT 23 Oct 08 01:34:52 PM PDT 23 101915603369 ps
T479 /workspace/coverage/default/3.sysrst_ctrl_smoke.2613633138 Oct 08 01:20:23 PM PDT 23 Oct 08 01:20:27 PM PDT 23 2115909803 ps
T480 /workspace/coverage/default/1.sysrst_ctrl_smoke.1736380037 Oct 08 01:38:38 PM PDT 23 Oct 08 01:38:40 PM PDT 23 2124543135 ps
T123 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.629614128 Oct 08 01:28:38 PM PDT 23 Oct 08 01:28:41 PM PDT 23 5302264242 ps
T481 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1977175873 Oct 08 01:35:30 PM PDT 23 Oct 08 01:35:33 PM PDT 23 2623251619 ps
T482 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.843685416 Oct 08 01:29:13 PM PDT 23 Oct 08 01:29:14 PM PDT 23 2601212021 ps
T152 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1580679347 Oct 08 01:26:10 PM PDT 23 Oct 08 01:26:14 PM PDT 23 3257275190 ps
T483 /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1771103783 Oct 08 01:20:25 PM PDT 23 Oct 08 01:20:28 PM PDT 23 3292959292 ps
T484 /workspace/coverage/default/45.sysrst_ctrl_smoke.699506049 Oct 08 01:29:16 PM PDT 23 Oct 08 01:29:20 PM PDT 23 2114761238 ps
T485 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.699157435 Oct 08 01:23:19 PM PDT 23 Oct 08 01:24:27 PM PDT 23 99492624423 ps
T486 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3362983257 Oct 08 01:25:53 PM PDT 23 Oct 08 01:26:03 PM PDT 23 3520832794 ps
T320 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1272615703 Oct 08 01:21:10 PM PDT 23 Oct 08 01:22:08 PM PDT 23 40891781948 ps
T487 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3183134508 Oct 08 01:24:14 PM PDT 23 Oct 08 01:24:17 PM PDT 23 9911111778 ps
T488 /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2192782696 Oct 08 01:34:27 PM PDT 23 Oct 08 01:41:27 PM PDT 23 321896273083 ps
T124 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2452565034 Oct 08 01:23:53 PM PDT 23 Oct 08 01:24:01 PM PDT 23 5847735317 ps
T489 /workspace/coverage/default/49.sysrst_ctrl_stress_all.2732334399 Oct 08 01:26:25 PM PDT 23 Oct 08 01:26:43 PM PDT 23 9125352101 ps
T490 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.797452752 Oct 08 01:23:12 PM PDT 23 Oct 08 01:23:15 PM PDT 23 3387114080 ps
T317 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3768476130 Oct 08 01:27:20 PM PDT 23 Oct 08 01:27:59 PM PDT 23 72773868110 ps
T491 /workspace/coverage/default/33.sysrst_ctrl_alert_test.2939787641 Oct 08 01:31:52 PM PDT 23 Oct 08 01:31:59 PM PDT 23 2013040346 ps
T492 /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1266455080 Oct 08 01:25:35 PM PDT 23 Oct 08 01:25:39 PM PDT 23 2903589949 ps
T493 /workspace/coverage/default/32.sysrst_ctrl_smoke.3308771897 Oct 08 01:24:32 PM PDT 23 Oct 08 01:24:39 PM PDT 23 2110489109 ps
T494 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3716097141 Oct 08 01:35:51 PM PDT 23 Oct 08 01:35:58 PM PDT 23 2190377958 ps
T495 /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3263715687 Oct 08 01:22:43 PM PDT 23 Oct 08 01:22:51 PM PDT 23 2514130062 ps
T496 /workspace/coverage/default/9.sysrst_ctrl_stress_all.3522289192 Oct 08 01:21:02 PM PDT 23 Oct 08 01:21:17 PM PDT 23 6023374237 ps
T497 /workspace/coverage/default/25.sysrst_ctrl_alert_test.3904421221 Oct 08 01:22:14 PM PDT 23 Oct 08 01:22:16 PM PDT 23 2027262788 ps
T157 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1982470338 Oct 08 01:22:37 PM PDT 23 Oct 08 01:22:44 PM PDT 23 2679002919 ps
T189 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2137013040 Oct 08 01:32:07 PM PDT 23 Oct 08 01:32:11 PM PDT 23 3077996162 ps
T217 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1520324853 Oct 08 01:20:32 PM PDT 23 Oct 08 01:20:39 PM PDT 23 2613823321 ps
T218 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2687680047 Oct 08 01:30:44 PM PDT 23 Oct 08 01:30:47 PM PDT 23 2634464170 ps
T219 /workspace/coverage/default/42.sysrst_ctrl_alert_test.4102746468 Oct 08 01:25:17 PM PDT 23 Oct 08 01:25:19 PM PDT 23 2025308682 ps
T220 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2003531314 Oct 08 01:25:11 PM PDT 23 Oct 08 01:25:20 PM PDT 23 3193846939 ps
T221 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3810886437 Oct 08 01:23:58 PM PDT 23 Oct 08 01:24:00 PM PDT 23 66165463234 ps
T222 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3703460303 Oct 08 01:21:04 PM PDT 23 Oct 08 01:21:07 PM PDT 23 2514482532 ps
T498 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.157509791 Oct 08 01:24:55 PM PDT 23 Oct 08 01:24:59 PM PDT 23 2440949995 ps
T499 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2003172861 Oct 08 01:21:58 PM PDT 23 Oct 08 01:23:28 PM PDT 23 68772633665 ps
T318 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1776840011 Oct 08 01:28:22 PM PDT 23 Oct 08 01:29:44 PM PDT 23 116268063817 ps
T500 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1981581768 Oct 08 01:22:36 PM PDT 23 Oct 08 01:22:43 PM PDT 23 2608523631 ps
T501 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3278971585 Oct 08 01:24:53 PM PDT 23 Oct 08 01:24:59 PM PDT 23 2077217654 ps
T502 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3133315621 Oct 08 01:38:45 PM PDT 23 Oct 08 01:38:55 PM PDT 23 3609610226 ps
T503 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3018850364 Oct 08 01:31:43 PM PDT 23 Oct 08 01:31:51 PM PDT 23 2507802228 ps
T504 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1166861591 Oct 08 01:23:52 PM PDT 23 Oct 08 01:23:59 PM PDT 23 2050669514 ps
T505 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3519652225 Oct 08 01:25:26 PM PDT 23 Oct 08 01:25:34 PM PDT 23 3097595707 ps
T158 /workspace/coverage/default/2.sysrst_ctrl_stress_all.4073719492 Oct 08 01:20:31 PM PDT 23 Oct 08 01:20:44 PM PDT 23 12867328214 ps
T506 /workspace/coverage/default/24.sysrst_ctrl_alert_test.1281512068 Oct 08 01:33:55 PM PDT 23 Oct 08 01:33:57 PM PDT 23 2019332267 ps
T507 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3945017939 Oct 08 01:23:27 PM PDT 23 Oct 08 01:23:34 PM PDT 23 2427743456 ps
T508 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.1158382856 Oct 08 01:26:23 PM PDT 23 Oct 08 01:26:26 PM PDT 23 2526532217 ps
T509 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1009811988 Oct 08 01:21:53 PM PDT 23 Oct 08 01:22:02 PM PDT 23 2611881866 ps
T510 /workspace/coverage/default/13.sysrst_ctrl_alert_test.2255907844 Oct 08 01:35:30 PM PDT 23 Oct 08 01:35:34 PM PDT 23 2017121690 ps
T511 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4235962459 Oct 08 01:36:12 PM PDT 23 Oct 08 01:36:16 PM PDT 23 2615897281 ps
T159 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3424882519 Oct 08 01:38:45 PM PDT 23 Oct 08 01:39:28 PM PDT 23 66843630699 ps
T214 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2592379693 Oct 08 01:21:13 PM PDT 23 Oct 08 01:21:23 PM PDT 23 3592831675 ps
T215 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1047906482 Oct 08 01:23:36 PM PDT 23 Oct 08 01:23:45 PM PDT 23 3608496124 ps
T216 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2852644533 Oct 08 01:39:38 PM PDT 23 Oct 08 01:40:33 PM PDT 23 79290662971 ps
T76 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3465653328 Oct 08 01:29:14 PM PDT 23 Oct 08 01:29:17 PM PDT 23 6143860934 ps
T147 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.159405536 Oct 08 01:25:17 PM PDT 23 Oct 08 01:25:18 PM PDT 23 2926536440 ps
T148 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.614981806 Oct 08 01:33:49 PM PDT 23 Oct 08 01:33:57 PM PDT 23 2510826830 ps
T149 /workspace/coverage/default/0.sysrst_ctrl_stress_all.1708667722 Oct 08 01:10:45 PM PDT 23 Oct 08 01:14:16 PM PDT 23 78730836969 ps
T150 /workspace/coverage/default/5.sysrst_ctrl_smoke.419535003 Oct 08 01:20:28 PM PDT 23 Oct 08 01:20:34 PM PDT 23 2112022142 ps
T329 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.421307798 Oct 08 01:34:25 PM PDT 23 Oct 08 01:35:38 PM PDT 23 51149566220 ps
T187 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.1818015777 Oct 08 01:23:22 PM PDT 23 Oct 08 01:23:26 PM PDT 23 3680054089 ps
T77 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.174450624 Oct 08 01:23:49 PM PDT 23 Oct 08 01:23:54 PM PDT 23 13129897844 ps
T172 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1791851392 Oct 08 01:24:49 PM PDT 23 Oct 08 01:25:01 PM PDT 23 4678614497 ps
T66 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2068417719 Oct 08 01:07:14 PM PDT 23 Oct 08 01:08:20 PM PDT 23 90024916084 ps
T512 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.698487324 Oct 08 01:33:11 PM PDT 23 Oct 08 01:33:13 PM PDT 23 4174130801 ps
T513 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3206561463 Oct 08 01:30:49 PM PDT 23 Oct 08 01:30:52 PM PDT 23 2277870526 ps
T514 /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1550796558 Oct 08 01:22:47 PM PDT 23 Oct 08 01:22:50 PM PDT 23 2041724932 ps
T515 /workspace/coverage/default/34.sysrst_ctrl_alert_test.1121475252 Oct 08 01:27:13 PM PDT 23 Oct 08 01:27:15 PM PDT 23 2037429277 ps
T516 /workspace/coverage/default/30.sysrst_ctrl_smoke.1039492347 Oct 08 01:32:32 PM PDT 23 Oct 08 01:32:33 PM PDT 23 2159613147 ps
T517 /workspace/coverage/default/3.sysrst_ctrl_alert_test.1943543850 Oct 08 01:20:18 PM PDT 23 Oct 08 01:20:21 PM PDT 23 2039041749 ps
T338 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3014862177 Oct 08 01:32:38 PM PDT 23 Oct 08 01:34:04 PM PDT 23 111782439584 ps
T518 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.496914422 Oct 08 01:32:14 PM PDT 23 Oct 08 01:32:21 PM PDT 23 2761748427 ps
T519 /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3837276573 Oct 08 01:22:23 PM PDT 23 Oct 08 01:22:30 PM PDT 23 2466471726 ps
T520 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3713999392 Oct 08 01:32:59 PM PDT 23 Oct 08 01:33:04 PM PDT 23 2209221578 ps
T521 /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3480194200 Oct 08 01:21:17 PM PDT 23 Oct 08 01:21:18 PM PDT 23 2664192052 ps
T522 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3221810464 Oct 08 01:22:25 PM PDT 23 Oct 08 01:22:27 PM PDT 23 2540992426 ps
T523 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2872189412 Oct 08 01:31:22 PM PDT 23 Oct 08 01:31:26 PM PDT 23 3326555575 ps
T524 /workspace/coverage/default/28.sysrst_ctrl_smoke.2029391982 Oct 08 01:22:27 PM PDT 23 Oct 08 01:22:30 PM PDT 23 2116708278 ps
T525 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1064709206 Oct 08 01:25:58 PM PDT 23 Oct 08 01:26:00 PM PDT 23 2652721174 ps
T248 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2368609254 Oct 08 01:30:29 PM PDT 23 Oct 08 01:32:08 PM PDT 23 138742468299 ps
T526 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.190677706 Oct 08 01:29:29 PM PDT 23 Oct 08 01:29:32 PM PDT 23 3058789279 ps
T527 /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3066033810 Oct 08 01:36:39 PM PDT 23 Oct 08 01:36:48 PM PDT 23 2610299501 ps
T319 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4258900568 Oct 08 01:28:57 PM PDT 23 Oct 08 01:33:52 PM PDT 23 119449840609 ps
T94 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1099168252 Oct 08 01:25:20 PM PDT 23 Oct 08 01:25:30 PM PDT 23 3888068901 ps
T528 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.4036454455 Oct 08 01:24:08 PM PDT 23 Oct 08 01:24:16 PM PDT 23 2609143694 ps
T529 /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.662342421 Oct 08 01:22:34 PM PDT 23 Oct 08 01:22:38 PM PDT 23 2500415798 ps
T530 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.4124049830 Oct 08 01:23:47 PM PDT 23 Oct 08 01:23:48 PM PDT 23 3689367433 ps
T531 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3865805499 Oct 08 01:19:35 PM PDT 23 Oct 08 01:19:43 PM PDT 23 2424063473 ps
T178 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3664288879 Oct 08 01:22:16 PM PDT 23 Oct 08 01:22:18 PM PDT 23 2680379698 ps
T181 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1308520382 Oct 08 01:26:02 PM PDT 23 Oct 08 01:27:23 PM PDT 23 105327056932 ps
T182 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.840097448 Oct 08 01:25:35 PM PDT 23 Oct 08 01:25:46 PM PDT 23 4089147225 ps
T183 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.23434877 Oct 08 01:20:18 PM PDT 23 Oct 08 01:20:21 PM PDT 23 2535777905 ps
T184 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.4004851192 Oct 08 01:20:50 PM PDT 23 Oct 08 01:22:35 PM PDT 23 42953692659 ps
T185 /workspace/coverage/default/35.sysrst_ctrl_smoke.2375028683 Oct 08 01:23:13 PM PDT 23 Oct 08 01:23:16 PM PDT 23 2120085046 ps
T532 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3959586438 Oct 08 01:22:28 PM PDT 23 Oct 08 01:22:36 PM PDT 23 2610727478 ps
T343 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3925960178 Oct 08 01:27:10 PM PDT 23 Oct 08 01:28:09 PM PDT 23 46174128506 ps
T533 /workspace/coverage/default/24.sysrst_ctrl_smoke.3958467865 Oct 08 01:23:36 PM PDT 23 Oct 08 01:23:42 PM PDT 23 2110975054 ps
T534 /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2674585547 Oct 08 01:12:39 PM PDT 23 Oct 08 01:12:41 PM PDT 23 2857698468 ps
T535 /workspace/coverage/default/15.sysrst_ctrl_alert_test.1929983798 Oct 08 01:21:04 PM PDT 23 Oct 08 01:21:06 PM PDT 23 2040631547 ps
T308 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2076223418 Oct 08 03:51:29 PM PDT 23 Oct 08 03:55:54 PM PDT 23 105976501042 ps
T536 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3200416134 Oct 08 01:21:12 PM PDT 23 Oct 08 01:21:20 PM PDT 23 2511789719 ps
T537 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1485856177 Oct 08 01:20:52 PM PDT 23 Oct 08 01:20:57 PM PDT 23 2515541849 ps
T299 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3017214754 Oct 08 01:25:01 PM PDT 23 Oct 08 01:26:48 PM PDT 23 176990950105 ps
T538 /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4180053159 Oct 08 01:23:50 PM PDT 23 Oct 08 01:24:00 PM PDT 23 3160625096 ps
T539 /workspace/coverage/default/6.sysrst_ctrl_smoke.2372122456 Oct 08 01:20:29 PM PDT 23 Oct 08 01:20:35 PM PDT 23 2110099248 ps
T540 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3169006277 Oct 08 01:25:24 PM PDT 23 Oct 08 01:25:37 PM PDT 23 22677727271 ps
T541 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4032752085 Oct 08 01:42:20 PM PDT 23 Oct 08 01:42:24 PM PDT 23 2618921101 ps
T95 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.506381669 Oct 08 01:27:52 PM PDT 23 Oct 08 01:29:06 PM PDT 23 121256367993 ps
T542 /workspace/coverage/default/36.sysrst_ctrl_smoke.1714473676 Oct 08 01:30:11 PM PDT 23 Oct 08 01:30:14 PM PDT 23 2116477851 ps
T543 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2530795479 Oct 08 01:21:53 PM PDT 23 Oct 08 01:21:57 PM PDT 23 2519692953 ps
T544 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2654470167 Oct 08 12:34:19 PM PDT 23 Oct 08 12:34:21 PM PDT 23 2265313612 ps
T316 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1851457871 Oct 08 01:32:28 PM PDT 23 Oct 08 01:33:11 PM PDT 23 62687011229 ps
T302 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1662561730 Oct 08 01:27:07 PM PDT 23 Oct 08 01:29:31 PM PDT 23 107902771792 ps
T545 /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.914406039 Oct 08 12:38:53 PM PDT 23 Oct 08 12:39:03 PM PDT 23 3745075632 ps
T160 /workspace/coverage/default/23.sysrst_ctrl_stress_all.1462923076 Oct 08 01:27:13 PM PDT 23 Oct 08 02:12:06 PM PDT 23 1379287441019 ps
T125 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2434529749 Oct 08 01:23:50 PM PDT 23 Oct 08 01:23:59 PM PDT 23 3643447967 ps
T324 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2693588407 Oct 08 01:21:50 PM PDT 23 Oct 08 01:23:19 PM PDT 23 130275036333 ps
T546 /workspace/coverage/default/39.sysrst_ctrl_smoke.2319638982 Oct 08 01:24:42 PM PDT 23 Oct 08 01:24:48 PM PDT 23 2111285799 ps
T547 /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2622676947 Oct 08 01:24:55 PM PDT 23 Oct 08 01:25:01 PM PDT 23 2083589262 ps
T548 /workspace/coverage/default/22.sysrst_ctrl_stress_all.2128703107 Oct 08 01:35:43 PM PDT 23 Oct 08 01:35:52 PM PDT 23 6590353633 ps
T549 /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.757840079 Oct 08 01:24:03 PM PDT 23 Oct 08 01:24:11 PM PDT 23 2453434410 ps
T550 /workspace/coverage/default/29.sysrst_ctrl_smoke.3447408436 Oct 08 01:32:50 PM PDT 23 Oct 08 01:32:56 PM PDT 23 2112416794 ps
T327 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1270847735 Oct 08 01:36:03 PM PDT 23 Oct 08 01:37:11 PM PDT 23 101090967893 ps
T551 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.503564489 Oct 08 01:27:10 PM PDT 23 Oct 08 01:27:13 PM PDT 23 3625628522 ps
T200 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.3808208316 Oct 08 01:28:49 PM PDT 23 Oct 08 01:28:50 PM PDT 23 3080584247 ps
T224 /workspace/coverage/default/0.sysrst_ctrl_alert_test.4173173192 Oct 08 03:31:29 PM PDT 23 Oct 08 03:31:31 PM PDT 23 2039157620 ps
T225 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2150486574 Oct 08 01:26:06 PM PDT 23 Oct 08 01:26:13 PM PDT 23 2701451754 ps
T226 /workspace/coverage/default/27.sysrst_ctrl_smoke.364802550 Oct 08 01:22:14 PM PDT 23 Oct 08 01:22:18 PM PDT 23 2116258950 ps
T227 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.623325671 Oct 08 01:30:37 PM PDT 23 Oct 08 01:30:44 PM PDT 23 2174300187 ps
T228 /workspace/coverage/default/29.sysrst_ctrl_alert_test.339775739 Oct 08 01:34:02 PM PDT 23 Oct 08 01:34:08 PM PDT 23 2011787995 ps
T229 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.2723523306 Oct 08 01:29:49 PM PDT 23 Oct 08 01:29:51 PM PDT 23 3106410687 ps
T230 /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.4146242155 Oct 08 01:28:36 PM PDT 23 Oct 08 01:28:38 PM PDT 23 2631926441 ps
T67 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1077542606 Oct 08 01:22:30 PM PDT 23 Oct 08 01:22:52 PM PDT 23 31223755576 ps
T552 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1151934199 Oct 08 01:24:24 PM PDT 23 Oct 08 01:24:32 PM PDT 23 2477433973 ps
T553 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3510929605 Oct 08 01:25:21 PM PDT 23 Oct 08 01:25:25 PM PDT 23 2454566562 ps
T325 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1334104514 Oct 08 01:29:26 PM PDT 23 Oct 08 01:32:01 PM PDT 23 81375364377 ps
T96 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.1064644490 Oct 08 01:35:36 PM PDT 23 Oct 08 01:41:47 PM PDT 23 144623937535 ps
T554 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2323048534 Oct 08 01:30:44 PM PDT 23 Oct 08 01:30:48 PM PDT 23 2527615368 ps
T249 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3282424131 Oct 08 01:23:17 PM PDT 23 Oct 08 01:23:57 PM PDT 23 44547540530 ps
T250 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1118594724 Oct 08 01:23:57 PM PDT 23 Oct 08 01:28:40 PM PDT 23 109122159057 ps
T555 /workspace/coverage/default/26.sysrst_ctrl_smoke.2687290693 Oct 08 01:28:42 PM PDT 23 Oct 08 01:28:48 PM PDT 23 2114740350 ps
T556 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.664494948 Oct 08 01:25:26 PM PDT 23 Oct 08 01:26:11 PM PDT 23 63717478425 ps
T557 /workspace/coverage/default/37.sysrst_ctrl_alert_test.2158119214 Oct 08 01:23:23 PM PDT 23 Oct 08 01:23:26 PM PDT 23 2022021434 ps
T558 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3101526588 Oct 08 01:22:28 PM PDT 23 Oct 08 01:22:34 PM PDT 23 2086423689 ps
T559 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1834734969 Oct 08 01:29:40 PM PDT 23 Oct 08 01:30:07 PM PDT 23 75222986375 ps
T560 /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2160416734 Oct 08 01:22:42 PM PDT 23 Oct 08 01:22:45 PM PDT 23 2577681691 ps
T561 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.180833598 Oct 08 01:24:17 PM PDT 23 Oct 08 01:24:21 PM PDT 23 2520796870 ps
T562 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.537238005 Oct 08 01:24:50 PM PDT 23 Oct 08 01:26:01 PM PDT 23 27330436613 ps
T563 /workspace/coverage/default/21.sysrst_ctrl_alert_test.3724190581 Oct 08 01:24:42 PM PDT 23 Oct 08 01:24:43 PM PDT 23 2074054828 ps
T68 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1419845473 Oct 08 02:06:34 PM PDT 23 Oct 08 02:06:42 PM PDT 23 39771921396 ps
T564 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3146477300 Oct 08 01:52:14 PM PDT 23 Oct 08 01:52:16 PM PDT 23 2801399973 ps
T565 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.849934009 Oct 08 01:31:56 PM PDT 23 Oct 08 01:32:03 PM PDT 23 2509712205 ps
T566 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2780314149 Oct 08 01:47:25 PM PDT 23 Oct 08 01:47:28 PM PDT 23 2524733387 ps
T567 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.2745334418 Oct 08 01:27:21 PM PDT 23 Oct 08 01:27:25 PM PDT 23 2518595829 ps
T568 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.740686756 Oct 08 01:25:59 PM PDT 23 Oct 08 01:26:02 PM PDT 23 2257084626 ps
T569 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1519262436 Oct 08 01:30:38 PM PDT 23 Oct 08 01:30:42 PM PDT 23 2616062413 ps
T570 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.141383769 Oct 08 01:33:28 PM PDT 23 Oct 08 01:33:30 PM PDT 23 2202805098 ps
T305 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.398844981 Oct 08 01:25:20 PM PDT 23 Oct 08 01:27:48 PM PDT 23 120503333769 ps
T571 /workspace/coverage/default/18.sysrst_ctrl_alert_test.1804726370 Oct 08 01:22:13 PM PDT 23 Oct 08 01:22:17 PM PDT 23 2025151840 ps
T180 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2579643933 Oct 08 01:23:29 PM PDT 23 Oct 08 01:23:36 PM PDT 23 2911008276 ps
T572 /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3841066015 Oct 08 01:31:24 PM PDT 23 Oct 08 01:31:30 PM PDT 23 4199069511 ps
T573 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3173056494 Oct 08 01:26:54 PM PDT 23 Oct 08 01:27:02 PM PDT 23 2467107781 ps
T348 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.919899764 Oct 08 01:20:37 PM PDT 23 Oct 08 01:22:25 PM PDT 23 605794213385 ps
T300 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1817911650 Oct 08 01:26:49 PM PDT 23 Oct 08 01:27:12 PM PDT 23 76801544808 ps
T574 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3464001439 Oct 08 01:25:15 PM PDT 23 Oct 08 01:26:53 PM PDT 23 144534445678 ps
T575 /workspace/coverage/default/29.sysrst_ctrl_stress_all.261517738 Oct 08 01:25:53 PM PDT 23 Oct 08 01:26:03 PM PDT 23 13880375874 ps
T576 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1818171825 Oct 08 01:22:31 PM PDT 23 Oct 08 01:22:33 PM PDT 23 2266461814 ps
T176 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.361130625 Oct 08 01:29:34 PM PDT 23 Oct 08 01:29:42 PM PDT 23 6466284305 ps
T577 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1004334475 Oct 08 01:28:53 PM PDT 23 Oct 08 01:29:01 PM PDT 23 2512191147 ps
T578 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2957185856 Oct 08 01:23:15 PM PDT 23 Oct 08 01:23:24 PM PDT 23 2459877557 ps
T579 /workspace/coverage/default/17.sysrst_ctrl_alert_test.575546729 Oct 08 01:28:58 PM PDT 23 Oct 08 01:29:02 PM PDT 23 2047251126 ps
T580 /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.340909598 Oct 08 01:29:19 PM PDT 23 Oct 08 01:29:24 PM PDT 23 2612530880 ps
T581 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3030539517 Oct 08 01:26:17 PM PDT 23 Oct 08 01:26:23 PM PDT 23 3838105878 ps
T190 /workspace/coverage/default/7.sysrst_ctrl_stress_all.4263425069 Oct 08 01:21:06 PM PDT 23 Oct 08 01:21:41 PM PDT 23 13939751226 ps
T582 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1401722249 Oct 08 01:22:58 PM PDT 23 Oct 08 01:23:01 PM PDT 23 3011121229 ps
T346 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.660978404 Oct 08 01:30:06 PM PDT 23 Oct 08 01:36:40 PM PDT 23 1884787102176 ps
T153 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3044955094 Oct 08 01:23:06 PM PDT 23 Oct 08 01:23:11 PM PDT 23 4030102258 ps
T583 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3741690137 Oct 08 01:30:11 PM PDT 23 Oct 08 01:30:15 PM PDT 23 2614598564 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%