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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.31 96.35 100.00 96.15 98.68 99.44 94.29


Total test records in report: 916
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T584 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.182836140 Oct 08 01:30:45 PM PDT 23 Oct 08 01:31:25 PM PDT 23 61768272182 ps
T585 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1581940028 Oct 08 01:23:36 PM PDT 23 Oct 08 01:23:59 PM PDT 23 52635737292 ps
T586 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.892809810 Oct 08 01:22:41 PM PDT 23 Oct 08 01:22:56 PM PDT 23 23601868054 ps
T304 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3567222699 Oct 08 01:28:08 PM PDT 23 Oct 08 01:30:51 PM PDT 23 59763711856 ps
T587 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2121872215 Oct 08 01:34:29 PM PDT 23 Oct 08 01:34:32 PM PDT 23 3397584262 ps
T588 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3958746600 Oct 08 01:28:22 PM PDT 23 Oct 08 01:28:29 PM PDT 23 2612381444 ps
T589 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2910776100 Oct 08 01:38:37 PM PDT 23 Oct 08 01:38:45 PM PDT 23 3818402549 ps
T590 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4190446578 Oct 08 01:25:48 PM PDT 23 Oct 08 01:25:55 PM PDT 23 2612840393 ps
T591 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3888095265 Oct 08 01:23:26 PM PDT 23 Oct 08 01:23:33 PM PDT 23 2119745382 ps
T592 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1436536503 Oct 08 01:26:40 PM PDT 23 Oct 08 01:26:42 PM PDT 23 2550088382 ps
T593 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3809992543 Oct 08 12:40:36 PM PDT 23 Oct 08 12:40:38 PM PDT 23 2224626805 ps
T594 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1611505672 Oct 08 01:25:38 PM PDT 23 Oct 08 01:25:40 PM PDT 23 3510928149 ps
T595 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3274481241 Oct 08 01:25:21 PM PDT 23 Oct 08 01:25:39 PM PDT 23 24605411705 ps
T313 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3727655871 Oct 08 01:30:35 PM PDT 23 Oct 08 01:32:27 PM PDT 23 77829302859 ps
T596 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1689328208 Oct 08 12:41:33 PM PDT 23 Oct 08 12:41:40 PM PDT 23 2205082843 ps
T349 /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3161038615 Oct 08 01:26:10 PM PDT 23 Oct 08 01:29:24 PM PDT 23 1694195726981 ps
T173 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3427896244 Oct 08 01:20:06 PM PDT 23 Oct 08 01:20:59 PM PDT 23 39367581426 ps
T188 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.2852067030 Oct 08 01:28:56 PM PDT 23 Oct 08 01:29:05 PM PDT 23 3197837864 ps
T597 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2934480264 Oct 08 01:21:04 PM PDT 23 Oct 08 01:21:06 PM PDT 23 2076929526 ps
T598 /workspace/coverage/default/49.sysrst_ctrl_smoke.3355048454 Oct 08 01:26:29 PM PDT 23 Oct 08 01:26:31 PM PDT 23 2135950205 ps
T599 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.309799949 Oct 08 01:34:28 PM PDT 23 Oct 08 01:36:14 PM PDT 23 47250966677 ps
T126 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3303394979 Oct 08 01:27:00 PM PDT 23 Oct 08 01:27:34 PM PDT 23 88051427699 ps
T600 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2004633750 Oct 08 01:21:33 PM PDT 23 Oct 08 01:21:38 PM PDT 23 4528676202 ps
T334 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3128195255 Oct 08 01:30:53 PM PDT 23 Oct 08 01:31:46 PM PDT 23 87392905132 ps
T601 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2417889911 Oct 08 01:22:42 PM PDT 23 Oct 08 01:25:03 PM PDT 23 190886895303 ps
T602 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2864185352 Oct 08 01:24:30 PM PDT 23 Oct 08 01:24:36 PM PDT 23 3925622741 ps
T603 /workspace/coverage/default/20.sysrst_ctrl_alert_test.4139326807 Oct 08 01:24:15 PM PDT 23 Oct 08 01:24:17 PM PDT 23 2042385935 ps
T314 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3237809214 Oct 08 01:35:58 PM PDT 23 Oct 08 01:39:30 PM PDT 23 75543107654 ps
T604 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.74120269 Oct 08 01:31:05 PM PDT 23 Oct 08 01:31:09 PM PDT 23 4385595376 ps
T605 /workspace/coverage/default/36.sysrst_ctrl_stress_all.1230123627 Oct 08 01:30:51 PM PDT 23 Oct 08 01:30:58 PM PDT 23 8377299612 ps
T606 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1820080790 Oct 08 01:28:53 PM PDT 23 Oct 08 01:29:00 PM PDT 23 4817286265 ps
T607 /workspace/coverage/default/4.sysrst_ctrl_stress_all.1201469441 Oct 08 01:20:55 PM PDT 23 Oct 08 01:21:12 PM PDT 23 6619336530 ps
T174 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4254683174 Oct 08 01:26:53 PM PDT 23 Oct 08 01:27:51 PM PDT 23 22045521344 ps
T608 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.1038545106 Oct 08 01:23:42 PM PDT 23 Oct 08 01:23:46 PM PDT 23 3134583012 ps
T609 /workspace/coverage/default/9.sysrst_ctrl_alert_test.3609009962 Oct 08 01:20:31 PM PDT 23 Oct 08 01:20:33 PM PDT 23 2033405440 ps
T610 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1562206083 Oct 08 01:28:00 PM PDT 23 Oct 08 01:28:22 PM PDT 23 26350577514 ps
T161 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2881038403 Oct 08 01:25:04 PM PDT 23 Oct 08 01:25:22 PM PDT 23 810058281575 ps
T611 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.832338779 Oct 08 01:31:25 PM PDT 23 Oct 08 01:33:12 PM PDT 23 152866749207 ps
T328 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4269370030 Oct 08 01:24:27 PM PDT 23 Oct 08 01:25:04 PM PDT 23 53930343263 ps
T612 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1494763058 Oct 08 01:31:25 PM PDT 23 Oct 08 01:31:27 PM PDT 23 2468811884 ps
T613 /workspace/coverage/default/39.sysrst_ctrl_alert_test.737642305 Oct 08 01:40:45 PM PDT 23 Oct 08 01:40:47 PM PDT 23 2032209052 ps
T614 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.797507838 Oct 08 01:21:57 PM PDT 23 Oct 08 01:22:00 PM PDT 23 2522335373 ps
T298 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2796762540 Oct 08 01:31:28 PM PDT 23 Oct 08 01:32:54 PM PDT 23 132124859105 ps
T615 /workspace/coverage/default/19.sysrst_ctrl_stress_all.2242229585 Oct 08 01:21:32 PM PDT 23 Oct 08 01:21:53 PM PDT 23 7225566347 ps
T616 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1209212053 Oct 08 01:35:44 PM PDT 23 Oct 08 01:36:33 PM PDT 23 86957397414 ps
T617 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3297246962 Oct 08 01:27:05 PM PDT 23 Oct 08 01:27:14 PM PDT 23 3424469586 ps
T162 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.596264520 Oct 08 01:22:51 PM PDT 23 Oct 08 01:23:12 PM PDT 23 35475908942 ps
T618 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4198024295 Oct 08 01:28:19 PM PDT 23 Oct 08 01:30:47 PM PDT 23 60980489189 ps
T619 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.649915868 Oct 08 01:21:07 PM PDT 23 Oct 08 01:21:09 PM PDT 23 2185178067 ps
T201 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1129362240 Oct 08 01:22:20 PM PDT 23 Oct 08 01:23:19 PM PDT 23 81989466973 ps
T620 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.4160648987 Oct 08 01:24:15 PM PDT 23 Oct 08 01:25:25 PM PDT 23 26392855522 ps
T621 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.598618270 Oct 08 01:23:22 PM PDT 23 Oct 08 01:23:29 PM PDT 23 2218497225 ps
T622 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2210866078 Oct 08 01:31:57 PM PDT 23 Oct 08 01:31:59 PM PDT 23 2640943376 ps
T127 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.762798786 Oct 08 01:25:00 PM PDT 23 Oct 08 01:25:19 PM PDT 23 235787153178 ps
T623 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.455797411 Oct 08 01:42:30 PM PDT 23 Oct 08 01:42:48 PM PDT 23 26856161111 ps
T624 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.766976728 Oct 08 01:30:58 PM PDT 23 Oct 08 01:34:03 PM PDT 23 69165826487 ps
T625 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.767892766 Oct 08 01:23:12 PM PDT 23 Oct 08 01:23:19 PM PDT 23 2515112110 ps
T626 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3417212936 Oct 08 01:28:31 PM PDT 23 Oct 08 01:28:38 PM PDT 23 2127276303 ps
T627 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1926002042 Oct 08 01:31:27 PM PDT 23 Oct 08 01:31:30 PM PDT 23 2768635464 ps
T137 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2766318487 Oct 08 01:34:50 PM PDT 23 Oct 08 01:34:57 PM PDT 23 4554115266 ps
T628 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.2959990282 Oct 08 01:23:07 PM PDT 23 Oct 08 01:23:09 PM PDT 23 2537265519 ps
T629 /workspace/coverage/default/34.sysrst_ctrl_smoke.2536852426 Oct 08 01:23:57 PM PDT 23 Oct 08 01:23:59 PM PDT 23 2144210094 ps
T630 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1445930769 Oct 08 01:22:18 PM PDT 23 Oct 08 01:22:20 PM PDT 23 2724960416 ps
T163 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4090572650 Oct 08 01:26:05 PM PDT 23 Oct 08 01:27:07 PM PDT 23 49088938022 ps
T631 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1212120774 Oct 08 01:26:37 PM PDT 23 Oct 08 01:30:27 PM PDT 23 168509103457 ps
T632 /workspace/coverage/default/44.sysrst_ctrl_smoke.781555266 Oct 08 01:36:15 PM PDT 23 Oct 08 01:36:16 PM PDT 23 2199834837 ps
T633 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2859169287 Oct 08 01:20:55 PM PDT 23 Oct 08 01:21:02 PM PDT 23 2522225368 ps
T634 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1837771351 Oct 08 01:21:31 PM PDT 23 Oct 08 01:21:37 PM PDT 23 2080872252 ps
T342 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1937058817 Oct 08 01:26:04 PM PDT 23 Oct 08 01:26:30 PM PDT 23 111093305994 ps
T635 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3114160384 Oct 08 01:24:01 PM PDT 23 Oct 08 01:24:08 PM PDT 23 4383861454 ps
T636 /workspace/coverage/default/40.sysrst_ctrl_alert_test.2522842385 Oct 08 01:25:24 PM PDT 23 Oct 08 01:25:26 PM PDT 23 2036253751 ps
T637 /workspace/coverage/default/33.sysrst_ctrl_smoke.2148695648 Oct 08 01:25:01 PM PDT 23 Oct 08 01:25:03 PM PDT 23 2126706405 ps
T638 /workspace/coverage/default/16.sysrst_ctrl_smoke.2819410226 Oct 08 01:27:27 PM PDT 23 Oct 08 01:27:33 PM PDT 23 2110632923 ps
T639 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1672017146 Oct 08 01:30:35 PM PDT 23 Oct 08 01:30:38 PM PDT 23 2115160904 ps
T640 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2926464809 Oct 08 01:24:51 PM PDT 23 Oct 08 01:24:55 PM PDT 23 2521627959 ps
T641 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1109661694 Oct 08 01:30:00 PM PDT 23 Oct 08 01:30:01 PM PDT 23 2518471563 ps
T332 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2877447018 Oct 08 01:25:19 PM PDT 23 Oct 08 01:29:18 PM PDT 23 199645868028 ps
T642 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.649191226 Oct 08 01:22:15 PM PDT 23 Oct 08 01:22:22 PM PDT 23 2472288619 ps
T643 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3897876553 Oct 08 12:28:46 PM PDT 23 Oct 08 12:28:48 PM PDT 23 11449098142 ps
T644 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.135191643 Oct 08 01:25:59 PM PDT 23 Oct 08 01:26:11 PM PDT 23 4710361612 ps
T645 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2231665179 Oct 08 01:30:56 PM PDT 23 Oct 08 01:31:02 PM PDT 23 2153174043 ps
T646 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.4257395427 Oct 08 01:21:29 PM PDT 23 Oct 08 01:21:37 PM PDT 23 2466221213 ps
T647 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.375361956 Oct 08 01:24:15 PM PDT 23 Oct 08 01:24:18 PM PDT 23 3367038113 ps
T648 /workspace/coverage/default/1.sysrst_ctrl_alert_test.2470544269 Oct 08 01:20:09 PM PDT 23 Oct 08 01:20:14 PM PDT 23 2017163614 ps
T138 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2960576769 Oct 08 01:22:19 PM PDT 23 Oct 08 01:23:12 PM PDT 23 85571063987 ps
T196 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.66924684 Oct 08 01:25:11 PM PDT 23 Oct 08 01:25:21 PM PDT 23 5347169654 ps
T649 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2715942797 Oct 08 01:23:35 PM PDT 23 Oct 08 01:23:38 PM PDT 23 2536598207 ps
T650 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3879758159 Oct 08 01:24:06 PM PDT 23 Oct 08 01:24:14 PM PDT 23 2468935878 ps
T651 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1920348357 Oct 08 01:24:52 PM PDT 23 Oct 08 01:25:00 PM PDT 23 2607736973 ps
T208 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.589673611 Oct 08 01:24:09 PM PDT 23 Oct 08 01:24:17 PM PDT 23 3122317608 ps
T652 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1026544116 Oct 08 01:23:12 PM PDT 23 Oct 08 01:23:15 PM PDT 23 2632938822 ps
T653 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2851441663 Oct 08 01:22:10 PM PDT 23 Oct 08 01:22:12 PM PDT 23 2900530940 ps
T654 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3208138540 Oct 08 01:26:39 PM PDT 23 Oct 08 01:26:41 PM PDT 23 2432201526 ps
T655 /workspace/coverage/default/22.sysrst_ctrl_alert_test.1477854913 Oct 08 01:24:29 PM PDT 23 Oct 08 01:24:34 PM PDT 23 2012539740 ps
T213 /workspace/coverage/default/42.sysrst_ctrl_stress_all.1959154633 Oct 08 01:26:34 PM PDT 23 Oct 08 01:26:44 PM PDT 23 14077299157 ps
T656 /workspace/coverage/default/31.sysrst_ctrl_alert_test.1793697401 Oct 08 01:25:26 PM PDT 23 Oct 08 01:25:32 PM PDT 23 2015215010 ps
T73 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1798441164 Oct 08 01:33:50 PM PDT 23 Oct 08 01:34:10 PM PDT 23 27554428983 ps
T657 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3054177061 Oct 08 01:33:38 PM PDT 23 Oct 08 01:33:42 PM PDT 23 3561681525 ps
T658 /workspace/coverage/default/10.sysrst_ctrl_smoke.495815150 Oct 08 01:24:37 PM PDT 23 Oct 08 01:24:40 PM PDT 23 2119509623 ps
T252 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.105438858 Oct 08 01:19:38 PM PDT 23 Oct 08 01:20:03 PM PDT 23 42137612893 ps
T659 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.4290466879 Oct 08 01:25:50 PM PDT 23 Oct 08 01:25:57 PM PDT 23 2445105626 ps
T660 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1245139645 Oct 08 01:24:09 PM PDT 23 Oct 08 01:24:12 PM PDT 23 2482803410 ps
T661 /workspace/coverage/default/8.sysrst_ctrl_smoke.3391734624 Oct 08 01:20:39 PM PDT 23 Oct 08 01:20:43 PM PDT 23 2118760549 ps
T662 /workspace/coverage/default/25.sysrst_ctrl_stress_all.502289394 Oct 08 01:28:54 PM PDT 23 Oct 08 01:28:57 PM PDT 23 10007224679 ps
T663 /workspace/coverage/default/27.sysrst_ctrl_alert_test.2563767186 Oct 08 01:24:07 PM PDT 23 Oct 08 01:24:10 PM PDT 23 2018054666 ps
T664 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4113368724 Oct 08 01:30:52 PM PDT 23 Oct 08 01:30:54 PM PDT 23 7176560116 ps
T665 /workspace/coverage/default/43.sysrst_ctrl_smoke.2806187059 Oct 08 01:28:54 PM PDT 23 Oct 08 01:29:01 PM PDT 23 2112647436 ps
T666 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.13454018 Oct 08 01:34:04 PM PDT 23 Oct 08 01:39:15 PM PDT 23 190000256195 ps
T667 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1580191048 Oct 08 01:23:13 PM PDT 23 Oct 08 01:24:07 PM PDT 23 23081392452 ps
T333 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.2805577809 Oct 08 01:23:16 PM PDT 23 Oct 08 01:26:28 PM PDT 23 165973102655 ps
T668 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.355246377 Oct 08 01:23:10 PM PDT 23 Oct 08 01:23:17 PM PDT 23 2462041988 ps
T669 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1352100300 Oct 08 01:21:58 PM PDT 23 Oct 08 01:24:13 PM PDT 23 289931293952 ps
T231 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1819351618 Oct 08 01:31:18 PM PDT 23 Oct 08 01:31:21 PM PDT 23 5006014079 ps
T670 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1730556718 Oct 08 01:19:36 PM PDT 23 Oct 08 01:19:44 PM PDT 23 2611882947 ps
T671 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.61358706 Oct 08 01:30:14 PM PDT 23 Oct 08 01:30:52 PM PDT 23 25336340655 ps
T672 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1840394973 Oct 08 01:20:04 PM PDT 23 Oct 08 01:21:08 PM PDT 23 121778295196 ps
T673 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1413548315 Oct 08 01:32:25 PM PDT 23 Oct 08 01:33:27 PM PDT 23 25583988832 ps
T674 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2920953567 Oct 08 01:28:53 PM PDT 23 Oct 08 01:29:01 PM PDT 23 4394860447 ps
T301 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.976957201 Oct 08 01:21:14 PM PDT 23 Oct 08 01:22:30 PM PDT 23 171082417917 ps
T675 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.857319196 Oct 08 01:20:54 PM PDT 23 Oct 08 01:21:00 PM PDT 23 2616184720 ps
T676 /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.854537000 Oct 08 01:24:08 PM PDT 23 Oct 08 01:24:15 PM PDT 23 2458005521 ps
T74 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1322125471 Oct 08 01:24:37 PM PDT 23 Oct 08 01:25:56 PM PDT 23 55175574449 ps
T677 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1441602817 Oct 08 01:24:55 PM PDT 23 Oct 08 01:25:01 PM PDT 23 2080736174 ps
T678 /workspace/coverage/default/41.sysrst_ctrl_smoke.2368544661 Oct 08 01:42:39 PM PDT 23 Oct 08 01:42:42 PM PDT 23 2115227507 ps
T679 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2626830630 Oct 08 01:24:41 PM PDT 23 Oct 08 01:24:46 PM PDT 23 5810090889 ps
T680 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3661913846 Oct 08 01:22:48 PM PDT 23 Oct 08 01:22:49 PM PDT 23 2598085222 ps
T681 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2344188505 Oct 08 12:52:39 PM PDT 23 Oct 08 12:52:42 PM PDT 23 2256309653 ps
T326 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1602223343 Oct 08 01:21:32 PM PDT 23 Oct 08 01:27:54 PM PDT 23 156205591810 ps
T682 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1089482189 Oct 08 01:25:01 PM PDT 23 Oct 08 01:31:52 PM PDT 23 160766203694 ps
T683 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.799824962 Oct 08 01:30:49 PM PDT 23 Oct 08 01:30:54 PM PDT 23 2514665822 ps
T684 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3745608413 Oct 08 01:26:19 PM PDT 23 Oct 08 01:26:21 PM PDT 23 2653150893 ps
T685 /workspace/coverage/default/5.sysrst_ctrl_alert_test.2491297596 Oct 08 01:32:37 PM PDT 23 Oct 08 01:32:40 PM PDT 23 2029124703 ps
T686 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3394998188 Oct 08 01:28:29 PM PDT 23 Oct 08 01:28:36 PM PDT 23 4316224798 ps
T687 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1288573885 Oct 08 01:41:42 PM PDT 23 Oct 08 01:41:47 PM PDT 23 2174551719 ps
T688 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2333895102 Oct 08 01:23:58 PM PDT 23 Oct 08 01:24:03 PM PDT 23 3356628861 ps
T689 /workspace/coverage/default/40.sysrst_ctrl_smoke.4082900350 Oct 08 01:33:08 PM PDT 23 Oct 08 01:33:14 PM PDT 23 2112038550 ps
T690 /workspace/coverage/default/17.sysrst_ctrl_smoke.2498450082 Oct 08 01:21:13 PM PDT 23 Oct 08 01:21:14 PM PDT 23 2239981696 ps
T195 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.703371917 Oct 08 01:24:54 PM PDT 23 Oct 08 01:24:55 PM PDT 23 2749216248 ps
T209 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.846148712 Oct 08 01:24:00 PM PDT 23 Oct 08 01:26:02 PM PDT 23 601543432002 ps
T691 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.241323925 Oct 08 01:23:01 PM PDT 23 Oct 08 01:23:05 PM PDT 23 2522517018 ps
T692 /workspace/coverage/default/48.sysrst_ctrl_smoke.3954366911 Oct 08 01:30:30 PM PDT 23 Oct 08 01:30:32 PM PDT 23 2138422323 ps
T693 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2614633727 Oct 08 01:25:06 PM PDT 23 Oct 08 01:25:08 PM PDT 23 2079328764 ps
T243 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.2569912513 Oct 08 01:32:54 PM PDT 23 Oct 08 01:34:34 PM PDT 23 37683078687 ps
T694 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1212752456 Oct 08 01:33:49 PM PDT 23 Oct 08 01:33:53 PM PDT 23 2473774741 ps
T695 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2697442764 Oct 08 01:32:55 PM PDT 23 Oct 08 01:32:59 PM PDT 23 3412781896 ps
T696 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1278945988 Oct 08 01:28:30 PM PDT 23 Oct 08 01:28:42 PM PDT 23 4024558773 ps
T697 /workspace/coverage/default/15.sysrst_ctrl_smoke.2906771948 Oct 08 01:36:53 PM PDT 23 Oct 08 01:36:56 PM PDT 23 2136763007 ps
T259 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2145497887 Oct 08 01:19:46 PM PDT 23 Oct 08 01:20:41 PM PDT 23 22011277909 ps
T698 /workspace/coverage/default/46.sysrst_ctrl_stress_all.2499944565 Oct 08 01:29:49 PM PDT 23 Oct 08 01:29:56 PM PDT 23 8768824908 ps
T699 /workspace/coverage/default/16.sysrst_ctrl_alert_test.800226501 Oct 08 01:21:38 PM PDT 23 Oct 08 01:21:40 PM PDT 23 2029154998 ps
T700 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.907012583 Oct 08 01:20:39 PM PDT 23 Oct 08 01:20:44 PM PDT 23 3486099943 ps
T701 /workspace/coverage/default/8.sysrst_ctrl_stress_all.2791261737 Oct 08 01:25:01 PM PDT 23 Oct 08 01:25:30 PM PDT 23 12349183029 ps
T241 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3289085006 Oct 08 01:28:45 PM PDT 23 Oct 08 01:29:17 PM PDT 23 72021576078 ps
T350 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4262614747 Oct 08 01:38:52 PM PDT 23 Oct 08 01:40:00 PM PDT 23 66793466935 ps
T702 /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1965964580 Oct 08 01:24:00 PM PDT 23 Oct 08 01:24:04 PM PDT 23 2457920468 ps
T703 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2721420469 Oct 08 01:21:24 PM PDT 23 Oct 08 01:21:28 PM PDT 23 3016898850 ps
T704 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3767681270 Oct 08 01:19:40 PM PDT 23 Oct 08 01:19:42 PM PDT 23 2474349178 ps
T244 /workspace/coverage/default/39.sysrst_ctrl_stress_all.1365594707 Oct 08 01:27:27 PM PDT 23 Oct 08 01:29:51 PM PDT 23 564358976856 ps
T79 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3672923306 Oct 08 01:27:05 PM PDT 23 Oct 08 01:27:08 PM PDT 23 7673397935 ps
T705 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3308051653 Oct 08 01:28:57 PM PDT 23 Oct 08 01:28:59 PM PDT 23 2535650460 ps
T339 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.708195409 Oct 08 01:24:36 PM PDT 23 Oct 08 01:26:14 PM PDT 23 70766539114 ps
T706 /workspace/coverage/default/3.sysrst_ctrl_stress_all.53719832 Oct 08 01:20:17 PM PDT 23 Oct 08 01:20:36 PM PDT 23 13906926452 ps
T707 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3940327260 Oct 08 01:20:58 PM PDT 23 Oct 08 01:21:00 PM PDT 23 2246833966 ps
T164 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3123963341 Oct 08 01:30:21 PM PDT 23 Oct 08 01:30:23 PM PDT 23 5626303756 ps
T708 /workspace/coverage/default/38.sysrst_ctrl_smoke.4041357815 Oct 08 01:32:52 PM PDT 23 Oct 08 01:32:59 PM PDT 23 2113382034 ps
T709 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1106676632 Oct 08 01:21:39 PM PDT 23 Oct 08 01:21:42 PM PDT 23 2521264824 ps
T223 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.322488360 Oct 08 01:29:41 PM PDT 23 Oct 08 01:29:47 PM PDT 23 4707269764 ps
T710 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1110875791 Oct 08 01:22:06 PM PDT 23 Oct 08 01:22:09 PM PDT 23 2637826728 ps
T711 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3313235312 Oct 08 01:20:40 PM PDT 23 Oct 08 01:21:01 PM PDT 23 79989323365 ps
T712 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2829619650 Oct 08 01:25:08 PM PDT 23 Oct 08 01:25:11 PM PDT 23 2459254826 ps
T344 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1704014352 Oct 08 01:24:47 PM PDT 23 Oct 08 01:26:27 PM PDT 23 39115745774 ps
T713 /workspace/coverage/default/21.sysrst_ctrl_smoke.1075477388 Oct 08 01:21:43 PM PDT 23 Oct 08 01:21:45 PM PDT 23 2138631669 ps
T97 /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3380307084 Oct 08 01:24:28 PM PDT 23 Oct 08 01:28:32 PM PDT 23 95689324490 ps
T714 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3220336297 Oct 08 01:21:22 PM PDT 23 Oct 08 01:21:24 PM PDT 23 2498762716 ps
T715 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.4262556977 Oct 08 01:42:10 PM PDT 23 Oct 08 01:42:16 PM PDT 23 2174226640 ps
T139 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2535687890 Oct 08 01:28:02 PM PDT 23 Oct 08 01:31:51 PM PDT 23 2793723885572 ps
T98 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3753242740 Oct 08 01:21:50 PM PDT 23 Oct 08 01:29:42 PM PDT 23 185237314462 ps
T716 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1994240134 Oct 08 01:21:00 PM PDT 23 Oct 08 01:21:02 PM PDT 23 3058895325 ps
T717 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.35028577 Oct 08 01:26:02 PM PDT 23 Oct 08 01:26:21 PM PDT 23 25595137255 ps
T718 /workspace/coverage/default/20.sysrst_ctrl_smoke.3531456123 Oct 08 01:22:32 PM PDT 23 Oct 08 01:22:36 PM PDT 23 2115014073 ps
T99 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1888737146 Oct 08 01:22:07 PM PDT 23 Oct 08 01:23:00 PM PDT 23 139456977024 ps
T323 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1517986266 Oct 08 01:24:14 PM PDT 23 Oct 08 01:24:35 PM PDT 23 83187590662 ps
T719 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1077334875 Oct 08 01:22:01 PM PDT 23 Oct 08 01:22:09 PM PDT 23 2963433064 ps
T720 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3468228675 Oct 08 01:27:14 PM PDT 23 Oct 08 01:27:20 PM PDT 23 2049564290 ps
T210 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3537556308 Oct 08 01:24:25 PM PDT 23 Oct 08 01:24:30 PM PDT 23 4413138608 ps
T721 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1931838469 Oct 08 01:21:02 PM PDT 23 Oct 08 01:21:06 PM PDT 23 3826360011 ps
T722 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3137745865 Oct 08 01:24:44 PM PDT 23 Oct 08 01:25:29 PM PDT 23 40501498275 ps
T341 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2312141945 Oct 08 01:33:35 PM PDT 23 Oct 08 01:33:50 PM PDT 23 22855765110 ps
T723 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4017649229 Oct 08 01:26:07 PM PDT 23 Oct 08 01:26:09 PM PDT 23 3408453732 ps
T724 /workspace/coverage/default/13.sysrst_ctrl_smoke.380508595 Oct 08 01:25:09 PM PDT 23 Oct 08 01:25:10 PM PDT 23 2210147378 ps
T306 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.2582753413 Oct 08 01:23:54 PM PDT 23 Oct 08 01:24:56 PM PDT 23 98145888398 ps
T725 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.581534272 Oct 08 01:30:03 PM PDT 23 Oct 08 01:30:07 PM PDT 23 2522731798 ps
T726 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3265854576 Oct 08 01:22:48 PM PDT 23 Oct 08 01:22:51 PM PDT 23 2627695405 ps
T727 /workspace/coverage/default/47.sysrst_ctrl_smoke.3347165659 Oct 08 01:32:47 PM PDT 23 Oct 08 01:32:53 PM PDT 23 2110481934 ps
T179 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4282132590 Oct 08 01:29:04 PM PDT 23 Oct 08 01:29:31 PM PDT 23 40712279730 ps
T186 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.4113528922 Oct 08 01:27:25 PM PDT 23 Oct 08 01:29:11 PM PDT 23 83993270845 ps
T345 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.598204555 Oct 08 01:19:39 PM PDT 23 Oct 08 01:19:48 PM PDT 23 28625597448 ps
T728 /workspace/coverage/default/4.sysrst_ctrl_alert_test.418168040 Oct 08 01:22:31 PM PDT 23 Oct 08 01:22:35 PM PDT 23 2018086285 ps
T729 /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1675717681 Oct 08 01:30:36 PM PDT 23 Oct 08 01:30:41 PM PDT 23 2451967122 ps
T730 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.668442024 Oct 08 01:22:30 PM PDT 23 Oct 08 01:22:33 PM PDT 23 2048487008 ps
T731 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.366968157 Oct 08 01:26:20 PM PDT 23 Oct 08 01:27:02 PM PDT 23 33202120414 ps
T732 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1941459047 Oct 08 01:22:01 PM PDT 23 Oct 08 01:24:56 PM PDT 23 64080673512 ps
T733 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3023351901 Oct 08 01:24:08 PM PDT 23 Oct 08 01:24:16 PM PDT 23 5919487340 ps
T734 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3791094494 Oct 08 01:21:38 PM PDT 23 Oct 08 01:21:39 PM PDT 23 2497822622 ps
T735 /workspace/coverage/default/11.sysrst_ctrl_smoke.2368681118 Oct 08 01:21:56 PM PDT 23 Oct 08 01:21:58 PM PDT 23 2125553474 ps
T736 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1746191427 Oct 08 01:25:30 PM PDT 23 Oct 08 01:25:57 PM PDT 23 40724375570 ps
T737 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3928623930 Oct 08 01:27:32 PM PDT 23 Oct 08 01:27:40 PM PDT 23 2463711536 ps
T347 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.648804300 Oct 08 01:30:10 PM PDT 23 Oct 08 01:30:59 PM PDT 23 35612913935 ps
T738 /workspace/coverage/default/23.sysrst_ctrl_smoke.2917049768 Oct 08 01:23:44 PM PDT 23 Oct 08 01:23:46 PM PDT 23 2133664885 ps
T739 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3461530909 Oct 08 01:23:01 PM PDT 23 Oct 08 01:23:03 PM PDT 23 4647201765 ps
T740 /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2577621291 Oct 08 01:22:13 PM PDT 23 Oct 08 01:22:19 PM PDT 23 2443788085 ps
T245 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.551527256 Oct 08 01:22:15 PM PDT 23 Oct 08 01:23:20 PM PDT 23 174506275321 ps
T741 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3097878708 Oct 08 01:23:20 PM PDT 23 Oct 08 01:23:24 PM PDT 23 2703446298 ps
T742 /workspace/coverage/default/14.sysrst_ctrl_stress_all.1149787354 Oct 08 01:21:28 PM PDT 23 Oct 08 01:21:36 PM PDT 23 12177892653 ps
T743 /workspace/coverage/default/6.sysrst_ctrl_alert_test.988893417 Oct 08 01:20:57 PM PDT 23 Oct 08 01:21:02 PM PDT 23 2013286829 ps
T744 /workspace/coverage/default/23.sysrst_ctrl_alert_test.1961454358 Oct 08 01:23:10 PM PDT 23 Oct 08 01:23:16 PM PDT 23 2012451455 ps
T745 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2334976738 Oct 08 01:21:02 PM PDT 23 Oct 08 01:24:39 PM PDT 23 165347145033 ps
T337 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1077239206 Oct 08 01:23:52 PM PDT 23 Oct 08 01:24:33 PM PDT 23 533991302348 ps
T340 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4246517279 Oct 08 01:28:28 PM PDT 23 Oct 08 01:29:30 PM PDT 23 49030512864 ps
T746 /workspace/coverage/default/10.sysrst_ctrl_stress_all.900155106 Oct 08 01:22:34 PM PDT 23 Oct 08 01:22:56 PM PDT 23 8951214350 ps
T747 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.366775513 Oct 08 01:32:33 PM PDT 23 Oct 08 01:35:41 PM PDT 23 65183269595 ps
T748 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4199619986 Oct 08 01:23:26 PM PDT 23 Oct 08 01:28:24 PM PDT 23 107083312030 ps
T749 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.4172032313 Oct 08 01:24:55 PM PDT 23 Oct 08 01:24:58 PM PDT 23 2470697134 ps
T750 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1624850698 Oct 08 01:33:51 PM PDT 23 Oct 08 01:33:57 PM PDT 23 4067230825 ps
T751 /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3093644520 Oct 08 01:22:43 PM PDT 23 Oct 08 01:22:45 PM PDT 23 2095304921 ps
T752 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2182971733 Oct 08 01:25:30 PM PDT 23 Oct 08 01:25:56 PM PDT 23 30851265028 ps
T315 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3307764376 Oct 08 01:28:20 PM PDT 23 Oct 08 01:30:10 PM PDT 23 42541874403 ps
T753 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3866945827 Oct 08 01:27:21 PM PDT 23 Oct 08 01:27:49 PM PDT 23 774669156750 ps
T754 /workspace/coverage/default/33.sysrst_ctrl_stress_all.570652857 Oct 08 01:26:16 PM PDT 23 Oct 08 01:26:34 PM PDT 23 12696660356 ps
T755 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.638285091 Oct 08 01:21:38 PM PDT 23 Oct 08 01:21:44 PM PDT 23 4381698665 ps
T756 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4151754391 Oct 08 01:20:31 PM PDT 23 Oct 08 01:20:33 PM PDT 23 10119044141 ps
T757 /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.572878067 Oct 08 01:21:11 PM PDT 23 Oct 08 01:21:15 PM PDT 23 2618227284 ps
T758 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3180338274 Oct 08 01:26:48 PM PDT 23 Oct 08 01:26:56 PM PDT 23 2990686805 ps
T759 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.779300903 Oct 08 01:27:42 PM PDT 23 Oct 08 01:27:45 PM PDT 23 2487258165 ps
T760 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3938709435 Oct 08 01:25:20 PM PDT 23 Oct 08 01:25:23 PM PDT 23 2145810844 ps
T761 /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1893559571 Oct 08 01:22:30 PM PDT 23 Oct 08 01:22:39 PM PDT 23 2510641300 ps
T762 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3442866213 Oct 08 01:41:50 PM PDT 23 Oct 08 01:41:59 PM PDT 23 3016361204 ps
T154 /workspace/coverage/default/31.sysrst_ctrl_stress_all.2397078005 Oct 08 01:22:47 PM PDT 23 Oct 08 01:23:20 PM PDT 23 13250577690 ps
T763 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.146357414 Oct 08 01:21:33 PM PDT 23 Oct 08 01:21:42 PM PDT 23 2610476678 ps
T307 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.925517196 Oct 08 01:37:11 PM PDT 23 Oct 08 01:39:42 PM PDT 23 56747062082 ps
T764 /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2858708289 Oct 08 01:22:20 PM PDT 23 Oct 08 01:22:23 PM PDT 23 2043494648 ps
T765 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3133875791 Oct 08 01:24:08 PM PDT 23 Oct 08 01:24:13 PM PDT 23 2085270568 ps
T766 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3997896203 Oct 08 01:34:27 PM PDT 23 Oct 08 01:34:35 PM PDT 23 2442197218 ps
T767 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1935483198 Oct 08 02:25:04 PM PDT 23 Oct 08 02:25:07 PM PDT 23 2627908898 ps
T768 /workspace/coverage/default/2.sysrst_ctrl_smoke.2397383589 Oct 08 01:19:30 PM PDT 23 Oct 08 01:19:32 PM PDT 23 2124885150 ps
T198 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.909155351 Oct 08 01:28:23 PM PDT 23 Oct 08 01:29:18 PM PDT 23 51761457522 ps
T769 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.34340085 Oct 08 01:26:45 PM PDT 23 Oct 08 01:27:41 PM PDT 23 128599530762 ps
T770 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3766336766 Oct 08 01:23:46 PM PDT 23 Oct 08 01:25:25 PM PDT 23 73834551010 ps
T177 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1812813791 Oct 08 01:30:19 PM PDT 23 Oct 08 01:30:27 PM PDT 23 5944213804 ps
T771 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.457788 Oct 08 01:28:26 PM PDT 23 Oct 08 01:30:49 PM PDT 23 50796032739 ps
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