SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_pin_in_value_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst_l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_flash_wp_l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_lid_open | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1406 | 1 | T70 | 29 | T71 | 10 | T21 | 27 | ||||
auto[1] | 1370 | 1 | T70 | 14 | T71 | 4 | T21 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1381 | 1 | T70 | 18 | T71 | 7 | T21 | 21 | ||||
auto[1] | 1395 | 1 | T70 | 25 | T71 | 7 | T21 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1410 | 1 | T70 | 23 | T71 | 7 | T21 | 28 | ||||
auto[1] | 1366 | 1 | T70 | 20 | T71 | 7 | T21 | 23 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1402 | 1 | T70 | 28 | T71 | 6 | T21 | 25 | ||||
auto[1] | 1374 | 1 | T70 | 15 | T71 | 8 | T21 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1369 | 1 | T70 | 15 | T71 | 8 | T21 | 27 | ||||
auto[1] | 1407 | 1 | T70 | 28 | T71 | 6 | T21 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1416 | 1 | T70 | 22 | T71 | 8 | T21 | 19 | ||||
auto[1] | 1360 | 1 | T70 | 21 | T71 | 6 | T21 | 32 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1409 | 1 | T70 | 25 | T71 | 9 | T21 | 28 | ||||
auto[1] | 1367 | 1 | T70 | 18 | T71 | 5 | T21 | 23 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1369 | 1 | T70 | 23 | T71 | 10 | T21 | 20 | ||||
auto[1] | 1407 | 1 | T70 | 20 | T71 | 4 | T21 | 31 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |