Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_key0_out_sel
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T45 |
3 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_key0_out_value
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T45 |
3 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
2 |
1 |
|
|
T45 |
2 |
auto[1] |
1 |
1 |
|
|
T45 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
2 |
1 |
|
|
T45 |
2 |
auto[1] |
1 |
1 |
|
|
T45 |
1 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
3 |
1 |
25.00 |
3 |
Automatically Generated Cross Bins for cross_key0_out_sel_value
Element holes
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Uncovered bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
auto[0] |
3 |
1 |
|
|
T45 |
3 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cross_key1_out_sel_value
Uncovered bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
[auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
auto[1] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
auto[0] |
2 |
1 |
|
|
T45 |
2 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cross_key2_out_sel_value
Uncovered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
[auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
auto[1] |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_key0_out_value
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T45 |
3 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_key1_out_value
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T45 |
3 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cross_key0_out_sel_value
Element holes
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Covered bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[0] |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cross_key1_out_sel_value
Element holes
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Covered bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[0] |
auto[1] |
2 |
1 |
|
|
T45 |
2 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cross_key2_out_sel_value
Uncovered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT |
auto[0] |
auto[1] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
auto[0] |
1 |
1 |
|
|
T45 |
1 |
auto[1] |
auto[1] |
1 |
1 |
|
|
T45 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
113 |
1 |
|
|
T29 |
2 |
|
T79 |
2 |
|
T21 |
1 |
auto[1] |
131 |
1 |
|
|
T29 |
1 |
|
T90 |
3 |
|
T79 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
119 |
1 |
|
|
T29 |
2 |
|
T90 |
2 |
|
T79 |
2 |
auto[1] |
125 |
1 |
|
|
T29 |
1 |
|
T90 |
1 |
|
T79 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
123 |
1 |
|
|
T29 |
2 |
|
T79 |
1 |
|
T101 |
2 |
auto[1] |
121 |
1 |
|
|
T29 |
1 |
|
T90 |
3 |
|
T79 |
2 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
127 |
1 |
|
|
T29 |
2 |
|
T90 |
1 |
|
T79 |
2 |
auto[1] |
117 |
1 |
|
|
T29 |
1 |
|
T90 |
2 |
|
T79 |
1 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
121 |
1 |
|
|
T29 |
2 |
|
T90 |
2 |
|
T101 |
3 |
auto[1] |
123 |
1 |
|
|
T29 |
1 |
|
T90 |
1 |
|
T79 |
3 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
123 |
1 |
|
|
T29 |
3 |
|
T90 |
2 |
|
T79 |
2 |
auto[1] |
121 |
1 |
|
|
T90 |
1 |
|
T79 |
1 |
|
T101 |
3 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46 |
1 |
|
|
T29 |
2 |
|
T79 |
1 |
|
T21 |
1 |
auto[0] |
auto[1] |
73 |
1 |
|
|
T90 |
2 |
|
T79 |
1 |
|
T101 |
1 |
auto[1] |
auto[0] |
67 |
1 |
|
|
T79 |
1 |
|
T101 |
1 |
|
T99 |
2 |
auto[1] |
auto[1] |
58 |
1 |
|
|
T29 |
1 |
|
T90 |
1 |
|
T101 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
64 |
1 |
|
|
T29 |
1 |
|
T79 |
1 |
|
T101 |
1 |
auto[0] |
auto[1] |
63 |
1 |
|
|
T29 |
1 |
|
T90 |
1 |
|
T79 |
1 |
auto[1] |
auto[0] |
59 |
1 |
|
|
T29 |
1 |
|
T101 |
1 |
|
T372 |
2 |
auto[1] |
auto[1] |
58 |
1 |
|
|
T90 |
2 |
|
T79 |
1 |
|
T99 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
61 |
1 |
|
|
T29 |
2 |
|
T90 |
2 |
|
T99 |
1 |
auto[0] |
auto[1] |
62 |
1 |
|
|
T29 |
1 |
|
T79 |
2 |
|
T21 |
1 |
auto[1] |
auto[0] |
60 |
1 |
|
|
T101 |
3 |
|
T99 |
1 |
|
T372 |
2 |
auto[1] |
auto[1] |
61 |
1 |
|
|
T90 |
1 |
|
T79 |
1 |
|
T99 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
17 |
1 |
|
|
T45 |
2 |
|
T63 |
2 |
|
T373 |
2 |
auto[1] |
9 |
1 |
|
|
T45 |
1 |
|
T63 |
1 |
|
T373 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T166 |
1 |
|
T117 |
1 |
|
T89 |
2 |
auto[1] |
18 |
1 |
|
|
T45 |
3 |
|
T63 |
3 |
|
T373 |
3 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16 |
1 |
|
|
T45 |
2 |
|
T63 |
2 |
|
T373 |
2 |
auto[1] |
10 |
1 |
|
|
T45 |
1 |
|
T63 |
1 |
|
T373 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T45 |
3 |
|
T63 |
2 |
|
T373 |
3 |
auto[1] |
6 |
1 |
|
|
T63 |
1 |
|
T166 |
1 |
|
T117 |
1 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12 |
1 |
|
|
T45 |
1 |
|
T63 |
2 |
|
T373 |
1 |
auto[1] |
14 |
1 |
|
|
T45 |
2 |
|
T63 |
1 |
|
T373 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16 |
1 |
|
|
T45 |
2 |
|
T63 |
3 |
|
T373 |
1 |
auto[1] |
10 |
1 |
|
|
T45 |
1 |
|
T373 |
2 |
|
T166 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
6 |
1 |
|
|
T166 |
1 |
|
T117 |
1 |
|
T89 |
1 |
auto[0] |
auto[1] |
2 |
1 |
|
|
T89 |
1 |
|
T239 |
1 |
|
- |
- |
auto[1] |
auto[0] |
11 |
1 |
|
|
T45 |
2 |
|
T63 |
2 |
|
T373 |
2 |
auto[1] |
auto[1] |
7 |
1 |
|
|
T45 |
1 |
|
T63 |
1 |
|
T373 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
13 |
1 |
|
|
T45 |
2 |
|
T63 |
1 |
|
T373 |
2 |
auto[0] |
auto[1] |
7 |
1 |
|
|
T45 |
1 |
|
T63 |
1 |
|
T373 |
1 |
auto[1] |
auto[0] |
3 |
1 |
|
|
T63 |
1 |
|
T166 |
1 |
|
T89 |
1 |
auto[1] |
auto[1] |
3 |
1 |
|
|
T117 |
1 |
|
T89 |
1 |
|
T239 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
7 |
1 |
|
|
T45 |
1 |
|
T63 |
2 |
|
T94 |
1 |
auto[0] |
auto[1] |
9 |
1 |
|
|
T45 |
1 |
|
T63 |
1 |
|
T373 |
1 |
auto[1] |
auto[0] |
5 |
1 |
|
|
T373 |
1 |
|
T166 |
1 |
|
T117 |
1 |
auto[1] |
auto[1] |
5 |
1 |
|
|
T45 |
1 |
|
T373 |
1 |
|
T166 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6 |
1 |
|
|
T45 |
1 |
|
T206 |
2 |
|
T166 |
1 |
auto[1] |
6 |
1 |
|
|
T45 |
2 |
|
T206 |
1 |
|
T166 |
2 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T45 |
2 |
|
T206 |
2 |
|
T166 |
1 |
auto[1] |
4 |
1 |
|
|
T45 |
1 |
|
T206 |
1 |
|
T166 |
2 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T45 |
2 |
|
T206 |
2 |
|
T166 |
2 |
auto[1] |
4 |
1 |
|
|
T45 |
1 |
|
T206 |
1 |
|
T166 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T45 |
2 |
|
T206 |
3 |
|
T166 |
2 |
auto[1] |
4 |
1 |
|
|
T45 |
1 |
|
T166 |
1 |
|
T94 |
2 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6 |
1 |
|
|
T45 |
2 |
|
T206 |
2 |
|
T94 |
2 |
auto[1] |
6 |
1 |
|
|
T45 |
1 |
|
T206 |
1 |
|
T166 |
3 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7 |
1 |
|
|
T45 |
2 |
|
T206 |
1 |
|
T166 |
1 |
auto[1] |
5 |
1 |
|
|
T45 |
1 |
|
T206 |
2 |
|
T166 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
5 |
1 |
|
|
T45 |
1 |
|
T206 |
2 |
|
T94 |
2 |
auto[0] |
auto[1] |
3 |
1 |
|
|
T45 |
1 |
|
T166 |
1 |
|
T94 |
1 |
auto[1] |
auto[0] |
1 |
1 |
|
|
T166 |
1 |
|
- |
- |
|
- |
- |
auto[1] |
auto[1] |
3 |
1 |
|
|
T45 |
1 |
|
T206 |
1 |
|
T166 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
7 |
1 |
|
|
T45 |
2 |
|
T206 |
2 |
|
T166 |
2 |
auto[0] |
auto[1] |
1 |
1 |
|
|
T206 |
1 |
|
- |
- |
|
- |
- |
auto[1] |
auto[0] |
1 |
1 |
|
|
T94 |
1 |
|
- |
- |
|
- |
- |
auto[1] |
auto[1] |
3 |
1 |
|
|
T45 |
1 |
|
T166 |
1 |
|
T94 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
4 |
1 |
|
|
T45 |
1 |
|
T206 |
1 |
|
T94 |
2 |
auto[0] |
auto[1] |
3 |
1 |
|
|
T45 |
1 |
|
T166 |
1 |
|
T94 |
1 |
auto[1] |
auto[0] |
2 |
1 |
|
|
T45 |
1 |
|
T206 |
1 |
|
- |
- |
auto[1] |
auto[1] |
3 |
1 |
|
|
T206 |
1 |
|
T166 |
2 |
|
- |
- |