SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_combo_detect_action_cg_0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 408 | 1 | T40 | 5 | T15 | 4 | T16 | 9 | ||||
auto[1] | 195 | 1 | T32 | 4 | T19 | 5 | T45 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 264 | 1 | T40 | 5 | T32 | 4 | T16 | 1 | ||||
auto[1] | 339 | 1 | T15 | 4 | T16 | 8 | T19 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 280 | 1 | T40 | 5 | T15 | 4 | T32 | 4 | ||||
auto[1] | 323 | 1 | T16 | 9 | T19 | 6 | T61 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 282 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 321 | 1 | T15 | 4 | T16 | 1 | T19 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 509 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 94 | 1 | T15 | 4 | T45 | 3 | T102 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 449 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 154 | 1 | T15 | 4 | T48 | 15 | T102 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 465 | 1 | T40 | 5 | T15 | 4 | T32 | 4 | ||||
auto[1] | 138 | 1 | T45 | 3 | T46 | 5 | T48 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 545 | 1 | T15 | 4 | T32 | 4 | T16 | 9 | ||||
auto[1] | 58 | 1 | T40 | 5 | T354 | 2 | T248 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 532 | 1 | T40 | 5 | T15 | 4 | T32 | 4 | ||||
auto[1] | 71 | 1 | T46 | 5 | T276 | 2 | T354 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 557 | 1 | T40 | 5 | T15 | 4 | T16 | 9 | ||||
auto[1] | 46 | 1 | T32 | 4 | T46 | 5 | T276 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 548 | 1 | T40 | 5 | T15 | 4 | T32 | 4 | ||||
auto[1] | 55 | 1 | T19 | 5 | T333 | 12 | T86 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 571 | 1 | T40 | 5 | T15 | 4 | T16 | 9 | ||||
auto[1] | 32 | 1 | T32 | 4 | T102 | 6 | T135 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 414 | 1 | T15 | 4 | T32 | 4 | T16 | 9 | ||||
auto[1] | 189 | 1 | T40 | 5 | T19 | 5 | T45 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 356 | 1 | T32 | 4 | T16 | 9 | T19 | 6 | ||||
auto[1] | 247 | 1 | T40 | 5 | T15 | 4 | T61 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 394 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 141 | 1 | T45 | 2 | T46 | 3 | T48 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 247 | 1 | T40 | 5 | T32 | 4 | T16 | 1 | ||||
auto[1] | 288 | 1 | T16 | 8 | T62 | 5 | T19 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 237 | 1 | T40 | 5 | T32 | 4 | T45 | 2 | ||||
auto[1] | 298 | 1 | T16 | 9 | T62 | 5 | T19 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 283 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 252 | 1 | T16 | 1 | T19 | 3 | T46 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 424 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 111 | 1 | T45 | 2 | T48 | 3 | T65 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 402 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 133 | 1 | T16 | 1 | T45 | 2 | T48 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 432 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 103 | 1 | T62 | 5 | T45 | 2 | T47 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 504 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 31 | 1 | T16 | 1 | T331 | 6 | T333 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 488 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 47 | 1 | T16 | 1 | T19 | 5 | T46 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 504 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 31 | 1 | T19 | 5 | T110 | 2 | T342 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 489 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 46 | 1 | T16 | 1 | T331 | 6 | T333 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 475 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 60 | 1 | T16 | 1 | T46 | 3 | T136 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 422 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 113 | 1 | T62 | 5 | T19 | 5 | T342 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 272 | 1 | T32 | 4 | T16 | 9 | T62 | 5 | ||||
auto[1] | 263 | 1 | T40 | 5 | T61 | 6 | T45 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 456 | 1 | T40 | 5 | T32 | 4 | T16 | 1 | ||||
auto[1] | 141 | 1 | T15 | 9 | T16 | 8 | T62 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 289 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 308 | 1 | T16 | 8 | T19 | 3 | T45 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 295 | 1 | T40 | 5 | T32 | 4 | T62 | 3 | ||||
auto[1] | 302 | 1 | T15 | 9 | T16 | 9 | T19 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 336 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 261 | 1 | T15 | 9 | T16 | 1 | T19 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 471 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 126 | 1 | T45 | 6 | T49 | 5 | T83 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 464 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 133 | 1 | T64 | 1 | T277 | 3 | T47 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 468 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 129 | 1 | T15 | 9 | T62 | 3 | T61 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 542 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 55 | 1 | T49 | 5 | T64 | 1 | T333 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 549 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 48 | 1 | T16 | 8 | T46 | 5 | T102 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 552 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 45 | 1 | T16 | 8 | T46 | 5 | T49 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 550 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 47 | 1 | T277 | 3 | T136 | 2 | T275 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 542 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 55 | 1 | T61 | 7 | T49 | 5 | T102 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 463 | 1 | T40 | 5 | T15 | 9 | T32 | 4 | ||||
auto[1] | 134 | 1 | T62 | 3 | T46 | 5 | T48 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 295 | 1 | T32 | 4 | T16 | 9 | T19 | 6 | ||||
auto[1] | 302 | 1 | T40 | 5 | T15 | 9 | T62 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 452 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 129 | 1 | T19 | 2 | T45 | 1 | T333 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 277 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 304 | 1 | T16 | 8 | T62 | 11 | T19 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 283 | 1 | T40 | 5 | T32 | 4 | T62 | 11 | ||||
auto[1] | 298 | 1 | T15 | 7 | T16 | 9 | T19 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 314 | 1 | T40 | 5 | T32 | 4 | T16 | 8 | ||||
auto[1] | 267 | 1 | T15 | 7 | T16 | 1 | T19 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 449 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 132 | 1 | T61 | 4 | T45 | 1 | T48 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 414 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 167 | 1 | T15 | 7 | T62 | 11 | T61 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 450 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 131 | 1 | T61 | 4 | T45 | 1 | T49 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 514 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 67 | 1 | T61 | 4 | T46 | 6 | T49 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 511 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 70 | 1 | T19 | 2 | T46 | 6 | T355 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 535 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 46 | 1 | T49 | 11 | T355 | 3 | T350 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 534 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 47 | 1 | T19 | 2 | T331 | 2 | T333 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 531 | 1 | T40 | 5 | T15 | 7 | T32 | 4 | ||||
auto[1] | 50 | 1 | T19 | 2 | T61 | 4 | T107 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 435 | 1 | T40 | 5 | T32 | 4 | T16 | 9 | ||||
auto[1] | 146 | 1 | T15 | 7 | T48 | 5 | T65 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 309 | 1 | T15 | 7 | T32 | 4 | T16 | 9 | ||||
auto[1] | 272 | 1 | T40 | 5 | T61 | 6 | T45 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |