Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T40

20

T15

11

T32

12

auto[1]

606

1

T15

9

T32

4

T16

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1853

1

T40

20

T15

16

T32

16

auto[1]

463

1

T15

4

T61

4

T45

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1729

1

T40

20

T15

9

T32

16

auto[1]

587

1

T15

11

T16

1

T62

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1815

1

T40

20

T15

11

T32

16

auto[1]

501

1

T15

9

T62

8

T61

11

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2105

1

T40

15

T15

20

T32

16

auto[1]

211

1

T40

5

T16

1

T61

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2080

1

T40

20

T15

20

T32

16

auto[1]

236

1

T16

9

T19

7

T46

19

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2148

1

T40

20

T15

20

T32

12

auto[1]

168

1

T32

4

T16

8

T19

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2121

1

T40

20

T15

20

T32

16

auto[1]

195

1

T16

1

T19

7

T277

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2119

1

T40

20

T15

20

T32

12

auto[1]

197

1

T32

4

T16

1

T19

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1734

1

T40

15

T15

13

T32

16

auto[1]

582

1

T40

5

T15

7

T62

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	779	1			T15	20		T62	19		T45	15
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	42	1			T40	5		T199	4		T345	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	46	1			T61	6		T102	6		T135	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T61	3		T107	1		T333	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	76	1			T19	5		T333	24		T342	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	29	1			T331	4		T222	3		T340	8
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	24	1			T277	3		T331	2		T92	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	18	1			T333	2		T346	4		T347	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	32	1			T107	1		T110	2		T223	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	19	1			T49	11		T342	3		T248	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	27	1			T248	1		T348	7		T349	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	12	1			T49	5		T350	3		T351	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	4	1			T331	2		T223	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T352	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T353	3		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	67	1			T354	3		T355	4		T199	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	29	1			T46	4		T354	2		T199	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	23	1			T46	3		T337	2		T352	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T64	1		T353	1		T356	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	17	1			T136	2		T275	2		T355	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T357	4		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	7	1			T19	2		T358	5		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T16	1		T92	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	40	1			T16	8		T19	5		T46	10
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	8	1			T350	1		T348	1		T82	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T102	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T359	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

152

1

T16

8

T19

2

T45

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

99

1

T40

5

T19

5

T139

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

91

1

T19

5

T45

1

T48

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T49

11

T270

8

T355

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T15

9

T61

6

T102

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T62

5

T46

5

T65

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T62

3

T46

5

T107

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

88

1

T16

1

T62

11

T46

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

59

1

T277

3

T139

2

T275

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

84

1

T15

7

T48

8

T47

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T279

3

T56

2

T112

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T48

7

T64

1

T83

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T353

8

T360

2

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T65

2

T204

1

T282

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T97

1

T199

1

T336

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

89

1

T45

6

T49

5

T331

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

53

1

T65

2

T136

4

T331

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32

1

T48

5

T157

5

T361

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T333

12

T282

3

T362

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

35

1

T45

3

T248

1

T204

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T45

1

T135

1

T250

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T83

3

T248

1

T204

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T363

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T15

4

T107

1

T331

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T48

3

T119

2

T364

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T280

8

T365

4

T89

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T111

1

T263

1

T334

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T61

3

T45

2

T48

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T263

1

T114

1

T336

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T97

1

T115

2

T118

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T204

1

T334

2

T116

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded