Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T27

9

T69

12

T104

8

auto[1]

1115

1

T27

11

T69

8

T104

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T27

5

T69

4

T104

5

from_0to1

515

1

T27

4

T69

4

T104

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T27

11

T69

11

T104

11

auto[1]

1094

1

T27

9

T69

9

T104

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T27

9

T69

9

T104

11

auto[1]

1121

1

T27

11

T69

11

T104

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T69

2

T104

1

T190

2

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T27

1

T190

1

T63

3

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T27

2

T193

2

T252

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T376

1

T377

1

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T69

2

T193

1

T330

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T27

1

T78

3

T190

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T104

1

T193

2

T376

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T27

1

T69

1

T104

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T27

2

T104

1

T78

2

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T69

2

T104

2

T78

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T78

2

T377

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T104

1

T78

1

T330

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T27

1

T104

1

T190

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T78

2

T252

1

T376

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T27

1

T104

1

T190

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T69

1

T78

1

T190

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T27

8

T69

9

T104

8

auto[1]

1123

1

T27

12

T69

11

T104

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T27

5

T69

8

T104

5

from_0to1

533

1

T27

6

T69

7

T104

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T27

9

T69

12

T104

11

auto[1]

1090

1

T27

11

T69

8

T104

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T27

13

T69

9

T104

7

auto[1]

1098

1

T27

7

T69

11

T104

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T78

1

T193

1

T330

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T69

2

T190

2

T193

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T27

1

T69

1

T190

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T104

1

T193

1

T330

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T27

1

T69

1

T104

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T69

2

T104

1

T330

2

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T27

2

T104

1

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T27

1

T69

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T27

2

T69

1

T104

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T69

2

T104

2

T252

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T69

2

T330

1

T376

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T27

2

T104

1

T78

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T27

1

T69

2

T193

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T78

1

T190

2

T193

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T104

1

T193

1

T48

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T27

1

T69

1

T190

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T27

11

T69

9

T104

5

auto[1]

1139

1

T27

9

T69

11

T104

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T27

2

T69

5

T104

4

from_0to1

522

1

T27

2

T69

5

T104

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T27

10

T69

5

T104

7

auto[1]

1074

1

T27

10

T69

15

T104

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T27

11

T69

13

T104

12

auto[1]

1108

1

T27

9

T69

7

T104

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T69

1

T104

1

T376

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T27

1

T69

1

T78

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T27

1

T69

1

T330

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T69

1

T193

1

T330

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T104

1

T78

1

T376

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T78

1

T190

2

T193

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T27

1

T69

2

T104

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T69

1

T378

1

T234

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T104

1

T78

1

T193

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T78

1

T190

1

T376

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T190

1

T193

1

T252

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T69

1

T104

2

T78

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T27

1

T69

1

T190

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T104

1

T193

1

T376

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T104

2

T78

2

T252

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T69

1

T252

1

T376

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T27

10

T69

8

T104

8

auto[1]

1119

1

T27

10

T69

12

T104

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T27

7

T69

7

T104

6

from_0to1

532

1

T27

7

T69

6

T104

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T27

9

T69

12

T104

14

auto[1]

1127

1

T27

11

T69

8

T104

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T27

9

T69

12

T104

6

auto[1]

1134

1

T27

11

T69

8

T104

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T27

1

T69

1

T104

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T27

2

T69

2

T104

2

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T69

1

T78

1

T330

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T27

2

T252

1

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T104

1

T78

1

T252

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T27

1

T78

1

T190

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T27

1

T78

1

T190

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T27

2

T104

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T104

1

T190

1

T193

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T27

1

T69

1

T104

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T27

1

T69

1

T193

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T69

1

T104

1

T330

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T27

2

T69

3

T193

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T69

2

T104

2

T78

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T69

1

T104

2

T193

2

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T27

1

T193

2

T330

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T27

10

T69

7

T104

13

auto[1]

1102

1

T27

10

T69

13

T104

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

546

1

T27

6

T69

6

T104

4

from_0to1

537

1

T27

5

T69

6

T104

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1145

1

T27

10

T69

11

T104

8

auto[1]

1075

1

T27

10

T69

9

T104

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T27

5

T69

14

T104

11

auto[1]

1108

1

T27

15

T69

6

T104

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T69

1

T104

1

T190

2

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T27

2

T190

1

T377

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T69

2

T104

2

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T27

2

T104

1

T330

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T63

1

T48

1

T83

2

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T69

1

T190

2

T330

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T27

1

T190

1

T193

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T69

1

T104

2

T190

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T69

1

T190

2

T193

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T69

2

T78

2

T252

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T27

1

T190

1

T330

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T27

1

T330

2

T377

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T69

3

T104

1

T190

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T27

1

T193

1

T252

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T27

2

T69

1

T104

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T27

1

T78

2

T330

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T27

12

T69

12

T104

8

auto[1]

1098

1

T27

8

T69

8

T104

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T27

6

T69

5

T104

4

from_0to1

503

1

T27

5

T69

6

T104

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T27

9

T69

10

T104

10

auto[1]

1111

1

T27

11

T69

10

T104

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T27

14

T69

11

T104

13

auto[1]

1093

1

T27

6

T69

9

T104

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T27

2

T69

1

T78

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T78

1

T190

1

T330

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T27

1

T69

2

T104

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T69

1

T193

1

T377

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T27

1

T190

1

T193

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T69

1

T104

2

T376

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T69

2

T252

2

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T27

1

T69

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T69

1

T104

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T27

1

T252

1

T376

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T27

1

T104

2

T193

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T27

1

T193

2

T63

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T27

1

T69

1

T104

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T69

1

T104

1

T78

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T27

2

T104

1

T252

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T78

1

T330

1

T376

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T27

12

T69

11

T104

9

auto[1]

1123

1

T27

8

T69

9

T104

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T27

5

T69

5

T104

3

from_0to1

525

1

T27

5

T69

6

T104

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T27

13

T69

10

T104

11

auto[1]

1108

1

T27

7

T69

10

T104

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T27

12

T69

8

T104

7

auto[1]

1063

1

T27

8

T69

12

T104

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T27

2

T193

2

T252

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T69

1

T78

1

T193

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T69

1

T190

1

T330

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T27

1

T190

1

T377

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T27

2

T104

1

T193

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T27

1

T69

2

T193

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T193

1

T330

1

T252

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T69

1

T78

1

T252

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T27

2

T69

2

T104

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T190

1

T193

1

T330

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T69

1

T193

1

T330

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T104

2

T78

1

T193

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T27

1

T69

1

T190

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T78

1

T193

1

T330

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T193

1

T48

2

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T27

1

T69

2

T104

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T27

10

T69

11

T104

11

auto[1]

1133

1

T27

10

T69

9

T104

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T27

4

T69

3

T104

3

from_0to1

507

1

T27

5

T69

3

T104

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T27

10

T69

11

T104

11

auto[1]

1091

1

T27

10

T69

9

T104

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T27

12

T69

11

T104

6

auto[1]

1132

1

T27

8

T69

9

T104

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T78

1

T190

2

T252

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T78

1

T330

1

T252

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T190

1

T193

1

T330

3

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T27

1

T69

1

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T69

1

T78

1

T190

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T27

1

T69

1

T78

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T27

1

T104

1

T193

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T27

1

T104

1

T330

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T27

2

T104

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T104

1

T252

1

T376

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T27

1

T69

1

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T69

1

T104

1

T193

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T27

2

T69

1

T104

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T252

1

T379

1

T48

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T193

1

T330

1

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T78

1

T190

1

T193

1