Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117552

1

T4

515

T5

11

T1

909

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136307	1			T4	112		T5	20		T1	418
values[0x0]	65170	1			T4	213		T5	6		T1	247
values[0x1]	66245	1			T4	275		T5	13		T1	245

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145698

1

T4

572

T5

18

T1

909

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1136	1			T4	1		T1	1		T6	16
valid_sources[0x01]	921	1			T1	4		T3	9		T6	18
valid_sources[0x02]	2124	1			T4	3		T1	4		T6	16
valid_sources[0x03]	1126	1			T4	4		T1	1		T6	4
valid_sources[0x04]	932	1			T4	5		T1	9		T23	36
valid_sources[0x05]	1544	1			T4	3		T1	5		T6	11
valid_sources[0x06]	957	1			T4	2		T6	13		T7	6
valid_sources[0x07]	1031	1			T4	3		T1	7		T6	20
valid_sources[0x08]	1012	1			T4	2		T1	3		T23	3
valid_sources[0x09]	988	1			T4	2		T1	4		T6	9
valid_sources[0x0a]	800	1			T4	3		T6	6		T7	2
valid_sources[0x0b]	1757	1			T4	1		T1	4		T6	6
valid_sources[0x0c]	1135	1			T4	2		T1	4		T6	6
valid_sources[0x0d]	1102	1			T4	1		T1	4		T23	17
valid_sources[0x0e]	1299	1			T4	2		T1	6		T3	1
valid_sources[0x0f]	869	1			T4	1		T1	6		T6	24
valid_sources[0x10]	1180	1			T4	1		T1	7		T6	18
valid_sources[0x11]	1598	1			T4	4		T1	5		T6	6
valid_sources[0x12]	966	1			T4	9		T1	8		T6	29
valid_sources[0x13]	884	1			T4	6		T1	5		T6	11
valid_sources[0x14]	804	1			T4	1		T1	9		T6	15
valid_sources[0x15]	1201	1			T4	1		T1	4		T3	7
valid_sources[0x16]	743	1			T6	12		T7	1		T24	29
valid_sources[0x17]	868	1			T4	3		T3	3		T6	17
valid_sources[0x18]	1039	1			T4	3		T1	1		T6	6
valid_sources[0x19]	786	1			T3	6		T6	24		T7	3
valid_sources[0x1a]	821	1			T4	5		T6	10		T7	6
valid_sources[0x1b]	813	1			T4	3		T1	7		T3	1
valid_sources[0x1c]	811	1			T4	3		T1	9		T3	1
valid_sources[0x1d]	1555	1			T4	1		T3	3		T6	3
valid_sources[0x1e]	1131	1			T1	6		T6	3		T24	31
valid_sources[0x1f]	2097	1			T4	2		T1	4		T6	20
valid_sources[0x20]	894	1			T1	4		T6	3		T7	3
valid_sources[0x21]	910	1			T4	2		T1	4		T6	6
valid_sources[0x22]	980	1			T4	1		T1	3		T6	17
valid_sources[0x23]	1017	1			T1	2		T6	1		T7	4
valid_sources[0x24]	1463	1			T4	2		T1	3		T6	5
valid_sources[0x25]	862	1			T4	3		T1	3		T6	6
valid_sources[0x26]	1859	1			T4	3		T6	5		T7	6
valid_sources[0x27]	1099	1			T4	3		T1	3		T6	8
valid_sources[0x28]	781	1			T4	1		T1	2		T6	11
valid_sources[0x29]	1194	1			T4	1		T6	22		T7	1
valid_sources[0x2a]	967	1			T4	2		T6	26		T7	2
valid_sources[0x2b]	889	1			T7	7		T24	15		T8	4
valid_sources[0x2c]	1556	1			T4	3		T1	10		T23	47
valid_sources[0x2d]	1020	1			T4	3		T1	3		T6	8
valid_sources[0x2e]	1754	1			T6	10		T7	5		T24	11
valid_sources[0x2f]	1076	1			T4	1		T1	8		T6	8
valid_sources[0x30]	681	1			T4	4		T1	2		T6	7
valid_sources[0x31]	1850	1			T4	4		T6	11		T7	5
valid_sources[0x32]	999	1			T4	4		T1	3		T6	12
valid_sources[0x33]	1274	1			T4	7		T1	4		T3	1
valid_sources[0x34]	1009	1			T3	3		T6	24		T7	2
valid_sources[0x35]	985	1			T4	1		T1	4		T6	20
valid_sources[0x36]	787	1			T4	2		T1	7		T6	6
valid_sources[0x37]	997	1			T4	3		T1	8		T6	15
valid_sources[0x38]	1749	1			T4	3		T1	2		T6	3
valid_sources[0x39]	990	1			T4	1		T1	3		T3	4
valid_sources[0x3a]	821	1			T4	2		T1	2		T6	16
valid_sources[0x3b]	873	1			T4	1		T1	2		T7	4
valid_sources[0x3c]	1047	1			T4	1		T1	5		T6	6
valid_sources[0x3d]	1151	1			T4	4		T2	38		T6	28
valid_sources[0x3e]	1152	1			T4	2		T1	4		T3	12
valid_sources[0x3f]	866	1			T4	3		T1	12		T3	2
valid_sources[0x40]	730	1			T4	2		T1	7		T6	15
valid_sources[0x41]	1284	1			T4	7		T1	3		T6	7
valid_sources[0x42]	994	1			T4	1		T6	22		T7	3
valid_sources[0x43]	919	1			T4	1		T1	5		T3	1
valid_sources[0x44]	785	1			T4	3		T1	2		T6	2
valid_sources[0x45]	920	1			T4	2		T1	12		T3	1
valid_sources[0x46]	988	1			T4	2		T3	6		T6	7
valid_sources[0x47]	1943	1			T4	2		T1	6		T6	20
valid_sources[0x48]	1187	1			T4	1		T1	2		T3	2
valid_sources[0x49]	1221	1			T4	4		T1	2		T6	13
valid_sources[0x4a]	1023	1			T4	2		T1	1		T3	1
valid_sources[0x4b]	1194	1			T4	2		T1	5		T6	10
valid_sources[0x4c]	868	1			T4	5		T2	20		T6	3
valid_sources[0x4d]	1273	1			T4	1		T1	2		T6	11
valid_sources[0x4e]	1042	1			T4	3		T1	19		T23	51
valid_sources[0x4f]	913	1			T4	3		T1	5		T6	6
valid_sources[0x50]	889	1			T4	4		T1	9		T6	15
valid_sources[0x51]	801	1			T4	2		T1	5		T6	11
valid_sources[0x52]	728	1			T4	1		T1	3		T6	2
valid_sources[0x53]	1457	1			T1	5		T6	11		T7	5
valid_sources[0x54]	1242	1			T4	4		T1	2		T6	6
valid_sources[0x55]	985	1			T4	3		T1	14		T6	8
valid_sources[0x56]	1142	1			T4	2		T1	8		T6	5
valid_sources[0x57]	1820	1			T4	2		T1	11		T3	2
valid_sources[0x58]	1021	1			T4	1		T1	1		T6	3
valid_sources[0x59]	1054	1			T6	29		T7	3		T24	8
valid_sources[0x5a]	861	1			T4	3		T6	12		T7	4
valid_sources[0x5b]	838	1			T4	4		T3	4		T6	5
valid_sources[0x5c]	848	1			T4	1		T1	1		T3	1
valid_sources[0x5d]	1054	1			T4	3		T1	14		T3	1
valid_sources[0x5e]	1784	1			T4	2		T1	3		T6	2
valid_sources[0x5f]	994	1			T4	4		T1	3		T6	8
valid_sources[0x60]	862	1			T4	2		T6	29		T7	5
valid_sources[0x61]	777	1			T4	2		T1	3		T3	2
valid_sources[0x62]	1410	1			T4	5		T1	6		T6	4
valid_sources[0x63]	1095	1			T1	5		T6	36		T7	6
valid_sources[0x64]	854	1			T4	1		T1	4		T6	11
valid_sources[0x65]	894	1			T4	5		T1	8		T3	3
valid_sources[0x66]	1162	1			T4	6		T3	11		T6	12
valid_sources[0x67]	764	1			T4	4		T1	3		T6	22
valid_sources[0x68]	1193	1			T4	2		T1	7		T6	21
valid_sources[0x69]	1077	1			T4	1		T1	6		T6	11
valid_sources[0x6a]	991	1			T4	4		T1	3		T6	23
valid_sources[0x6b]	715	1			T4	1		T6	11		T7	3
valid_sources[0x6c]	1046	1			T4	3		T1	5		T6	18
valid_sources[0x6d]	821	1			T4	1		T1	3		T3	3
valid_sources[0x6e]	1012	1			T3	7		T6	5		T7	3
valid_sources[0x6f]	860	1			T4	1		T1	10		T6	1
valid_sources[0x70]	1064	1			T4	3		T6	12		T7	2
valid_sources[0x71]	1216	1			T4	3		T1	2		T6	10
valid_sources[0x72]	1474	1			T4	2		T1	8		T7	6
valid_sources[0x73]	1000	1			T4	1		T23	38		T6	19
valid_sources[0x74]	950	1			T4	2		T1	2		T6	3
valid_sources[0x75]	1374	1			T4	5		T1	6		T7	3
valid_sources[0x76]	901	1			T4	5		T3	3		T6	14
valid_sources[0x77]	793	1			T4	1		T1	3		T6	4
valid_sources[0x78]	983	1			T4	4		T1	18		T23	12
valid_sources[0x79]	1200	1			T4	1		T1	8		T6	14
valid_sources[0x7a]	846	1			T4	3		T1	1		T6	44
valid_sources[0x7b]	969	1			T4	3		T1	3		T6	15
valid_sources[0x7c]	870	1			T4	3		T1	1		T3	7
valid_sources[0x7d]	949	1			T4	2		T1	1		T6	12
valid_sources[0x7e]	899	1			T4	2		T6	12		T7	1
valid_sources[0x7f]	980	1			T4	3		T1	11		T3	4
valid_sources[0x80]	1245	1			T4	3		T1	3		T6	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63284

1

T4

104

T5

9

T1

417

values[0x0]

all_enables

biggest_size

31729

1

T4

208

T5

1

T1

247

values[0x1]

all_enables

biggest_size

22539

1

T4

203

T5

1

T1

245