Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1403211215	11436	0	0
auto_block_debounce_ctl_rd_A	1403211215	1593	0	0
auto_block_out_ctl_rd_A	1403211215	2152	0	0
com_det_ctl_0_rd_A	1403211215	3594	0	0
com_det_ctl_1_rd_A	1403211215	3780	0	0
com_det_ctl_2_rd_A	1403211215	3814	0	0
com_det_ctl_3_rd_A	1403211215	3912	0	0
com_out_ctl_0_rd_A	1403211215	4283	0	0
com_out_ctl_1_rd_A	1403211215	4352	0	0
com_out_ctl_2_rd_A	1403211215	4205	0	0
com_out_ctl_3_rd_A	1403211215	4249	0	0
com_pre_det_ctl_0_rd_A	1403211215	1437	0	0
com_pre_det_ctl_1_rd_A	1403211215	1288	0	0
com_pre_det_ctl_2_rd_A	1403211215	1240	0	0
com_pre_det_ctl_3_rd_A	1403211215	1381	0	0
com_pre_sel_ctl_0_rd_A	1403211215	4323	0	0
com_pre_sel_ctl_1_rd_A	1403211215	4265	0	0
com_pre_sel_ctl_2_rd_A	1403211215	4160	0	0
com_pre_sel_ctl_3_rd_A	1403211215	4339	0	0
com_sel_ctl_0_rd_A	1403211215	4393	0	0
com_sel_ctl_1_rd_A	1403211215	4168	0	0
com_sel_ctl_2_rd_A	1403211215	4157	0	0
com_sel_ctl_3_rd_A	1403211215	4099	0	0
ec_rst_ctl_rd_A	1403211215	2404	0	0
intr_enable_rd_A	1403211215	1659	0	0
key_intr_ctl_rd_A	1403211215	2779	0	0
key_intr_debounce_ctl_rd_A	1403211215	1356	0	0
key_invert_ctl_rd_A	1403211215	4464	0	0
pin_allowed_ctl_rd_A	1403211215	4743	0	0
pin_out_ctl_rd_A	1403211215	3754	0	0
pin_out_value_rd_A	1403211215	3870	0	0
regwen_rd_A	1403211215	1426	0	0
ulp_ac_debounce_ctl_rd_A	1403211215	1454	0	0
ulp_ctl_rd_A	1403211215	1413	0	0
ulp_lid_debounce_ctl_rd_A	1403211215	1485	0	0
ulp_pwrb_debounce_ctl_rd_A	1403211215	1438	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	11436	0	0
T1	265566	0	0	0
T2	198038	0	0	0
T3	98837	0	0	0
T4	24325	730	0	0
T5	48690	0	0	0
T6	319582	0	0	0
T7	201602	0	0	0
T8	111462	5	0	0
T9	0	79	0	0
T23	51052	395	0	0
T24	674989	0	0	0
T34	0	7	0	0
T295	0	248	0	0
T298	0	1	0	0
T299	0	534	0	0
T300	0	733	0	0
T301	0	302	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1593	0	0
T8	111462	34	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	409	0	0
T34	0	56	0	0
T38	0	59	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	10	0	0
T310	0	3	0	0
T311	0	9	0	0
T312	0	3	0	0
T313	0	67	0	0
T314	0	13	0	0
T315	131078	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	2152	0	0
T8	111462	69	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	426	0	0
T34	0	112	0	0
T38	0	185	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	29	0	0
T310	0	5	0	0
T311	0	7	0	0
T312	0	9	0	0
T313	0	172	0	0
T314	0	6	0	0
T315	131078	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	3594	0	0
T8	111462	18	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	428	0	0
T34	0	40	0	0
T38	0	34	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	23	0	0
T310	0	6	0	0
T311	0	5	0	0
T312	0	8	0	0
T313	0	37	0	0
T315	131078	0	0	0
T316	0	4	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	3780	0	0
T8	111462	8	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	419	0	0
T34	0	29	0	0
T38	0	35	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	15	0	0
T310	0	8	0	0
T311	0	8	0	0
T312	0	5	0	0
T313	0	37	0	0
T314	0	10	0	0
T315	131078	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	3814	0	0
T8	111462	29	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	464	0	0
T34	0	46	0	0
T38	0	34	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	7	0	0
T310	0	4	0	0
T311	0	12	0	0
T312	0	3	0	0
T313	0	13	0	0
T314	0	8	0	0
T315	131078	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	3912	0	0
T8	111462	14	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	365	0	0
T34	0	42	0	0
T38	0	21	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	27	0	0
T311	0	6	0	0
T312	0	17	0	0
T313	0	35	0	0
T314	0	10	0	0
T315	131078	0	0	0
T316	0	2	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4283	0	0
T8	111462	53	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	418	0	0
T34	0	109	0	0
T38	0	124	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	25	0	0
T310	0	4	0	0
T311	0	7	0	0
T312	0	10	0	0
T313	0	113	0	0
T314	0	6	0	0
T315	131078	0	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4352	0	0
T8	111462	47	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	518	0	0
T34	0	90	0	0
T38	0	77	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	2	0	0
T310	0	2	0	0
T311	0	4	0	0
T312	0	12	0	0
T313	0	96	0	0
T314	0	1	0	0
T315	131078	0	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4205	0	0
T8	111462	46	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	437	0	0
T34	0	106	0	0
T38	0	110	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	6	0	0
T310	0	3	0	0
T311	0	3	0	0
T312	0	7	0	0
T313	0	100	0	0
T314	0	9	0	0
T315	131078	0	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4249	0	0
T8	111462	39	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	441	0	0
T34	0	98	0	0
T38	0	76	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	28	0	0
T310	0	8	0	0
T311	0	5	0	0
T312	0	10	0	0
T313	0	151	0	0
T314	0	11	0	0
T315	131078	0	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1437	0	0
T8	111462	21	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	410	0	0
T34	0	39	0	0
T38	0	38	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	8	0	0
T310	0	6	0	0
T311	0	4	0	0
T312	0	4	0	0
T313	0	19	0	0
T314	0	12	0	0
T315	131078	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1288	0	0
T8	111462	31	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	457	0	0
T34	0	42	0	0
T38	0	25	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	5	0	0
T311	0	11	0	0
T312	0	4	0	0
T313	0	25	0	0
T314	0	3	0	0
T315	131078	0	0	0
T316	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1240	0	0
T8	111462	26	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	414	0	0
T34	0	41	0	0
T38	0	12	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	2	0	0
T310	0	3	0	0
T311	0	8	0	0
T312	0	2	0	0
T313	0	37	0	0
T314	0	11	0	0
T315	131078	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1381	0	0
T8	111462	22	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	417	0	0
T34	0	32	0	0
T38	0	31	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	31	0	0
T310	0	9	0	0
T311	0	3	0	0
T312	0	10	0	0
T313	0	43	0	0
T314	0	16	0	0
T315	131078	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4323	0	0
T8	111462	70	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	384	0	0
T34	0	132	0	0
T38	0	127	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	4	0	0
T310	0	5	0	0
T311	0	10	0	0
T312	0	7	0	0
T313	0	123	0	0
T314	0	7	0	0
T315	131078	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4265	0	0
T8	111462	61	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	383	0	0
T34	0	164	0	0
T38	0	91	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	4	0	0
T311	0	7	0	0
T312	0	3	0	0
T313	0	125	0	0
T314	0	10	0	0
T315	131078	0	0	0
T316	0	6	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4160	0	0
T8	111462	88	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	485	0	0
T34	0	166	0	0
T38	0	79	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T310	0	6	0	0
T311	0	5	0	0
T312	0	5	0	0
T313	0	98	0	0
T314	0	7	0	0
T315	131078	0	0	0
T316	0	5	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4339	0	0
T8	111462	58	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	435	0	0
T34	0	108	0	0
T38	0	121	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	9	0	0
T310	0	5	0	0
T311	0	12	0	0
T312	0	14	0	0
T313	0	141	0	0
T314	0	12	0	0
T315	131078	0	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4393	0	0
T8	111462	34	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	433	0	0
T34	0	195	0	0
T38	0	96	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T310	0	6	0	0
T311	0	10	0	0
T312	0	5	0	0
T313	0	138	0	0
T314	0	1	0	0
T315	131078	0	0	0
T316	0	6	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4168	0	0
T8	111462	53	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	394	0	0
T34	0	131	0	0
T38	0	46	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	10	0	0
T311	0	6	0	0
T312	0	10	0	0
T313	0	113	0	0
T314	0	18	0	0
T315	131078	0	0	0
T316	0	8	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4157	0	0
T8	111462	56	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	444	0	0
T34	0	131	0	0
T38	0	82	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T310	0	3	0	0
T311	0	1	0	0
T312	0	4	0	0
T313	0	118	0	0
T314	0	10	0	0
T315	131078	0	0	0
T316	0	20	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4099	0	0
T8	111462	52	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	415	0	0
T34	0	119	0	0
T38	0	57	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	13	0	0
T310	0	3	0	0
T311	0	6	0	0
T312	0	13	0	0
T313	0	69	0	0
T314	0	6	0	0
T315	131078	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	2404	0	0
T8	111462	9	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	442	0	0
T34	0	42	0	0
T38	0	18	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	3	0	0
T311	0	8	0	0
T312	0	13	0	0
T313	0	53	0	0
T314	0	9	0	0
T315	131078	0	0	0
T316	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1659	0	0
T8	111462	24	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	432	0	0
T34	0	40	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T310	0	6	0	0
T311	0	3	0	0
T312	0	9	0	0
T313	0	48	0	0
T315	131078	0	0	0
T317	0	6	0	0
T318	0	21	0	0
T319	0	15	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	2779	0	0
T8	111462	158	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	390	0	0
T34	0	96	0	0
T38	0	339	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	8	0	0
T310	0	6	0	0
T311	0	13	0	0
T312	0	9	0	0
T313	0	248	0	0
T314	0	8	0	0
T315	131078	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1356	0	0
T8	111462	16	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	446	0	0
T34	0	59	0	0
T38	0	43	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	17	0	0
T310	0	2	0	0
T311	0	6	0	0
T313	0	42	0	0
T314	0	9	0	0
T315	131078	0	0	0
T316	0	9	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4464	0	0
T8	111462	51	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	468	0	0
T34	0	309	0	0
T38	0	190	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	14	0	0
T311	0	4	0	0
T312	0	5	0	0
T313	0	249	0	0
T314	0	10	0	0
T315	131078	0	0	0
T316	0	54	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	4743	0	0
T8	111462	220	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	432	0	0
T34	0	471	0	0
T38	0	252	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	4	0	0
T310	0	1	0	0
T311	0	5	0	0
T312	0	11	0	0
T313	0	284	0	0
T314	0	20	0	0
T315	131078	0	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	3754	0	0
T8	111462	111	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	438	0	0
T34	0	205	0	0
T38	0	118	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	40	0	0
T310	0	8	0	0
T311	0	16	0	0
T312	0	12	0	0
T313	0	174	0	0
T315	131078	0	0	0
T316	0	1	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	3870	0	0
T8	111462	90	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	394	0	0
T34	0	130	0	0
T38	0	184	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	10	0	0
T310	0	1	0	0
T311	0	12	0	0
T312	0	7	0	0
T313	0	241	0	0
T314	0	1	0	0
T315	131078	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1426	0	0
T8	111462	35	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	462	0	0
T34	0	43	0	0
T38	0	52	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	15	0	0
T310	0	10	0	0
T311	0	2	0	0
T312	0	8	0	0
T313	0	48	0	0
T314	0	17	0	0
T315	131078	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1454	0	0
T8	111462	33	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	438	0	0
T34	0	27	0	0
T38	0	36	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	14	0	0
T310	0	4	0	0
T311	0	14	0	0
T312	0	8	0	0
T313	0	43	0	0
T314	0	14	0	0
T315	131078	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1413	0	0
T8	111462	28	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	445	0	0
T34	0	25	0	0
T38	0	44	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	15	0	0
T311	0	5	0	0
T312	0	1	0	0
T313	0	55	0	0
T314	0	4	0	0
T315	131078	0	0	0
T320	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1485	0	0
T8	111462	19	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	414	0	0
T34	0	27	0	0
T38	0	46	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	6	0	0
T310	0	6	0	0
T311	0	9	0	0
T312	0	1	0	0
T313	0	50	0	0
T314	0	15	0	0
T315	131078	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1403211215	1438	0	0
T8	111462	19	0	0
T9	53930	0	0	0
T10	302551	0	0	0
T11	198434	0	0	0
T12	197020	0	0	0
T25	188570	405	0	0
T34	0	49	0	0
T38	0	58	0	0
T42	195438	0	0	0
T43	48730	0	0	0
T295	204226	0	0	0
T299	0	15	0	0
T310	0	4	0	0
T311	0	8	0	0
T312	0	3	0	0
T313	0	39	0	0
T314	0	5	0	0
T315	131078	0	0	0