Unified Coverage Report :: Module :: prim_reg_cdc_arb

Module : prim_reg_cdc_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	96.51			95.65	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb	83.33	100.00	66.67
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb	83.33	100.00	66.67
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb	83.33	100.00	66.67
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb	83.33	100.00	66.67
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb	83.33	100.00	66.67
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb	83.33	100.00	66.67
tb.dut.u_reg.u_ulp_status_cdc.u_arb	90.16	92.00	86.05			82.61	100.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb	90.16	92.00	86.05			82.61	100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb	97.17	100.00	93.02			95.65	100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb	97.17	100.00	93.02			95.65	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb	100.00	100.00	100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	300	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
284	1	1
285	1	1
300		unreachable

---

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.16	92.00

tb.dut.u_reg.u_ulp_status_cdc.u_arb

SCORE	LINE
90.16	92.00

tb.dut.u_reg.u_wkup_status_cdc.u_arb

SCORE	LINE
97.17	100.00

tb.dut.u_reg.u_combo_intr_status_cdc.u_arb

SCORE	LINE
97.17	100.00

tb.dut.u_reg.u_key_intr_status_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	112	3	3	100.00
ALWAYS	122	6	6	100.00
CONT_ASSIGN	136	1	1	100.00
ALWAYS	140	6	6	100.00
ALWAYS	156	10	10	100.00
CONT_ASSIGN	184	1	1	100.00
ALWAYS	188	19	19	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
112	1	1
113	1	1
115	1	1
122	1	1
123	1	1
124	1	1
129	1	1
130	1	1
133	1	1
			MISSING_ELSE
136	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
184	1	1
188	1	1
189	1	1
193	1	1
194	1	1
196	1	1
198	1	1
200	1	1
201	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
211	1	1
212	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
229	1	1
244	1	1
245	1	1

---

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

---

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.16	86.05

tb.dut.u_reg.u_ulp_status_cdc.u_arb

SCORE	COND
90.16	86.05

tb.dut.u_reg.u_wkup_status_cdc.u_arb

SCORE	COND
97.17	93.02

tb.dut.u_reg.u_combo_intr_status_cdc.u_arb

SCORE	COND
97.17	93.02

tb.dut.u_reg.u_key_intr_status_cdc.u_arb

	Total	Covered	Percent
Conditions	43	40	93.02
Logical	43	40	93.02
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T14,T15

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T3,T7

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T7

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T13,T14,T15

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T13,T20,T21

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T13,T20,T21
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T4,T5,T1

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T14,T15

---

Branch Coverage for Module : prim_reg_cdc_arb

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
IF	112	2	2	100.00
IF	122	4	4	100.00
IF	140	4	4	100.00
IF	156	6	6	100.00
CASE	198	7	6	85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	112	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	122	if ((!rst_dst_ni))
-2-:	124	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	130	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	if ((!rst_dst_ni))
-2-:	142	if (gen_wr_req.dst_lat_d)
-3-:	144	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T13,T20,T21
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	156	if ((!rst_dst_ni))
-2-:	158	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	160	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	162	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	164	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T1
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T13,T14,T15
0	0	0	0	1	Covered	T13,T20,T21
0	0	0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	198	case (gen_wr_req.state_q)
-2-:	201	if (gen_wr_req.dst_req)
-3-:	205	if (dst_update)
-4-:	208	if ((dst_qs_o != dst_qs_i))
-5-:	218	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	Covered	T13,T14,T15
StIdle	0	0	1	-	Covered	T13,T20,T21
StIdle	0	0	0	-	Covered	T1,T3,T6
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Module : prim_reg_cdc_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	32101376	1593	0	3656
gen_wr_req.HwIdSelCheck_A	32101376	1757	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32101376	1593	0	3656
T13	2154	1	0	1
T14	569	2	0	1
T15	54078	20	0	2
T16	23425	1	0	1
T17	1648	2	0	1
T18	63755	1	0	1
T19	23904	3	0	1
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T26	99226	0	0	1
T27	502	0	0	1
T28	659	0	0	1
T29	1172	0	0	2
T30	1096	0	0	2
T31	2676	0	0	2
T32	15978	0	0	2
T44	0	1	0	0
T45	0	7	0	0
T46	0	4	0	0
T48	0	28	0	0
T49	0	7	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T62	33073	0	0	1
T63	0	3	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	494	0	0	1
T67	422	0	0	1
T68	631	0	0	1
T69	510	0	0	1
T70	445	0	0	1
T71	421	0	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32101376	1757	0	0
T13	2154	2	0	0
T14	569	2	0	0
T15	54078	20	0	0
T16	23425	1	0	0
T17	1648	2	0	0
T18	63755	1	0	0
T19	23904	3	0	0
T20	0	2	0	0
T21	0	4	0	0
T22	0	3	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	1172	0	0	0
T30	1096	0	0	0
T31	2676	0	0	0
T32	15978	0	0	0
T44	0	1	0	0
T45	0	9	0	0
T46	0	4	0	0
T48	0	31	0	0
T49	0	7	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	0	4	0	0
T62	33073	0	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T70	445	0	0	0
T71	421	0	0	0