SYSRST_CTRL Simulation Results

Wednesday October 11 2023 19:03:00 UTC

GitHub Revision: f600eccc2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1737291072

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.530s 2.114ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 7.790s 2.461ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.390s 2.386ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.780s 2.540ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 16.980s 6.042ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.390s 2.046ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.611m 38.273ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 15.680s 3.167ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.590s 2.067ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.390s 2.046ms 20 20 100.00
sysrst_ctrl_csr_aliasing 15.680s 3.167ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 7.506m 159.389ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 9.681m 230.597ms 94 100 94.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 13.455m 309.391ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 19.248m 1.889s 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.590s 2.508ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.740s 2.192ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 35.014m 778.867ms 47 50 94.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.930s 2.615ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.549m 1.298s 48 50 96.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 52.960s 39.783ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 11.691m 253.180ms 48 50 96.00
V2 alert_test sysrst_ctrl_alert_test 6.170s 2.011ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.110s 2.013ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.930s 2.039ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.930s 2.039ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 16.980s 6.042ms 5 5 100.00
sysrst_ctrl_csr_rw 6.390s 2.046ms 20 20 100.00
sysrst_ctrl_csr_aliasing 15.680s 3.167ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 29.610s 7.774ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 16.980s 6.042ms 5 5 100.00
sysrst_ctrl_csr_rw 6.390s 2.046ms 20 20 100.00
sysrst_ctrl_csr_aliasing 15.680s 3.167ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 29.610s 7.774ms 20 20 100.00
V2 TOTAL 679 692 98.12
V2S tl_intg_err sysrst_ctrl_sec_cm 1.724m 42.009ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.760m 42.489ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.760m 42.489ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.158m 1.517s 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 914 932 98.07

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 11 73.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.55 99.29 96.26 100.00 95.51 98.68 99.34 93.79

Failure Buckets

Past Results