f600eccc2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sysrst_ctrl_smoke | 6.530s | 2.114ms | 50 | 50 | 100.00 |
V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 7.790s | 2.461ms | 50 | 50 | 100.00 |
V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 6.390s | 2.386ms | 5 | 5 | 100.00 |
V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 6.780s | 2.540ms | 5 | 5 | 100.00 |
V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 16.980s | 6.042ms | 5 | 5 | 100.00 |
V1 | csr_rw | sysrst_ctrl_csr_rw | 6.390s | 2.046ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 3.611m | 38.273ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 15.680s | 3.167ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 6.590s | 2.067ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 6.390s | 2.046ms | 20 | 20 | 100.00 |
sysrst_ctrl_csr_aliasing | 15.680s | 3.167ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 165 | 165 | 100.00 | |||
V2 | combo_detect | sysrst_ctrl_combo_detect | 7.506m | 159.389ms | 50 | 50 | 100.00 |
V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 9.681m | 230.597ms | 94 | 100 | 94.00 |
V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 13.455m | 309.391ms | 50 | 50 | 100.00 |
V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 19.248m | 1.889s | 50 | 50 | 100.00 |
V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 7.590s | 2.508ms | 50 | 50 | 100.00 |
V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 6.740s | 2.192ms | 50 | 50 | 100.00 |
V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 35.014m | 778.867ms | 47 | 50 | 94.00 |
V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 7.930s | 2.615ms | 50 | 50 | 100.00 |
V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 4.549m | 1.298s | 48 | 50 | 96.00 |
V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 52.960s | 39.783ms | 2 | 2 | 100.00 |
V2 | stress_all | sysrst_ctrl_stress_all | 11.691m | 253.180ms | 48 | 50 | 96.00 |
V2 | alert_test | sysrst_ctrl_alert_test | 6.170s | 2.011ms | 50 | 50 | 100.00 |
V2 | intr_test | sysrst_ctrl_intr_test | 6.110s | 2.013ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 7.930s | 2.039ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 7.930s | 2.039ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 16.980s | 6.042ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.390s | 2.046ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 15.680s | 3.167ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 29.610s | 7.774ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 16.980s | 6.042ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.390s | 2.046ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 15.680s | 3.167ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 29.610s | 7.774ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 679 | 692 | 98.12 | |||
V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.724m | 42.009ms | 5 | 5 | 100.00 |
sysrst_ctrl_tl_intg_err | 1.760m | 42.489ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.760m | 42.489ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 6.158m | 1.517s | 45 | 50 | 90.00 |
V3 | TOTAL | 45 | 50 | 90.00 | |||
TOTAL | 914 | 932 | 98.07 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 15 | 15 | 11 | 73.33 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.55 | 99.29 | 96.26 | 100.00 | 95.51 | 98.68 | 99.34 | 93.79 |
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
has 7 failures:
Test sysrst_ctrl_stress_all has 2 failures.
12.sysrst_ctrl_stress_all.4004003138
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 152882845319 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 153085345319 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 153085345319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.sysrst_ctrl_stress_all.3371462545
Line 520, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 6754208023 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 6966708023 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 9406708023 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 9406808349 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
UVM_INFO @ 9436768349 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ultra_low_pwr_vseq
Test sysrst_ctrl_ultra_low_pwr has 2 failures.
17.sysrst_ctrl_ultra_low_pwr.2219346825
Line 513, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2836572916 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 3874072916 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3874072916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.sysrst_ctrl_ultra_low_pwr.1760417427
Line 514, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 5896920237 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 5984420237 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 7534420237 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 7534448758 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
UVM_INFO @ 7546033680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test sysrst_ctrl_stress_all_with_rand_reset has 3 failures.
19.sysrst_ctrl_stress_all_with_rand_reset.3627874378
Line 516, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4294584398 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 4352084398 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 5352084398 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 5352106447 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
UVM_INFO @ 5356616447 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ec_pwr_on_rst_vseq
32.sysrst_ctrl_stress_all_with_rand_reset.2703751686
Line 641, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 282150455381 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 282287955381 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 282807955381 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 282808663607 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
UVM_INFO @ 282848205590 ps: (cip_base_vseq.sv:706) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
... and 1 more failures.
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *
has 4 failures:
12.sysrst_ctrl_ec_pwr_on_rst.1603016371
Line 513, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
UVM_FATAL @ 2950750630 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 2950750630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.sysrst_ctrl_ec_pwr_on_rst.1103042676
Line 513, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
UVM_FATAL @ 2208672323 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 2208672323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
38.sysrst_ctrl_stress_all_with_rand_reset.1470100250
Line 594, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 55408855755 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 55408855755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
has 2 failures:
45.sysrst_ctrl_combo_detect_with_pre_cond.2636357956
Line 536, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 38087403008 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 48404187675 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
UVM_INFO @ 48404271009 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x27
UVM_INFO @ 48917775117 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_INFO @ 48932403008 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= f
86.sysrst_ctrl_combo_detect_with_pre_cond.353012642
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 120085157761 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 120085157761 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 120085157761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])
has 1 failures:
3.sysrst_ctrl_combo_detect_with_pre_cond.1175638335
Line 521, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 14364559856 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 14484622332 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
UVM_INFO @ 14484622332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*])
has 1 failures:
8.sysrst_ctrl_stress_all_with_rand_reset.4034993614
Line 595, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50339440553 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 50359305319 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 8/10
UVM_INFO @ 50362322528 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 9/10
UVM_INFO @ 50362322528 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/390
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*
has 1 failures:
25.sysrst_ctrl_combo_detect_with_pre_cond.3433656233
Line 522, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 15316801070 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
UVM_ERROR @ 15316801070 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 15316801070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-*
has 1 failures:
54.sysrst_ctrl_combo_detect_with_pre_cond.1300122756
Line 526, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 15238343731 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 25426615722 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x17
UVM_INFO @ 25426769568 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x15
UVM_INFO @ 25803692268 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_INFO @ 25803999960 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
has 1 failures:
84.sysrst_ctrl_combo_detect_with_pre_cond.1605203695
Line 524, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 12945172517 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 12945172517 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12945172517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---