Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 44 | 95.65 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 30 | 93.75 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
0 |
1 |
187 |
0 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 43 | 93.48 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 29 | 90.62 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
0 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
0 |
1 |
187 |
0 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 40 | 93.02 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 29 | 90.62 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
0 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
0 |
1 |
187 |
0 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 22 | 22 | 100.00 |
Logical | 22 | 22 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T16,T22,T24 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T22,T24 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T24 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T24 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T22,T24 |
1 | 0 | Covered | T16,T22,T24 |
1 | 1 | Covered | T16,T22,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T22,T24 |
0 | 1 | Covered | T96,T97 |
1 | 0 | Covered | T96,T97 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T22,T24 |
0 | 1 | Covered | T16,T22,T24 |
1 | 0 | Covered | T96,T97 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T16,T22,T24 |
1 | - | Covered | T16,T22,T24 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T17,T18 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T17,T18 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T17,T18 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T17,T18,T23 |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T96,T97 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T17,T18,T23 |
1 | - | Covered | T16,T17,T18 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T96,T97 |
1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T34,T95 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T34,T95 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T34,T95 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T96,T97 |
1 | 0 | Covered | T96,T97 |
1 | 1 | Covered | T28,T34,T95 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T34,T95 |
0 | 1 | Covered | T96,T97 |
1 | 0 | Covered | T96,T97 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T34,T95 |
0 | 1 | Covered | T96,T97 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T28,T34,T95 |
1 | - | Covered | T96,T97 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 16 | 14 | 87.50 |
Logical | 16 | 14 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T40 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Covered | T16,T22,T40 |
1 | 1 | Covered | T19,T20,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T20,T21 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T20,T21 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T19,T20,T21 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T23 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T23 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T23 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T22,T23 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T22,T23 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T22,T23 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T22,T23 |
0 | 1 | Covered | T16,T22,T23 |
1 | 0 | Covered | T96,T97 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T16,T22,T23 |
1 | - | Covered | T16,T22,T23 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 19 | 17 | 89.47 |
Logical | 19 | 17 | 89.47 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T22,T40 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T16,T22,T40 |
1 | 1 | Covered | T16,T22,T40 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Covered | T16,T22,T40 |
1 | 1 | Covered | T19,T20,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T20,T21 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T20,T21 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T19,T20,T21 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 19 | 17 | 89.47 |
Logical | 19 | 17 | 89.47 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T19,T20,T21 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T19,T20,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T20,T21 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T20,T21 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T19,T20,T21 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T16,T17,T18 |
DetectSt |
168 |
Covered |
T16,T17,T18 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T16,T17,T18 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T16,T17,T18 |
DebounceSt->IdleSt |
163 |
Covered |
T16,T22,T23 |
DetectSt->IdleSt |
186 |
Covered |
T96,T97 |
DetectSt->StableSt |
191 |
Covered |
T16,T17,T18 |
IdleSt->DebounceSt |
148 |
Covered |
T16,T17,T18 |
StableSt->IdleSt |
206 |
Covered |
T16,T17,T18 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
22 |
95.65 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T16,T17,T18 |
0 |
1 |
Covered |
T16,T17,T18 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T17,T18 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T17,T18 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T96,T97 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T16,T17,T18 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T16,T22,T23 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T16,T17,T18 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T96,T97 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T16,T17,T18 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T16,T22,T24 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T16,T17,T18 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T17,T18,T23 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T20,T28 |
0 |
1 |
Covered |
T19,T20,T28 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T28 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T19,T20,T28 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T22,T40 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T96,T97 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T19,T20,T28 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T96,T97 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T19,T20,T28 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T96,T97 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T19,T20,T28 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T28,T34,T95 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T19,T20,T21 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T19,T20,T28 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
4594 |
0 |
0 |
T16 |
17445 |
4 |
0 |
0 |
T17 |
1254 |
4 |
0 |
0 |
T18 |
1254 |
4 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
4 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T28 |
506 |
4 |
0 |
0 |
T29 |
479 |
2 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T34 |
0 |
4 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
4 |
0 |
0 |
T95 |
0 |
2 |
0 |
0 |
T98 |
627 |
4 |
0 |
0 |
T99 |
0 |
4 |
0 |
0 |
T101 |
0 |
4 |
0 |
0 |
T102 |
0 |
4 |
0 |
0 |
T103 |
0 |
4 |
0 |
0 |
T104 |
0 |
4 |
0 |
0 |
T105 |
0 |
4 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
4 |
0 |
0 |
T125 |
0 |
4 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
222867 |
0 |
0 |
T16 |
17445 |
170 |
0 |
0 |
T17 |
1254 |
81 |
0 |
0 |
T18 |
1254 |
81 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
170 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
170 |
0 |
0 |
T25 |
0 |
170 |
0 |
0 |
T28 |
506 |
46 |
0 |
0 |
T29 |
479 |
25 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
170 |
0 |
0 |
T34 |
0 |
46 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
81 |
0 |
0 |
T95 |
0 |
21 |
0 |
0 |
T98 |
627 |
81 |
0 |
0 |
T99 |
0 |
81 |
0 |
0 |
T101 |
0 |
81 |
0 |
0 |
T102 |
0 |
81 |
0 |
0 |
T103 |
0 |
81 |
0 |
0 |
T104 |
0 |
81 |
0 |
0 |
T105 |
0 |
81 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
170 |
0 |
0 |
T125 |
0 |
170 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
52826496 |
0 |
0 |
T16 |
453570 |
390377 |
0 |
0 |
T17 |
16302 |
5872 |
0 |
0 |
T18 |
16302 |
5872 |
0 |
0 |
T22 |
453570 |
390377 |
0 |
0 |
T23 |
21242 |
10797 |
0 |
0 |
T24 |
453570 |
390377 |
0 |
0 |
T39 |
10478 |
52 |
0 |
0 |
T40 |
13598 |
3172 |
0 |
0 |
T41 |
12844 |
2418 |
0 |
0 |
T42 |
13078 |
2652 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
10 |
0 |
0 |
T96 |
38605 |
5 |
0 |
0 |
T97 |
0 |
5 |
0 |
0 |
T114 |
2470 |
0 |
0 |
0 |
T115 |
2515 |
0 |
0 |
0 |
T116 |
2615 |
0 |
0 |
0 |
T117 |
3135 |
0 |
0 |
0 |
T118 |
3135 |
0 |
0 |
0 |
T119 |
2070 |
0 |
0 |
0 |
T120 |
87225 |
0 |
0 |
0 |
T121 |
87225 |
0 |
0 |
0 |
T122 |
4085 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
106524 |
0 |
0 |
T16 |
17445 |
152 |
0 |
0 |
T17 |
1254 |
8 |
0 |
0 |
T18 |
1254 |
8 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
152 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
152 |
0 |
0 |
T25 |
0 |
152 |
0 |
0 |
T28 |
506 |
83 |
0 |
0 |
T29 |
479 |
3 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
152 |
0 |
0 |
T34 |
0 |
83 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
8 |
0 |
0 |
T95 |
0 |
80 |
0 |
0 |
T98 |
627 |
8 |
0 |
0 |
T99 |
0 |
8 |
0 |
0 |
T101 |
0 |
8 |
0 |
0 |
T102 |
0 |
8 |
0 |
0 |
T103 |
0 |
8 |
0 |
0 |
T104 |
0 |
8 |
0 |
0 |
T105 |
0 |
8 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
152 |
0 |
0 |
T125 |
0 |
152 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
2143 |
0 |
0 |
T16 |
17445 |
2 |
0 |
0 |
T17 |
1254 |
2 |
0 |
0 |
T18 |
1254 |
2 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
2 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
2 |
0 |
0 |
T25 |
0 |
2 |
0 |
0 |
T28 |
506 |
2 |
0 |
0 |
T29 |
479 |
1 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T98 |
627 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
2 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
2 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
2 |
0 |
0 |
T125 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
50610382 |
0 |
0 |
T16 |
453570 |
370795 |
0 |
0 |
T17 |
16302 |
5700 |
0 |
0 |
T18 |
16302 |
5700 |
0 |
0 |
T22 |
453570 |
370795 |
0 |
0 |
T23 |
21242 |
7520 |
0 |
0 |
T24 |
453570 |
370795 |
0 |
0 |
T39 |
10478 |
52 |
0 |
0 |
T40 |
13598 |
3172 |
0 |
0 |
T41 |
12844 |
2418 |
0 |
0 |
T42 |
13078 |
2652 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
50643559 |
0 |
0 |
T16 |
453570 |
371000 |
0 |
0 |
T17 |
16302 |
5726 |
0 |
0 |
T18 |
16302 |
5726 |
0 |
0 |
T22 |
453570 |
371000 |
0 |
0 |
T23 |
21242 |
7538 |
0 |
0 |
T24 |
453570 |
371000 |
0 |
0 |
T39 |
10478 |
78 |
0 |
0 |
T40 |
13598 |
3198 |
0 |
0 |
T41 |
12844 |
2444 |
0 |
0 |
T42 |
13078 |
2678 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
2419 |
0 |
0 |
T16 |
17445 |
2 |
0 |
0 |
T17 |
1254 |
2 |
0 |
0 |
T18 |
1254 |
2 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
2 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
2 |
0 |
0 |
T25 |
0 |
2 |
0 |
0 |
T28 |
506 |
2 |
0 |
0 |
T29 |
479 |
1 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T98 |
627 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
2 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
2 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
2 |
0 |
0 |
T125 |
0 |
2 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
2175 |
0 |
0 |
T16 |
17445 |
2 |
0 |
0 |
T17 |
1254 |
2 |
0 |
0 |
T18 |
1254 |
2 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
2 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
2 |
0 |
0 |
T25 |
0 |
2 |
0 |
0 |
T28 |
506 |
2 |
0 |
0 |
T29 |
479 |
1 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T98 |
627 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
2 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
2 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
2 |
0 |
0 |
T125 |
0 |
2 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
2143 |
0 |
0 |
T16 |
17445 |
2 |
0 |
0 |
T17 |
1254 |
2 |
0 |
0 |
T18 |
1254 |
2 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
2 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
2 |
0 |
0 |
T25 |
0 |
2 |
0 |
0 |
T28 |
506 |
2 |
0 |
0 |
T29 |
479 |
1 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T98 |
627 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
2 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
2 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
2 |
0 |
0 |
T125 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
2143 |
0 |
0 |
T16 |
17445 |
2 |
0 |
0 |
T17 |
1254 |
2 |
0 |
0 |
T18 |
1254 |
2 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
2 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
2 |
0 |
0 |
T25 |
0 |
2 |
0 |
0 |
T28 |
506 |
2 |
0 |
0 |
T29 |
479 |
1 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T98 |
627 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
2 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
2 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
2 |
0 |
0 |
T125 |
0 |
2 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63017032 |
104026 |
0 |
0 |
T16 |
17445 |
150 |
0 |
0 |
T17 |
1254 |
6 |
0 |
0 |
T18 |
1254 |
6 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T22 |
34890 |
150 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
150 |
0 |
0 |
T25 |
0 |
150 |
0 |
0 |
T28 |
506 |
80 |
0 |
0 |
T29 |
479 |
2 |
0 |
0 |
T30 |
1037 |
0 |
0 |
0 |
T31 |
817 |
0 |
0 |
0 |
T32 |
0 |
150 |
0 |
0 |
T34 |
0 |
80 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T46 |
503 |
0 |
0 |
0 |
T47 |
403 |
0 |
0 |
0 |
T65 |
627 |
6 |
0 |
0 |
T95 |
0 |
78 |
0 |
0 |
T98 |
627 |
6 |
0 |
0 |
T99 |
0 |
6 |
0 |
0 |
T101 |
0 |
6 |
0 |
0 |
T102 |
0 |
6 |
0 |
0 |
T103 |
0 |
6 |
0 |
0 |
T104 |
0 |
6 |
0 |
0 |
T105 |
0 |
6 |
0 |
0 |
T106 |
494 |
0 |
0 |
0 |
T107 |
884 |
0 |
0 |
0 |
T124 |
0 |
150 |
0 |
0 |
T125 |
0 |
150 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21813588 |
25100 |
0 |
0 |
T16 |
157005 |
204 |
0 |
0 |
T17 |
5643 |
9 |
0 |
0 |
T18 |
5643 |
9 |
0 |
0 |
T19 |
0 |
5 |
0 |
0 |
T22 |
157005 |
204 |
0 |
0 |
T23 |
7353 |
13 |
0 |
0 |
T24 |
157005 |
204 |
0 |
0 |
T25 |
0 |
50 |
0 |
0 |
T39 |
3627 |
0 |
0 |
0 |
T40 |
4707 |
48 |
0 |
0 |
T41 |
4446 |
54 |
0 |
0 |
T42 |
4527 |
42 |
0 |
0 |
T65 |
0 |
9 |
0 |
0 |
T66 |
0 |
21 |
0 |
0 |
T67 |
0 |
21 |
0 |
0 |
T126 |
0 |
3 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12118660 |
10166910 |
0 |
0 |
T16 |
87225 |
75125 |
0 |
0 |
T17 |
3135 |
1135 |
0 |
0 |
T18 |
3135 |
1135 |
0 |
0 |
T22 |
87225 |
75125 |
0 |
0 |
T23 |
4085 |
2085 |
0 |
0 |
T24 |
87225 |
75125 |
0 |
0 |
T39 |
2015 |
15 |
0 |
0 |
T40 |
2615 |
615 |
0 |
0 |
T41 |
2470 |
470 |
0 |
0 |
T42 |
2515 |
515 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
41203444 |
34567494 |
0 |
0 |
T16 |
296565 |
255425 |
0 |
0 |
T17 |
10659 |
3859 |
0 |
0 |
T18 |
10659 |
3859 |
0 |
0 |
T22 |
296565 |
255425 |
0 |
0 |
T23 |
13889 |
7089 |
0 |
0 |
T24 |
296565 |
255425 |
0 |
0 |
T39 |
6851 |
51 |
0 |
0 |
T40 |
8891 |
2091 |
0 |
0 |
T41 |
8398 |
1598 |
0 |
0 |
T42 |
8551 |
1751 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21813588 |
18300438 |
0 |
0 |
T16 |
157005 |
135225 |
0 |
0 |
T17 |
5643 |
2043 |
0 |
0 |
T18 |
5643 |
2043 |
0 |
0 |
T22 |
157005 |
135225 |
0 |
0 |
T23 |
7353 |
3753 |
0 |
0 |
T24 |
157005 |
135225 |
0 |
0 |
T39 |
3627 |
27 |
0 |
0 |
T40 |
4707 |
1107 |
0 |
0 |
T41 |
4446 |
846 |
0 |
0 |
T42 |
4527 |
927 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55745836 |
1600 |
0 |
0 |
T16 |
17445 |
2 |
0 |
0 |
T17 |
1254 |
2 |
0 |
0 |
T18 |
1254 |
2 |
0 |
0 |
T22 |
34890 |
2 |
0 |
0 |
T23 |
1634 |
0 |
0 |
0 |
T24 |
34890 |
2 |
0 |
0 |
T25 |
0 |
2 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T39 |
806 |
0 |
0 |
0 |
T40 |
1046 |
0 |
0 |
0 |
T41 |
988 |
0 |
0 |
0 |
T42 |
1006 |
0 |
0 |
0 |
T65 |
627 |
2 |
0 |
0 |
T96 |
7721 |
5 |
0 |
0 |
T98 |
0 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
2 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
2 |
0 |
0 |
T114 |
494 |
0 |
0 |
0 |
T115 |
503 |
0 |
0 |
0 |
T116 |
523 |
0 |
0 |
0 |
T117 |
627 |
0 |
0 |
0 |
T118 |
627 |
0 |
0 |
0 |
T119 |
414 |
0 |
0 |
0 |
T120 |
17445 |
0 |
0 |
0 |
T121 |
17445 |
0 |
0 |
0 |
T122 |
817 |
0 |
0 |
0 |
T124 |
0 |
2 |
0 |
0 |
T125 |
0 |
2 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7271196 |
9600 |
0 |
0 |
T19 |
3111 |
192 |
0 |
0 |
T20 |
3111 |
192 |
0 |
0 |
T21 |
3111 |
192 |
0 |
0 |
T25 |
52335 |
0 |
0 |
0 |
T30 |
3111 |
192 |
0 |
0 |
T37 |
0 |
192 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |
T43 |
1209 |
0 |
0 |
0 |
T44 |
1209 |
0 |
0 |
0 |
T45 |
25209 |
0 |
0 |
0 |
T46 |
1509 |
0 |
0 |
0 |
T47 |
1209 |
0 |
0 |
0 |
T48 |
0 |
192 |
0 |
0 |
T49 |
0 |
192 |
0 |
0 |
T50 |
0 |
192 |
0 |
0 |
T51 |
0 |
192 |
0 |
0 |