Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T16,T22,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T22,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T22,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T22,T24
0	1	Not Covered
1	0	Covered	T96,T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T22,T24
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T22,T24
DetectSt	168	Covered	T16,T22,T24
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T16,T22,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T22,T24
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T22,T24
IdleSt->DebounceSt	148	Covered	T16,T22,T24
StableSt->IdleSt	206	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T22,T24
0	1	Covered	T16,T22,T24
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T22,T24
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T22,T24
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T22,T24
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T22,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T22,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T96,T97
StableSt	-	-	-	-	-	-	0	Covered	T16,T22,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	1906	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2000049	0	0
DisabledNoDetection_A	2423732	2001366	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	1804	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T16	17445	2
T17	627	0
T18	627	0
T22	17445	2
T23	817	0
T24	17445	2
T25	0	2
T32	0	2
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	2
T125	0	2
T127	0	2
T128	0	2
T129	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	4554
T16	17445	90
T17	627	0
T18	627	0
T22	17445	90
T23	817	0
T24	17445	90
T25	0	90
T32	0	90
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	90
T125	0	90
T127	0	90
T128	0	90
T129	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	17445	15014
T17	627	226
T18	627	226
T22	17445	15014
T23	817	416
T24	17445	15014
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	1906
T16	17445	38
T17	627	0
T18	627	0
T22	17445	38
T23	817	0
T24	17445	38
T25	0	38
T32	0	38
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	38
T125	0	38
T127	0	38
T128	0	38
T129	0	38

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2000049
T16	17445	14791
T17	627	226
T18	627	226
T22	17445	14791
T23	817	4
T24	17445	14791
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2001366
T16	17445	14799
T17	627	227
T18	627	227
T22	17445	14799
T23	817	4
T24	17445	14799
T39	403	3
T40	523	123
T41	494	94
T42	503	103

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	1804
T16	17445	36
T17	627	0
T18	627	0
T22	17445	36
T23	817	0
T24	17445	36
T25	0	36
T32	0	36
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	36
T125	0	36
T127	0	36
T128	0	36
T129	0	36

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	417
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T16,T22,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T22,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T96,T97
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T96,T97
1	-	Covered	T16,T22,T24

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T22,T24
DetectSt	168	Covered	T16,T22,T24
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T16,T22,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T22,T24
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T22,T24
IdleSt->DebounceSt	148	Covered	T16,T22,T24
StableSt->IdleSt	206	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T22,T24
0	1	Covered	T16,T22,T24
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T22,T24
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T22,T24
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T22,T24
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T22,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T22,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T22,T24
StableSt	-	-	-	-	-	-	0	Covered	T96,T97
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	60	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2020645	0	0
DisabledNoDetection_A	2423732	2022012	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	8	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	1964	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	50	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T16	17445	2
T17	627	0
T18	627	0
T22	17445	2
T23	817	0
T24	17445	2
T25	0	2
T32	0	2
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	2
T125	0	2
T127	0	2
T128	0	2
T129	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	4554
T16	17445	90
T17	627	0
T18	627	0
T22	17445	90
T23	817	0
T24	17445	90
T25	0	90
T32	0	90
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	90
T125	0	90
T127	0	90
T128	0	90
T129	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	17445	15014
T17	627	226
T18	627	226
T22	17445	15014
T23	817	416
T24	17445	15014
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	60
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2020645
T16	17445	14791
T17	627	226
T18	627	226
T22	17445	14791
T23	817	416
T24	17445	14791
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2022012
T16	17445	14799
T17	627	227
T18	627	227
T22	17445	14799
T23	817	417
T24	17445	14799
T39	403	3
T40	523	123
T41	494	94
T42	503	103

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	8
T96	7721	4
T97	0	4
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	1964
T16	17445	17
T17	627	0
T18	627	0
T22	17445	17
T23	817	1
T24	17445	17
T39	403	0
T40	523	5
T41	494	4
T42	503	3
T66	0	3
T67	0	3
T126	0	1

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	417
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	50
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T16,T22,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T22,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T22,T24
0	1	Not Covered
1	0	Covered	T96,T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T22,T24
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T22,T24
DetectSt	168	Covered	T16,T22,T24
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T16,T22,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T22,T24
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T22,T24
IdleSt->DebounceSt	148	Covered	T16,T22,T24
StableSt->IdleSt	206	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T22,T24
0	1	Covered	T16,T22,T24
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T22,T24
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T22,T24
IdleSt	0	-	-	-	-	-	-	Covered	T16,T22,T40
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T22,T24
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T22,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T22,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T96,T97
StableSt	-	-	-	-	-	-	0	Covered	T16,T22,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	1860	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2020645	0	0
DisabledNoDetection_A	2423732	2022012	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	1758	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T16	17445	2
T17	627	0
T18	627	0
T22	17445	2
T23	817	0
T24	17445	2
T25	0	2
T32	0	2
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	2
T125	0	2
T127	0	2
T128	0	2
T129	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	4554
T16	17445	90
T17	627	0
T18	627	0
T22	17445	90
T23	817	0
T24	17445	90
T25	0	90
T32	0	90
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	90
T125	0	90
T127	0	90
T128	0	90
T129	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	17445	15014
T17	627	226
T18	627	226
T22	17445	15014
T23	817	416
T24	17445	15014
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	1860
T16	17445	37
T17	627	0
T18	627	0
T22	17445	37
T23	817	0
T24	17445	37
T25	0	37
T32	0	37
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	37
T125	0	37
T127	0	37
T128	0	37
T129	0	37

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2020645
T16	17445	14791
T17	627	226
T18	627	226
T22	17445	14791
T23	817	416
T24	17445	14791
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2022012
T16	17445	14799
T17	627	227
T18	627	227
T22	17445	14799
T23	817	417
T24	17445	14799
T39	403	3
T40	523	123
T41	494	94
T42	503	103

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	0
T24	17445	1
T25	0	1
T32	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	1
T125	0	1
T127	0	1
T128	0	1
T129	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	1758
T16	17445	35
T17	627	0
T18	627	0
T22	17445	35
T23	817	0
T24	17445	35
T25	0	35
T32	0	35
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T124	0	35
T125	0	35
T127	0	35
T128	0	35
T129	0	35

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	417
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T22,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T23,T26,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T23,T26,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T23,T26,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T26,T31
1	0	Covered	T16,T22,T40
1	1	Covered	T23,T26,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T26,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T26,T31
0	1	Covered	T23,T26,T31
1	0	Covered	T96,T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T26,T31
1	-	Covered	T23,T26,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T26,T31
DetectSt	168	Covered	T23,T26,T31
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T23,T26,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T26,T31
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T23,T26,T31
IdleSt->DebounceSt	148	Covered	T23,T26,T31
StableSt->IdleSt	206	Covered	T23,T26,T31

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T26,T31
0	1	Covered	T23,T26,T31
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T23,T26,T31
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T26,T31
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T26,T31
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T26,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T23,T26,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T26,T31
StableSt	-	-	-	-	-	-	0	Covered	T23,T26,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	3054	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	3008	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2011297	0	0
DisabledNoDetection_A	2423732	2012664	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	2956	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3098	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	50	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T19	1037	0
T23	817	2
T24	17445	0
T26	0	2
T31	0	2
T35	0	2
T36	0	2
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	2
T131	0	2
T132	0	2
T133	0	2
T134	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	3054
T19	1037	0
T23	817	60
T24	17445	0
T26	0	60
T31	0	60
T35	0	60
T36	0	60
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	60
T131	0	60
T132	0	60
T133	0	60
T134	0	60

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	17445	15016
T17	627	226
T18	627	226
T22	17445	15016
T23	817	414
T24	17445	15016
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	3008
T19	1037	0
T23	817	60
T24	17445	0
T26	0	60
T31	0	60
T35	0	60
T36	0	60
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	60
T131	0	60
T132	0	60
T133	0	60
T134	0	60

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2011297
T16	17445	15016
T17	627	226
T18	627	226
T22	17445	15016
T23	817	4
T24	17445	15016
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2012664
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	4
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	2956
T19	1037	0
T23	817	59
T24	17445	0
T26	0	59
T31	0	59
T35	0	59
T36	0	59
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	59
T131	0	59
T132	0	59
T133	0	59
T134	0	59

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	3098
T16	17445	27
T17	627	0
T18	627	0
T19	0	5
T22	17445	27
T23	817	1
T24	17445	27
T39	403	0
T40	523	5
T41	494	7
T42	503	3
T66	0	3
T67	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	417
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	50
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T22,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T23,T26,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T23,T26,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T23,T26,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T40
1	1	Covered	T23,T26,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T26,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T26,T31
0	1	Covered	T23,T26,T31
1	0	Covered	T96,T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T26,T31
1	-	Covered	T23,T26,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T26,T31
DetectSt	168	Covered	T23,T26,T31
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T23,T26,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T26,T31
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T23,T26,T31
IdleSt->DebounceSt	148	Covered	T23,T26,T31
StableSt->IdleSt	206	Covered	T23,T26,T31

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T26,T31
0	1	Covered	T23,T26,T31
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T23,T26,T31
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T26,T31
IdleSt	0	-	-	-	-	-	-	Covered	T16,T22,T40
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T26,T31
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T26,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T23,T26,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T26,T31
StableSt	-	-	-	-	-	-	0	Covered	T23,T26,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	3054	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	11156	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2000049	0	0
DisabledNoDetection_A	2423732	2001366	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	11104	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	50	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T19	1037	0
T23	817	2
T24	17445	0
T26	0	2
T31	0	2
T35	0	2
T36	0	2
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	2
T131	0	2
T132	0	2
T133	0	2
T134	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	3054
T19	1037	0
T23	817	60
T24	17445	0
T26	0	60
T31	0	60
T35	0	60
T36	0	60
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	60
T131	0	60
T132	0	60
T133	0	60
T134	0	60

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	17445	15016
T17	627	226
T18	627	226
T22	17445	15016
T23	817	414
T24	17445	15016
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	11156
T19	1037	0
T23	817	223
T24	17445	0
T26	0	223
T31	0	223
T35	0	223
T36	0	223
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	223
T131	0	223
T132	0	223
T133	0	223
T134	0	223

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2000049
T16	17445	14791
T17	627	226
T18	627	226
T22	17445	14791
T23	817	4
T24	17445	14791
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2001366
T16	17445	14799
T17	627	227
T18	627	227
T22	17445	14799
T23	817	4
T24	17445	14799
T39	403	3
T40	523	123
T41	494	94
T42	503	103

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	11104
T19	1037	0
T23	817	222
T24	17445	0
T26	0	222
T31	0	222
T35	0	222
T36	0	222
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	222
T131	0	222
T132	0	222
T133	0	222
T134	0	222

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	417
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	50
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T22,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T23,T26,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T23,T26,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T23,T26,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T40
1	1	Covered	T23,T26,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T26,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T26,T31
0	1	Not Covered
1	0	Covered	T96,T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T26,T31
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T26,T31
DetectSt	168	Covered	T23,T26,T31
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T23,T26,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T26,T31
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T23,T26,T31
IdleSt->DebounceSt	148	Covered	T23,T26,T31
StableSt->IdleSt	206	Covered	T96,T97

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T26,T31
0	1	Covered	T23,T26,T31
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T23,T26,T31
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T26,T31
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T26,T31
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T26,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T23,T26,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T96,T97
StableSt	-	-	-	-	-	-	0	Covered	T23,T26,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	3054	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	3158	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2000047	0	0
DisabledNoDetection_A	2423732	2001364	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	3056	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	2972	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T19	1037	0
T23	817	2
T24	17445	0
T26	0	2
T31	0	2
T35	0	2
T36	0	2
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	2
T131	0	2
T132	0	2
T133	0	2
T134	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	3054
T19	1037	0
T23	817	60
T24	17445	0
T26	0	60
T31	0	60
T35	0	60
T36	0	60
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	60
T131	0	60
T132	0	60
T133	0	60
T134	0	60

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	17445	15016
T17	627	226
T18	627	226
T22	17445	15016
T23	817	414
T24	17445	15016
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	3158
T19	1037	0
T23	817	63
T24	17445	0
T26	0	63
T31	0	63
T35	0	63
T36	0	63
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	63
T131	0	63
T132	0	63
T133	0	63
T134	0	63

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2000047
T16	17445	14791
T17	627	226
T18	627	226
T22	17445	14791
T23	817	4
T24	17445	14791
T39	403	2
T40	523	122
T41	494	93
T42	503	102

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2001364
T16	17445	14799
T17	627	227
T18	627	227
T22	17445	14799
T23	817	4
T24	17445	14799
T39	403	3
T40	523	123
T41	494	94
T42	503	103

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T19	1037	0
T23	817	1
T24	17445	0
T26	0	1
T31	0	1
T35	0	1
T36	0	1
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	1
T131	0	1
T132	0	1
T133	0	1
T134	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	3056
T19	1037	0
T23	817	61
T24	17445	0
T26	0	61
T31	0	61
T35	0	61
T36	0	61
T41	494	0
T42	503	0
T43	403	0
T65	627	0
T66	503	0
T67	503	0
T126	414	0
T130	0	61
T131	0	61
T132	0	61
T133	0	61
T134	0	61

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	2972
T16	17445	25
T17	627	0
T18	627	0
T22	17445	25
T23	817	1
T24	17445	25
T25	0	25
T39	403	0
T40	523	6
T41	494	9
T42	503	5
T66	0	5
T67	0	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	17445	15025
T17	627	227
T18	627	227
T22	17445	15025
T23	817	417
T24	17445	15025
T39	403	3
T40	523	123
T41	494	94
T42	503	103

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children