Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.43	100.00	93.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1786691	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1932	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1786691	0	0
T16	488486	4015	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4015	0	0
T23	203230	0	0	0
T24	488486	4015	0	0
T25	0	4015	0	0
T27	0	8163	0	0
T28	0	1071	0	0
T29	0	1086	0	0
T32	0	4015	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T107	0	1113	0	0
T108	0	1113	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1932	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	5	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T107	0	1	0	0
T108	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1091464	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1147	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1091464	0	0
T19	130789	2233	0	0
T20	130789	2233	0	0
T21	130789	2233	0	0
T25	488486	0	0	0
T30	130789	2233	0	0
T37	0	2233	0	0
T38	0	2233	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2233	0	0
T49	0	2233	0	0
T50	0	2233	0	0
T51	0	2233	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1147	0	0
T19	130789	2	0	0
T20	130789	2	0	0
T21	130789	2	0	0
T25	488486	0	0	0
T30	130789	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	971565	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1012	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	971565	0	0
T19	130789	2210	0	0
T20	130789	2210	0	0
T21	130789	2210	0	0
T25	488486	0	0	0
T30	130789	2210	0	0
T37	0	2210	0	0
T38	0	2210	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2210	0	0
T49	0	2210	0	0
T50	0	2210	0	0
T51	0	2210	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1012	0	0
T19	130789	2	0	0
T20	130789	2	0	0
T21	130789	2	0	0
T25	488486	0	0	0
T30	130789	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1116552	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1147	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1116552	0	0
T19	130789	2195	0	0
T20	130789	2195	0	0
T21	130789	2195	0	0
T25	488486	0	0	0
T30	130789	2195	0	0
T37	0	2195	0	0
T38	0	2195	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2195	0	0
T49	0	2195	0	0
T50	0	2195	0	0
T51	0	2195	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1147	0	0
T19	130789	2	0	0
T20	130789	2	0	0
T21	130789	2	0	0
T25	488486	0	0	0
T30	130789	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1193449	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1238	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1193449	0	0
T19	130789	2223	0	0
T20	130789	2223	0	0
T21	130789	2223	0	0
T25	488486	0	0	0
T30	130789	2223	0	0
T37	0	2223	0	0
T38	0	2223	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2223	0	0
T49	0	2223	0	0
T50	0	2223	0	0
T51	0	2223	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1238	0	0
T19	130789	2	0	0
T20	130789	2	0	0
T21	130789	2	0	0
T25	488486	0	0	0
T30	130789	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T92
1	-	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	836775	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	800	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	836775	0	0
T19	130789	1100	0	0
T20	130789	1100	0	0
T21	130789	1100	0	0
T25	488486	0	0	0
T30	130789	1100	0	0
T37	0	1100	0	0
T38	0	1100	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	1100	0	0
T49	0	1100	0	0
T50	0	1100	0	0
T51	0	1100	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	800	0	0
T19	130789	1	0	0
T20	130789	1	0	0
T21	130789	1	0	0
T25	488486	0	0	0
T30	130789	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	112864	0	0	0
T44	112864	0	0	0
T45	235306	0	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T29,T34
1	-	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T16,T22,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T23
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1505038	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1510	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1505038	0	0
T16	488486	6330	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T19	0	1099	0	0
T20	0	1099	0	0
T21	0	1099	0	0
T22	488486	6330	0	0
T23	203230	0	0	0
T24	488486	6330	0	0
T25	0	6330	0	0
T27	0	7706	0	0
T28	0	782	0	0
T29	0	717	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1510	0	0
T16	488486	7	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	488486	7	0	0
T23	203230	0	0	0
T24	488486	7	0	0
T25	0	7	0	0
T27	0	8	0	0
T30	0	1	0	0
T32	0	7	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T41

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T22,T41

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T41

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T22,T41

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T41
0	0	1	Covered	T16,T22,T41
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T41
0	0	1	Covered	T16,T22,T41
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	3035455	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	3105	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	3035455	0	0
T16	488486	19796	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	19796	0	0
T23	203230	0	0	0
T24	488486	19796	0	0
T25	0	19796	0	0
T32	0	19796	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	19782	0	0
T42	140863	0	0	0
T106	0	19782	0	0
T109	0	19782	0	0
T110	0	19782	0	0
T111	0	19782	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	3105	0	0
T16	488486	20	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	20	0	0
T23	203230	0	0	0
T24	488486	20	0	0
T25	0	20	0	0
T32	0	20	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	20	0	0
T42	140863	0	0	0
T106	0	20	0	0
T109	0	20	0	0
T110	0	20	0	0
T111	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T40

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T40

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T40
0	0	1	Covered	T16,T22,T40
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T40
0	0	1	Covered	T16,T22,T40
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	5023070	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	5170	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	5023070	0	0
T16	488486	39828	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	39828	0	0
T23	203230	0	0	0
T24	488486	39828	0	0
T25	0	39828	0	0
T39	112864	0	0	0
T40	146706	19492	0	0
T41	138342	1113	0	0
T42	140863	19506	0	0
T66	0	19506	0	0
T67	0	19506	0	0
T106	0	1113	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	5170	0	0
T16	488486	41	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	41	0	0
T23	203230	0	0	0
T24	488486	41	0	0
T25	0	41	0	0
T39	112864	0	0	0
T40	146706	20	0	0
T41	138342	1	0	0
T42	140863	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T106	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T40

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T40

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T40
0	0	1	Covered	T16,T22,T40
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T40
0	0	1	Covered	T16,T22,T40
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	5867210	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	5967	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	5867210	0	0
T16	488486	45394	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	45394	0	0
T23	203230	0	0	0
T24	488486	45394	0	0
T25	0	45394	0	0
T39	112864	0	0	0
T40	146706	19754	0	0
T41	138342	1115	0	0
T42	140863	19804	0	0
T66	0	19804	0	0
T67	0	19804	0	0
T108	0	1115	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	5967	0	0
T16	488486	46	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	46	0	0
T23	203230	0	0	0
T24	488486	46	0	0
T25	0	46	0	0
T39	112864	0	0	0
T40	146706	20	0	0
T41	138342	1	0	0
T42	140863	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T108	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T40

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T40

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T40
0	0	1	Covered	T16,T22,T40
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T40
0	0	1	Covered	T16,T22,T40
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	4794510	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	4925	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	4794510	0	0
T16	488486	39295	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	39295	0	0
T23	203230	0	0	0
T24	488486	39295	0	0
T25	0	39295	0	0
T32	0	39295	0	0
T39	112864	0	0	0
T40	146706	19618	0	0
T41	138342	0	0	0
T42	140863	19644	0	0
T46	0	19644	0	0
T66	0	19644	0	0
T67	0	19644	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	4925	0	0
T16	488486	40	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	40	0	0
T23	203230	0	0	0
T24	488486	40	0	0
T25	0	40	0	0
T32	0	40	0	0
T39	112864	0	0	0
T40	146706	20	0	0
T41	138342	0	0	0
T42	140863	20	0	0
T46	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T23
1	1	Covered	T16,T22,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T23
1	1	Covered	T16,T22,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T23
0	0	1	Covered	T16,T22,T23
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T23
0	0	1	Covered	T16,T22,T23
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1219877	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1246	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1219877	0	0
T16	488486	1107	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	1107	0	0
T23	203230	1115	0	0
T24	488486	1107	0	0
T25	0	1107	0	0
T26	0	1115	0	0
T31	0	1115	0	0
T32	0	1107	0	0
T35	0	1115	0	0
T36	0	1115	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1246	0	0
T16	488486	1	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	1	0	0
T23	203230	1	0	0
T24	488486	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T23
1	1	Covered	T16,T22,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T23
1	1	Covered	T16,T22,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T23
0	0	1	Covered	T16,T22,T23
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T23
0	0	1	Covered	T16,T22,T23
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1783846	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1924	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1783846	0	0
T16	488486	5078	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5078	0	0
T23	203230	1113	0	0
T24	488486	5078	0	0
T25	0	5078	0	0
T26	0	1113	0	0
T27	0	8109	0	0
T28	0	1059	0	0
T29	0	1081	0	0
T31	0	1113	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1924	0	0
T16	488486	6	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	6	0	0
T23	203230	1	0	0
T24	488486	6	0	0
T25	0	6	0	0
T26	0	1	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T17,T18,T65

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T17,T18,T65

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T17,T18,T65
0	0	1	Covered	T17,T18,T65
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T17,T18,T65
0	0	1	Covered	T17,T18,T65
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1193645	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1259	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1193645	0	0
T17	175783	4731	0	0
T18	175783	4731	0	0
T22	488486	0	0	0
T23	203230	0	0	0
T24	488486	0	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T65	175783	4731	0	0
T98	0	4731	0	0
T99	0	4731	0	0
T101	0	4731	0	0
T102	0	4731	0	0
T103	0	4731	0	0
T104	0	4731	0	0
T105	0	4731	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1259	0	0
T17	175783	5	0	0
T18	175783	5	0	0
T22	488486	0	0	0
T23	203230	0	0	0
T24	488486	0	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T65	175783	5	0	0
T98	0	5	0	0
T99	0	5	0	0
T101	0	5	0	0
T102	0	5	0	0
T103	0	5	0	0
T104	0	5	0	0
T105	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T17,T18,T65

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T17,T18,T65

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T17,T18,T65
0	0	1	Covered	T17,T18,T65
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T17,T18,T65
0	0	1	Covered	T17,T18,T65
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1143333	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1192	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1143333	0	0
T17	175783	3042	0	0
T18	175783	3042	0	0
T22	488486	0	0	0
T23	203230	0	0	0
T24	488486	0	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T65	175783	3042	0	0
T98	0	3042	0	0
T99	0	3042	0	0
T101	0	3042	0	0
T102	0	3042	0	0
T103	0	3042	0	0
T104	0	3042	0	0
T105	0	3042	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1192	0	0
T17	175783	3	0	0
T18	175783	3	0	0
T22	488486	0	0	0
T23	203230	0	0	0
T24	488486	0	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T65	175783	3	0	0
T98	0	3	0	0
T99	0	3	0	0
T101	0	3	0	0
T102	0	3	0	0
T103	0	3	0	0
T104	0	3	0	0
T105	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T28,T34,T95

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T28,T34,T95
1	1	Covered	T28,T34,T95

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T28,T34,T95

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T34,T95
1	1	Covered	T28,T34,T95

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T28,T34,T95
0	0	1	Covered	T28,T34,T95
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T28,T34,T95
0	0	1	Covered	T28,T34,T95
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	998106	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1052	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	998106	0	0
T1	0	16281	0	0
T2	0	906	0	0
T21	130789	0	0	0
T28	141936	1115	0	0
T29	134330	0	0	0
T30	130789	0	0	0
T31	203230	0	0	0
T34	0	1115	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T92	0	12436	0	0
T95	0	1115	0	0
T96	0	10508	0	0
T97	0	10508	0	0
T98	175783	0	0	0
T106	138342	0	0	0
T107	247808	0	0	0
T112	0	1115	0	0
T113	0	1115	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1052	0	0
T1	0	19	0	0
T11	0	13	0	0
T21	130789	0	0	0
T28	141936	1	0	0
T29	134330	0	0	0
T30	130789	0	0	0
T31	203230	0	0	0
T34	0	1	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T92	0	13	0	0
T95	0	1	0	0
T96	0	11	0	0
T97	0	11	0	0
T98	175783	0	0	0
T106	138342	0	0	0
T107	247808	0	0	0
T112	0	1	0	0
T113	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	918274	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	982	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	918274	0	0
T1	0	17147	0	0
T2	0	825	0	0
T3	0	825	0	0
T5	0	17147	0	0
T6	0	825	0	0
T11	0	8287	0	0
T15	0	1829	0	0
T92	0	8287	0	0
T96	215076	10492	0	0
T97	0	10492	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	982	0	0
T1	0	20	0	0
T5	0	20	0	0
T7	0	20	0	0
T11	0	9	0	0
T15	0	2	0	0
T68	0	2	0	0
T69	0	9	0	0
T92	0	9	0	0
T96	215076	11	0	0
T97	0	11	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1074469	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1127	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1074469	0	0
T1	0	17599	0	0
T2	0	699	0	0
T3	0	699	0	0
T5	0	17599	0	0
T6	0	699	0	0
T11	0	15439	0	0
T15	0	1910	0	0
T92	0	15439	0	0
T96	215076	10517	0	0
T97	0	10517	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1127	0	0
T1	0	20	0	0
T5	0	20	0	0
T7	0	20	0	0
T11	0	16	0	0
T15	0	2	0	0
T68	0	2	0	0
T69	0	16	0	0
T92	0	16	0	0
T96	215076	11	0	0
T97	0	11	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	956817	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1012	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	956817	0	0
T1	0	17326	0	0
T2	0	747	0	0
T3	0	747	0	0
T5	0	17326	0	0
T6	0	747	0	0
T11	0	9391	0	0
T15	0	1936	0	0
T92	0	9391	0	0
T96	215076	10521	0	0
T97	0	10521	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1012	0	0
T1	0	20	0	0
T5	0	20	0	0
T7	0	20	0	0
T11	0	10	0	0
T15	0	2	0	0
T68	0	2	0	0
T69	0	10	0	0
T92	0	10	0	0
T96	215076	11	0	0
T97	0	11	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T28,T34,T95

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T28,T34,T95
1	1	Covered	T28,T34,T95

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T28,T34,T95

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T34,T95
1	1	Covered	T28,T34,T95

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T28,T34,T95
0	0	1	Covered	T28,T34,T95
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T28,T34,T95
0	0	1	Covered	T28,T34,T95
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	967832	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1023	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	967832	0	0
T1	0	17222	0	0
T2	0	803	0	0
T21	130789	0	0	0
T28	141936	1113	0	0
T29	134330	0	0	0
T30	130789	0	0	0
T31	203230	0	0	0
T34	0	1113	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T92	0	10502	0	0
T95	0	1113	0	0
T96	0	8196	0	0
T97	0	8196	0	0
T98	175783	0	0	0
T106	138342	0	0	0
T107	247808	0	0	0
T112	0	1113	0	0
T113	0	1113	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1023	0	0
T1	0	20	0	0
T11	0	11	0	0
T21	130789	0	0	0
T28	141936	1	0	0
T29	134330	0	0	0
T30	130789	0	0	0
T31	203230	0	0	0
T34	0	1	0	0
T46	140863	0	0	0
T47	112864	0	0	0
T92	0	11	0	0
T95	0	1	0	0
T96	0	9	0	0
T97	0	9	0	0
T98	175783	0	0	0
T106	138342	0	0	0
T107	247808	0	0	0
T112	0	1	0	0
T113	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1055937	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1123	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1055937	0	0
T1	0	16597	0	0
T2	0	834	0	0
T3	0	834	0	0
T5	0	16597	0	0
T6	0	834	0	0
T11	0	15546	0	0
T15	0	1962	0	0
T92	0	15546	0	0
T96	215076	8191	0	0
T97	0	8191	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1123	0	0
T1	0	20	0	0
T5	0	20	0	0
T7	0	20	0	0
T11	0	16	0	0
T15	0	2	0	0
T68	0	2	0	0
T69	0	16	0	0
T92	0	16	0	0
T96	215076	9	0	0
T97	0	9	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1068121	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1118	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1068121	0	0
T1	0	17602	0	0
T2	0	783	0	0
T3	0	783	0	0
T5	0	17602	0	0
T6	0	783	0	0
T11	0	15505	0	0
T15	0	1983	0	0
T92	0	15505	0	0
T96	215076	8218	0	0
T97	0	8218	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1118	0	0
T1	0	20	0	0
T5	0	20	0	0
T7	0	20	0	0
T11	0	16	0	0
T15	0	2	0	0
T68	0	2	0	0
T69	0	16	0	0
T92	0	16	0	0
T96	215076	9	0	0
T97	0	9	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T96,T97,T1
0	0	1	Covered	T96,T97,T1
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	990005	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1048	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	990005	0	0
T1	0	17303	0	0
T2	0	642	0	0
T3	0	642	0	0
T5	0	17303	0	0
T6	0	642	0	0
T11	0	11368	0	0
T15	0	2059	0	0
T92	0	11368	0	0
T96	215076	8225	0	0
T97	0	8225	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1048	0	0
T1	0	20	0	0
T5	0	20	0	0
T7	0	20	0	0
T11	0	12	0	0
T15	0	2	0	0
T68	0	2	0	0
T69	0	12	0	0
T92	0	12	0	0
T96	215076	9	0	0
T97	0	9	0	0
T114	138342	0	0	0
T115	140863	0	0	0
T116	146706	0	0	0
T117	175783	0	0	0
T118	175783	0	0	0
T119	116176	0	0	0
T120	488486	0	0	0
T121	488486	0	0	0
T122	203230	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1697673	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1777	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1697673	0	0
T16	488486	4456	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4456	0	0
T23	203230	0	0	0
T24	488486	4456	0	0
T25	0	4456	0	0
T27	0	8932	0	0
T28	0	1090	0	0
T29	0	1113	0	0
T32	0	4456	0	0
T33	0	8932	0	0
T34	0	1090	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1777	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	5	0	0
T33	0	9	0	0
T34	0	1	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1515794	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1597	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1515794	0	0
T16	488486	4415	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4415	0	0
T23	203230	0	0	0
T24	488486	4415	0	0
T25	0	4415	0	0
T27	0	8870	0	0
T32	0	4415	0	0
T33	0	8870	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8870	0	0
T123	0	8870	0	0
T124	0	4415	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1597	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1642757	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1747	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1642757	0	0
T16	488486	4380	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4380	0	0
T23	203230	0	0	0
T24	488486	4380	0	0
T25	0	4380	0	0
T27	0	8806	0	0
T32	0	4380	0	0
T33	0	8806	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8806	0	0
T123	0	8806	0	0
T124	0	4380	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1747	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1577726	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1692	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1577726	0	0
T16	488486	4340	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4340	0	0
T23	203230	0	0	0
T24	488486	4340	0	0
T25	0	4340	0	0
T27	0	8728	0	0
T32	0	4340	0	0
T33	0	8728	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8728	0	0
T123	0	8728	0	0
T124	0	4340	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1692	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1858413	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1968	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1858413	0	0
T16	488486	4303	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4303	0	0
T23	203230	0	0	0
T24	488486	4303	0	0
T25	0	4303	0	0
T27	0	8660	0	0
T28	0	1086	0	0
T29	0	1102	0	0
T32	0	4303	0	0
T33	0	8660	0	0
T34	0	1086	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1968	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	5	0	0
T33	0	9	0	0
T34	0	1	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1644517	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1763	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1644517	0	0
T16	488486	4262	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4262	0	0
T23	203230	0	0	0
T24	488486	4262	0	0
T25	0	4262	0	0
T27	0	8592	0	0
T32	0	4262	0	0
T33	0	8592	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8592	0	0
T123	0	8592	0	0
T124	0	4262	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1763	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1622780	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1738	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1622780	0	0
T16	488486	4216	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4216	0	0
T23	203230	0	0	0
T24	488486	4216	0	0
T25	0	4216	0	0
T27	0	8528	0	0
T32	0	4216	0	0
T33	0	8528	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8528	0	0
T123	0	8528	0	0
T124	0	4216	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1738	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1697927	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1813	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1697927	0	0
T16	488486	4188	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4188	0	0
T23	203230	0	0	0
T24	488486	4188	0	0
T25	0	4188	0	0
T27	0	8470	0	0
T32	0	4188	0	0
T33	0	8470	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8470	0	0
T123	0	8470	0	0
T124	0	4188	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1813	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1653905	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1773	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1653905	0	0
T16	488486	4150	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4150	0	0
T23	203230	0	0	0
T24	488486	4150	0	0
T25	0	4150	0	0
T27	0	8413	0	0
T28	0	1081	0	0
T29	0	1090	0	0
T32	0	4150	0	0
T33	0	8413	0	0
T34	0	1081	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1773	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	5	0	0
T33	0	9	0	0
T34	0	1	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1532754	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1663	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1532754	0	0
T16	488486	4110	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4110	0	0
T23	203230	0	0	0
T24	488486	4110	0	0
T25	0	4110	0	0
T27	0	8347	0	0
T32	0	4110	0	0
T33	0	8347	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8347	0	0
T123	0	8347	0	0
T124	0	4110	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1663	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1483275	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1603	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1483275	0	0
T16	488486	4089	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4089	0	0
T23	203230	0	0	0
T24	488486	4089	0	0
T25	0	4089	0	0
T27	0	8295	0	0
T32	0	4089	0	0
T33	0	8295	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8295	0	0
T123	0	8295	0	0
T124	0	4089	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1603	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1543220	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1683	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1543220	0	0
T16	488486	4059	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	4059	0	0
T23	203230	0	0	0
T24	488486	4059	0	0
T25	0	4059	0	0
T27	0	8236	0	0
T32	0	4059	0	0
T33	0	8236	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	8236	0	0
T123	0	8236	0	0
T124	0	4059	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1683	0	0
T16	488486	5	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	5	0	0
T23	203230	0	0	0
T24	488486	5	0	0
T25	0	5	0	0
T27	0	9	0	0
T32	0	5	0	0
T33	0	9	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0
T100	0	9	0	0
T123	0	9	0	0
T124	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T22,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T16,T22,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T17,T18
0	1	-	Covered	T16,T22,T24
0	0	1	Covered	T16,T22,T24
0	0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	754515696	1344425	0	0
DstReqKnown_A	2727417	2106687	0	0
SrcAckBusyChk_A	754515696	1410	0	0
SrcBusyKnown_A	754515696	753291408	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1344425	0	0
T16	488486	6262	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	6262	0	0
T23	203230	0	0	0
T24	488486	6262	0	0
T25	0	6262	0	0
T27	0	7644	0	0
T28	0	1106	0	0
T29	0	1112	0	0
T32	0	6262	0	0
T33	0	7644	0	0
T34	0	1106	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2727417	2106687	0	0
T16	17445	15025	0	0
T17	627	227	0	0
T18	627	227	0	0
T22	17445	15025	0	0
T23	817	417	0	0
T24	17445	15025	0	0
T39	403	3	0	0
T40	523	123	0	0
T41	494	94	0	0
T42	503	103	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	1410	0	0
T16	488486	7	0	0
T17	175783	0	0	0
T18	175783	0	0	0
T22	488486	7	0	0
T23	203230	0	0	0
T24	488486	7	0	0
T25	0	7	0	0
T27	0	8	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	7	0	0
T33	0	8	0	0
T34	0	1	0	0
T39	112864	0	0	0
T40	146706	0	0	0
T41	138342	0	0	0
T42	140863	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	754515696	753291408	0	0
T16	488486	487880	0	0
T17	175783	175699	0	0
T18	175783	175699	0	0
T22	488486	487880	0	0
T23	203230	203146	0	0
T24	488486	487880	0	0
T39	112864	112780	0	0
T40	146706	146622	0	0
T41	138342	138258	0	0
T42	140863	140779	0	0