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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
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T556 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.60876353155118376881452798265493629590490560883377817530371461721967021656460 Oct 29 12:30:17 PM PDT 23 Oct 29 12:30:23 PM PDT 23 3138968703 ps
T557 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.108789235879764348410482114351542133739171850029996759434108455354880964151611 Oct 29 12:28:23 PM PDT 23 Oct 29 12:28:29 PM PDT 23 3138968703 ps
T558 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.77231866170931123662382028380088700530872742458435446962036830178123465486907 Oct 29 12:27:53 PM PDT 23 Oct 29 12:28:05 PM PDT 23 4425119128 ps
T559 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.107887155021097282961677555604612375907648170504174013818063136971596459285195 Oct 29 12:28:32 PM PDT 23 Oct 29 12:31:36 PM PDT 23 118289458206 ps
T560 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.62780380978113645872855778580903759540612122431404771574659483508710398741174 Oct 29 12:29:30 PM PDT 23 Oct 29 12:29:35 PM PDT 23 2074566504 ps
T561 /workspace/coverage/default/31.sysrst_ctrl_alert_test.5790392177924089723862831854330446732995248103854238776682668209567292133117 Oct 29 12:29:49 PM PDT 23 Oct 29 12:29:53 PM PDT 23 2015424120 ps
T562 /workspace/coverage/default/3.sysrst_ctrl_alert_test.74503326663220159430581614303947346902990431923891770257082405206614969881702 Oct 29 12:28:04 PM PDT 23 Oct 29 12:28:08 PM PDT 23 2015424120 ps
T563 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.30606221653715843138902668948738603627628361996993496955602606019903723097915 Oct 29 12:27:55 PM PDT 23 Oct 29 12:28:02 PM PDT 23 5189470156 ps
T564 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.87065324903770069379485197026731867024742392980087529485839502976604288881240 Oct 29 12:30:12 PM PDT 23 Oct 29 12:30:17 PM PDT 23 2515402263 ps
T565 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.22564780330830350275089295816222480877257750718443585244334743416883239286029 Oct 29 12:30:26 PM PDT 23 Oct 29 12:30:32 PM PDT 23 3138968703 ps
T566 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.30454529184490815010756217553662298965439323318816895220974267594209220862947 Oct 29 12:28:15 PM PDT 23 Oct 29 12:31:19 PM PDT 23 118289458206 ps
T567 /workspace/coverage/default/21.sysrst_ctrl_smoke.17611731207433198161644166316668251213294074678606260960336260547642835002582 Oct 29 12:29:14 PM PDT 23 Oct 29 12:29:18 PM PDT 23 2116887594 ps
T568 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.24868953827735916966721795964664162410495797707565247462995037405546437574245 Oct 29 12:28:06 PM PDT 23 Oct 29 12:28:12 PM PDT 23 2515402263 ps
T569 /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.114654705537793332296459020803886995029025524880622145496538953852139542720788 Oct 29 12:28:47 PM PDT 23 Oct 29 12:28:53 PM PDT 23 2619740714 ps
T570 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.5258640187671811189656156748958726517642814736128584347660064206005854297710 Oct 29 12:30:51 PM PDT 23 Oct 29 12:30:56 PM PDT 23 2515402263 ps
T571 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.107636891090226478448834016322901235503695283346354380096738946055615868414674 Oct 29 12:29:10 PM PDT 23 Oct 29 12:29:15 PM PDT 23 2515402263 ps
T572 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.53827034771326420903892473426045787015745491547807964334102374297872794514896 Oct 29 12:29:51 PM PDT 23 Oct 29 12:29:58 PM PDT 23 2470384766 ps
T573 /workspace/coverage/default/36.sysrst_ctrl_stress_all.75411780384809932281410348299959991287659924522743873902251442013156549733595 Oct 29 12:30:14 PM PDT 23 Oct 29 12:32:31 PM PDT 23 87228974549 ps
T574 /workspace/coverage/default/30.sysrst_ctrl_smoke.2727975008353291982998924510422670616073388576179163677340102698377219167396 Oct 29 12:29:48 PM PDT 23 Oct 29 12:29:53 PM PDT 23 2116887594 ps
T575 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.62207517057087220016168424254780402064661494895310356837045824549461973000740 Oct 29 12:31:07 PM PDT 23 Oct 29 12:31:15 PM PDT 23 4425119128 ps
T576 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.810989240405103020622014281847341027288819244828344830731119277506965134597 Oct 29 12:28:39 PM PDT 23 Oct 29 12:28:44 PM PDT 23 2470384766 ps
T577 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.112942844213358417409065206693190794603123086649923835034899452606587742551514 Oct 29 12:28:26 PM PDT 23 Oct 29 12:28:32 PM PDT 23 2515402263 ps
T578 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.59372801265243582410968501005396671255774162101038156379324072726166022817366 Oct 29 12:28:13 PM PDT 23 Oct 29 12:28:19 PM PDT 23 2515402263 ps
T579 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.80102739228970647730344277380535083236378651104853571367028700738028858726999 Oct 29 12:27:59 PM PDT 23 Oct 29 12:28:06 PM PDT 23 3138968703 ps
T580 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.31434946104300911698410026511372721615951242039202475563852022763604035704634 Oct 29 12:30:35 PM PDT 23 Oct 29 12:30:42 PM PDT 23 4089103959 ps
T581 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.76595186488920328920377939688799095270185064468903075045404749507526555336997 Oct 29 12:29:11 PM PDT 23 Oct 29 12:29:18 PM PDT 23 4089103959 ps
T582 /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.31648296437672304024940219501233181398844976018159292946730132794854274443405 Oct 29 12:27:57 PM PDT 23 Oct 29 12:28:02 PM PDT 23 2470384766 ps
T583 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.10548380134708162282043268019433314904208173303235103842789757573935543584020 Oct 29 12:28:33 PM PDT 23 Oct 29 12:28:38 PM PDT 23 3138968703 ps
T584 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.7262556779404047209473733670547438942554634428096282469156681803797893495728 Oct 29 12:28:34 PM PDT 23 Oct 29 12:28:39 PM PDT 23 2619740714 ps
T585 /workspace/coverage/default/46.sysrst_ctrl_stress_all.76633368585333415428309535550153147092209366547515073271678557734541947746072 Oct 29 12:30:50 PM PDT 23 Oct 29 12:33:09 PM PDT 23 87228974549 ps
T586 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.15351167947842817820907885608142475163414944040826171855798277763455401221316 Oct 29 12:28:04 PM PDT 23 Oct 29 12:28:10 PM PDT 23 2470384766 ps
T587 /workspace/coverage/default/47.sysrst_ctrl_alert_test.12482497854106616238523105775207654364684076102053951404743852575434354558060 Oct 29 12:30:47 PM PDT 23 Oct 29 12:30:51 PM PDT 23 2015424120 ps
T588 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.30834984629946701371620721456300204022358332044057308490165748937339319894395 Oct 29 12:30:04 PM PDT 23 Oct 29 12:30:12 PM PDT 23 4425119128 ps
T589 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.40151708456558209818887848071028759943081147330139039118377115658532083068020 Oct 29 12:29:24 PM PDT 23 Oct 29 12:29:29 PM PDT 23 2619740714 ps
T590 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.91197473908997558138721666479539281906852139769370279792609652592891353606837 Oct 29 12:29:27 PM PDT 23 Oct 29 12:29:38 PM PDT 23 4425119128 ps
T591 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.64480847594257618193804488893481734009512334904661151248992483176654922418212 Oct 29 12:29:23 PM PDT 23 Oct 29 12:29:29 PM PDT 23 3138968703 ps
T592 /workspace/coverage/default/37.sysrst_ctrl_smoke.2569018058192851754055081178645563379967300837535011874281125634863187389972 Oct 29 12:30:13 PM PDT 23 Oct 29 12:30:17 PM PDT 23 2116887594 ps
T593 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.107318347299027694435483432574939560456995430852023670677562280454213171556290 Oct 29 12:30:50 PM PDT 23 Oct 29 12:30:58 PM PDT 23 4425119128 ps
T594 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.98024462869616495981016019336385010122176223111273329388889317143117724746806 Oct 29 12:29:56 PM PDT 23 Oct 29 12:32:59 PM PDT 23 118289458206 ps
T595 /workspace/coverage/default/2.sysrst_ctrl_smoke.110801215914895016989845609031754011180550004438933313412379585813285738458686 Oct 29 12:27:50 PM PDT 23 Oct 29 12:27:55 PM PDT 23 2116887594 ps
T596 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.49759494329554234103514354662763468596180942207724836018132048833829179320519 Oct 29 12:29:52 PM PDT 23 Oct 29 12:29:58 PM PDT 23 2619740714 ps
T597 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.60574123995877323221123596063203588369925001137758744958728665275034982052033 Oct 29 12:30:51 PM PDT 23 Oct 29 12:30:56 PM PDT 23 2619740714 ps
T598 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.94524642611731196968112556743146098953890873931226448571363106742919721181733 Oct 29 12:29:04 PM PDT 23 Oct 29 12:29:09 PM PDT 23 2470384766 ps
T599 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.71037286839186856276508276112872497370978619360153470965558411908855461423400 Oct 29 12:28:39 PM PDT 23 Oct 29 12:28:44 PM PDT 23 5189470156 ps
T600 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.62048024651517668586263435271270545740094114213806972172472279992813497662533 Oct 29 12:28:13 PM PDT 23 Oct 29 12:28:19 PM PDT 23 5189470156 ps
T601 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.100630494150462742880076956030092621953494372010897143075752395759576545141548 Oct 29 12:29:53 PM PDT 23 Oct 29 12:30:00 PM PDT 23 4089103959 ps
T602 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.109114556143325136088900405079049342288336000478077906320958673083074702900926 Oct 29 12:28:01 PM PDT 23 Oct 29 12:28:07 PM PDT 23 2619740714 ps
T603 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.96840841918043583192851224764735656095613724723760227591033123941919073184918 Oct 29 12:30:18 PM PDT 23 Oct 29 12:30:26 PM PDT 23 4425119128 ps
T604 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.26148840207907767036759392881734412657571020161782094708644374327563332225095 Oct 29 12:30:03 PM PDT 23 Oct 29 12:30:09 PM PDT 23 3138968703 ps
T605 /workspace/coverage/default/29.sysrst_ctrl_stress_all.15458618050165499472137277299993413557595013270850288787474902941782192115649 Oct 29 12:29:45 PM PDT 23 Oct 29 12:32:02 PM PDT 23 87228974549 ps
T606 /workspace/coverage/default/40.sysrst_ctrl_stress_all.78357899998193744087161136646720717832608765125205605758525044042980078913513 Oct 29 12:30:29 PM PDT 23 Oct 29 12:32:48 PM PDT 23 87228974549 ps
T607 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.97239242661462691178282567114684599213121525447725203190633144569571798924686 Oct 29 12:30:25 PM PDT 23 Oct 29 12:30:30 PM PDT 23 2470384766 ps
T608 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.76548210047975946006791892125081359605637095896433449772600944359444873561407 Oct 29 12:29:35 PM PDT 23 Oct 29 12:32:42 PM PDT 23 118289458206 ps
T609 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.32437241738352864744732081928301277814405262126123072313832779167413763412934 Oct 29 12:30:50 PM PDT 23 Oct 29 12:30:57 PM PDT 23 4089103959 ps
T146 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.44413734613996707068498353335960952804232726748543372761452983987879754231249 Oct 29 12:29:02 PM PDT 23 Oct 29 12:30:08 PM PDT 23 42018621949 ps
T610 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.88319780807526759809426158731806388159470201291315341574996553436619477230171 Oct 29 12:30:48 PM PDT 23 Oct 29 12:30:53 PM PDT 23 2515402263 ps
T611 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.4582651617903251341731056572167123207351681120283754608169117379171705118014 Oct 29 12:30:29 PM PDT 23 Oct 29 12:30:35 PM PDT 23 2074566504 ps
T612 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.83324919844171759860794307778795181855161667917985712631656536813045656216379 Oct 29 12:29:54 PM PDT 23 Oct 29 12:30:00 PM PDT 23 3138968703 ps
T613 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.55995022352749872651116683938541267886282664211179584566087558038612201778255 Oct 29 12:30:16 PM PDT 23 Oct 29 12:30:21 PM PDT 23 2619740714 ps
T614 /workspace/coverage/default/28.sysrst_ctrl_stress_all.111940179497105447728656508383945290512384366106790480997862352588257809668841 Oct 29 12:29:37 PM PDT 23 Oct 29 12:31:53 PM PDT 23 87228974549 ps
T615 /workspace/coverage/default/24.sysrst_ctrl_alert_test.29725960584941025594163108495843734187769654414051665072094401187942029619437 Oct 29 12:29:31 PM PDT 23 Oct 29 12:29:36 PM PDT 23 2015424120 ps
T616 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.115769366834169972436666056435857577524298962695173101110267888910858321611484 Oct 29 12:29:54 PM PDT 23 Oct 29 12:32:58 PM PDT 23 118289458206 ps
T617 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2109843453012328031247838114235664379257089566036353685016647697007373113127 Oct 29 12:29:23 PM PDT 23 Oct 29 12:29:29 PM PDT 23 5189470156 ps
T618 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.9921422731705907115319110061309041568866872688608989645085005343315243320786 Oct 29 12:29:12 PM PDT 23 Oct 29 12:29:20 PM PDT 23 4425119128 ps
T619 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.23190909670855724063171086239955225940349720041728797978170147034907386820832 Oct 29 12:30:18 PM PDT 23 Oct 29 12:30:23 PM PDT 23 5189470156 ps
T620 /workspace/coverage/default/32.sysrst_ctrl_alert_test.97944468346544324472328367718305841594445962462270241809529995840374388946096 Oct 29 12:29:55 PM PDT 23 Oct 29 12:29:59 PM PDT 23 2015424120 ps
T621 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.34550703833747579591512490013343599021932506118854371655119330408446434336869 Oct 29 12:30:38 PM PDT 23 Oct 29 12:30:43 PM PDT 23 2470384766 ps
T622 /workspace/coverage/default/42.sysrst_ctrl_smoke.27832796498418219383532511270405985987136869770084539795786997604345915869513 Oct 29 12:30:31 PM PDT 23 Oct 29 12:30:35 PM PDT 23 2116887594 ps
T623 /workspace/coverage/default/27.sysrst_ctrl_smoke.52709748609840759315021898312018290791219497927322247992591196081198865609127 Oct 29 12:29:26 PM PDT 23 Oct 29 12:29:31 PM PDT 23 2116887594 ps
T624 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.66273227814350596794789814395042695006692903638332824497559043527752570196814 Oct 29 12:30:42 PM PDT 23 Oct 29 12:30:47 PM PDT 23 5189470156 ps
T625 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.71986698142218374733290817385424055141272370890698207753603174556761227601914 Oct 29 12:29:03 PM PDT 23 Oct 29 12:29:08 PM PDT 23 2515402263 ps
T626 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.86466535397668596144200531963015072793120024215570314134567357115664660714948 Oct 29 12:28:26 PM PDT 23 Oct 29 12:28:31 PM PDT 23 5189470156 ps
T627 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.108566904035102295242206661044601355184664150819963138966276544425961265643777 Oct 29 12:30:51 PM PDT 23 Oct 29 12:30:56 PM PDT 23 5189470156 ps
T628 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.54767700357525388607028789375794969181201117961340531673303982968117232105784 Oct 29 12:29:54 PM PDT 23 Oct 29 12:29:59 PM PDT 23 5189470156 ps
T629 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.64334579569248531807761663492617521625138537004028288313345804262178311206725 Oct 29 12:31:07 PM PDT 23 Oct 29 12:34:13 PM PDT 23 118289458206 ps
T630 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.84250498613309783017606835626705040870398189666316774663188660387850636108340 Oct 29 12:30:32 PM PDT 23 Oct 29 12:30:37 PM PDT 23 2470384766 ps
T631 /workspace/coverage/default/5.sysrst_ctrl_alert_test.114700805961692914572500986280767072244216089994525680459104013002472092554144 Oct 29 12:27:56 PM PDT 23 Oct 29 12:28:01 PM PDT 23 2015424120 ps
T632 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.30028844774154392080857322097471990175821169875153055191379032386484157292103 Oct 29 12:28:46 PM PDT 23 Oct 29 12:28:50 PM PDT 23 2074566504 ps
T633 /workspace/coverage/default/34.sysrst_ctrl_smoke.106212438069941718604721267876091661651998870775187732088281663202752715163748 Oct 29 12:29:51 PM PDT 23 Oct 29 12:29:57 PM PDT 23 2116887594 ps
T634 /workspace/coverage/default/13.sysrst_ctrl_smoke.77153774998378436525695954466883884312054846962820672590956902369700939789950 Oct 29 12:28:28 PM PDT 23 Oct 29 12:28:32 PM PDT 23 2116887594 ps
T635 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.85734939223605025155478085922088910100435733275147510017447944885672992161314 Oct 29 12:28:06 PM PDT 23 Oct 29 12:28:15 PM PDT 23 4425119128 ps
T636 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.79815541268874325808592530853606175011991682064307227615440335056905228152404 Oct 29 12:28:07 PM PDT 23 Oct 29 12:28:16 PM PDT 23 3138968703 ps
T637 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.33260642486738737437660007105855386151300203889096157816597345082335747553316 Oct 29 12:29:41 PM PDT 23 Oct 29 12:29:46 PM PDT 23 5189470156 ps
T638 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.109036827401447330852771215935228327527460426337619373727523053030605430636043 Oct 29 12:27:55 PM PDT 23 Oct 29 12:28:05 PM PDT 23 4425119128 ps
T639 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.104252408318706036132607918121996247880264915034456035034155280598591605553902 Oct 29 12:30:07 PM PDT 23 Oct 29 12:30:13 PM PDT 23 4089103959 ps
T640 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.7274946916348812585520514383988919457314666330794085700238744700813354694312 Oct 29 12:28:44 PM PDT 23 Oct 29 12:28:51 PM PDT 23 4089103959 ps
T641 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.8721299320539646720876095734846671044947748374108613656599885757759016202694 Oct 29 12:27:31 PM PDT 23 Oct 29 12:27:36 PM PDT 23 3138968703 ps
T642 /workspace/coverage/default/1.sysrst_ctrl_alert_test.63287899710821132370127638530920688873934120048733923402791861112351185115899 Oct 29 12:27:45 PM PDT 23 Oct 29 12:27:52 PM PDT 23 2015424120 ps
T643 /workspace/coverage/default/12.sysrst_ctrl_smoke.61194004121306568951342313565158234414334257583083698226174405194287454404909 Oct 29 12:29:20 PM PDT 23 Oct 29 12:29:25 PM PDT 23 2116887594 ps
T644 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.63065809614978641897358992750196311886105559594715914987663734756761516292828 Oct 29 12:29:08 PM PDT 23 Oct 29 12:29:12 PM PDT 23 2074566504 ps
T645 /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.91847193382868714013904527724514751600075155563600749188503901099288943084508 Oct 29 12:30:31 PM PDT 23 Oct 29 12:30:37 PM PDT 23 3138968703 ps
T646 /workspace/coverage/default/1.sysrst_ctrl_stress_all.108918541099578533861123237055372621385946045782798555226176926342959264045382 Oct 29 12:29:02 PM PDT 23 Oct 29 12:31:19 PM PDT 23 87228974549 ps
T647 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.87690270373429774355218516309774639413583848571087085893218820924010295873222 Oct 29 12:30:12 PM PDT 23 Oct 29 12:30:17 PM PDT 23 2470384766 ps
T648 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.114279455306743299920824427694755223442992721256213605707890477439485927887500 Oct 29 12:28:55 PM PDT 23 Oct 29 12:28:59 PM PDT 23 2074566504 ps
T649 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.76701947875657230825064616729144942938477955965711007212630201759716553163785 Oct 29 12:29:31 PM PDT 23 Oct 29 12:29:37 PM PDT 23 5189470156 ps
T650 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.90643795115554212201485585598585363047262542904359496894413900320631087867901 Oct 29 12:29:00 PM PDT 23 Oct 29 12:29:08 PM PDT 23 4425119128 ps
T651 /workspace/coverage/default/22.sysrst_ctrl_smoke.83250760595656921372836809599362690718718108959206310442170240207692598963524 Oct 29 12:29:12 PM PDT 23 Oct 29 12:29:16 PM PDT 23 2116887594 ps
T652 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.90352097591031819369052773336186000313603790274011180442057538094948076995809 Oct 29 12:30:50 PM PDT 23 Oct 29 12:30:55 PM PDT 23 2515402263 ps
T653 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.50457958473051593188196580695505767828434792230350622502894579850749160856037 Oct 29 12:29:53 PM PDT 23 Oct 29 12:30:01 PM PDT 23 4425119128 ps
T654 /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.9332741085683707531034967532562081852017441088093117389830012826182732883990 Oct 29 12:30:41 PM PDT 23 Oct 29 12:30:46 PM PDT 23 2515402263 ps
T655 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.16592265934070894047121416773289924250372461083486973032027418068018007817386 Oct 29 12:29:57 PM PDT 23 Oct 29 12:30:02 PM PDT 23 2515402263 ps
T656 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.5456372173224485604102541500350622152690010854413253919369286020970907933206 Oct 29 12:28:39 PM PDT 23 Oct 29 12:28:44 PM PDT 23 2515402263 ps
T657 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.75740051480874577242785147647669658911187945055051147828690200521665494607110 Oct 29 12:27:39 PM PDT 23 Oct 29 12:27:47 PM PDT 23 4425119128 ps
T658 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.57286550675293284853677156992009924676677769389845058639874134901791689201977 Oct 29 12:29:51 PM PDT 23 Oct 29 12:29:58 PM PDT 23 2470384766 ps
T659 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.56675373801212543351177282463720120246380851432696198297973406055092132028311 Oct 29 12:29:07 PM PDT 23 Oct 29 12:29:14 PM PDT 23 4089103959 ps
T660 /workspace/coverage/default/10.sysrst_ctrl_smoke.29458275211748412128145632279174929197377056110569265503456791300630266749100 Oct 29 12:28:34 PM PDT 23 Oct 29 12:28:38 PM PDT 23 2116887594 ps
T661 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.10503945284883336184980839216756742620285117445161972488616541887412781632247 Oct 29 12:29:08 PM PDT 23 Oct 29 12:29:13 PM PDT 23 5189470156 ps
T662 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.98683186274532672614836935131953490513112128406128180493460612087717773204347 Oct 29 12:28:07 PM PDT 23 Oct 29 12:28:16 PM PDT 23 5189470156 ps
T663 /workspace/coverage/default/25.sysrst_ctrl_stress_all.24106991895273466272034422684393656152712689349560823364017963621834767793234 Oct 29 12:29:18 PM PDT 23 Oct 29 12:31:34 PM PDT 23 87228974549 ps
T664 /workspace/coverage/default/48.sysrst_ctrl_smoke.92648012790872322318065150311672774337642304526384047070977031857738761616231 Oct 29 12:30:53 PM PDT 23 Oct 29 12:30:57 PM PDT 23 2116887594 ps
T665 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.31440112455069666472623585047157504276446536131337576798883258419259764498020 Oct 29 12:29:56 PM PDT 23 Oct 29 12:30:04 PM PDT 23 4089103959 ps
T666 /workspace/coverage/default/24.sysrst_ctrl_combo_detect.42394115360734487591047957195861281751547722336320962621729053750793241626786 Oct 29 12:29:23 PM PDT 23 Oct 29 12:32:26 PM PDT 23 118289458206 ps
T117 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.77423100648790329502928825446935832013354952638284365752773118330903930878632 Oct 29 12:27:30 PM PDT 23 Oct 29 12:27:35 PM PDT 23 2534562824 ps
T667 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.22739730466583357555480478463578545939444934970619390830748401787040649633960 Oct 29 12:29:45 PM PDT 23 Oct 29 12:29:51 PM PDT 23 3138968703 ps
T668 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.99732292507695005933134595104847718855580576212477943873717666912056796609991 Oct 29 12:29:52 PM PDT 23 Oct 29 12:29:57 PM PDT 23 2074566504 ps
T669 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.27539837602373533846097672786174961243300285789618293837451621338973503512029 Oct 29 12:30:51 PM PDT 23 Oct 29 12:30:56 PM PDT 23 2515402263 ps
T670 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.45934617505725719490248108260515492454918387417581895783482733682386153057156 Oct 29 12:28:06 PM PDT 23 Oct 29 12:28:13 PM PDT 23 4089103959 ps
T64 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.18740750677685690768560087419119387950658050945580492193978710164028402956462 Oct 29 12:27:09 PM PDT 23 Oct 29 12:27:13 PM PDT 23 2074977215 ps
T143 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.78454657314770911147833124558631331988089408994663199559834425171230609841478 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2023227629 ps
T144 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.52951574116910956139493834962378097789372962549695808077458859320978942184403 Oct 29 12:27:17 PM PDT 23 Oct 29 12:27:21 PM PDT 23 2023227629 ps
T87 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.61350446844361873416105021614262774631888754256204871630862128739390113327196 Oct 29 12:27:33 PM PDT 23 Oct 29 12:27:59 PM PDT 23 9477310853 ps
T65 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.48724060977145241258348981329745952475059132333084710079266235880890236175541 Oct 29 12:27:21 PM PDT 23 Oct 29 12:27:32 PM PDT 23 6030981281 ps
T1 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.52611466532483835884185561640788764970746659727173517551193037247673371753203 Oct 29 12:27:22 PM PDT 23 Oct 29 12:28:33 PM PDT 23 42510939439 ps
T11 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.96236588952511530299895815064697085197148435720203147807183373520667796144592 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2023227629 ps
T2 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.90374568538780407169732116716894499890084523147272784298783430681545797861599 Oct 29 12:26:55 PM PDT 23 Oct 29 12:27:01 PM PDT 23 2186637036 ps
T3 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.87590300110302440246289370051626457617214219963193230153818213919987610531193 Oct 29 12:28:07 PM PDT 23 Oct 29 12:29:17 PM PDT 23 42510939439 ps
T4 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.68405799128439405326245745428813422772042282477137059628275049835330529548061 Oct 29 12:26:18 PM PDT 23 Oct 29 12:27:30 PM PDT 23 42510939439 ps
T12 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.39210560419094884862348027496585345788250383589532822563479277583613880881662 Oct 29 12:27:50 PM PDT 23 Oct 29 12:27:55 PM PDT 23 2023227629 ps
T13 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.111512979836791960401363833279683444249347882218497117821545927027831641847119 Oct 29 12:25:14 PM PDT 23 Oct 29 12:25:41 PM PDT 23 9477310853 ps
T5 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.86796427877342593562923662067197257273533195550824506140224689702271043928508 Oct 29 12:28:08 PM PDT 23 Oct 29 12:28:17 PM PDT 23 2186637036 ps
T6 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.25328328626743172195685027840625386100777447235561414366616386897449918869251 Oct 29 12:27:01 PM PDT 23 Oct 29 12:27:05 PM PDT 23 2142012393 ps
T14 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.113988886532474216345186542648683543932265640164598498183585031417013941924803 Oct 29 12:24:50 PM PDT 23 Oct 29 12:25:18 PM PDT 23 9477310853 ps
T7 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.32883684228543872533093974018244450202950586224379349511064256853902665220376 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:20 PM PDT 23 2142012393 ps
T60 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.43495940574465687857428914556571397854846811190912975568166079387085515413603 Oct 29 12:27:26 PM PDT 23 Oct 29 12:27:51 PM PDT 23 9477310853 ps
T671 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.80578242182541011680641507153334006527114763713179636334193037012648467091515 Oct 29 12:27:07 PM PDT 23 Oct 29 12:27:12 PM PDT 23 2023227629 ps
T8 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.41072851064838522889900722455220828869773036916134460207826487168529331825564 Oct 29 12:26:57 PM PDT 23 Oct 29 12:27:03 PM PDT 23 2186637036 ps
T88 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.6835868827529897513041583586410734207336480479726563837163174709255305331347 Oct 29 12:26:00 PM PDT 23 Oct 29 12:26:25 PM PDT 23 9477310853 ps
T66 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.83419151907892974522475960810928480859070586177087383566696229296757033612698 Oct 29 12:27:07 PM PDT 23 Oct 29 12:27:15 PM PDT 23 2890827831 ps
T74 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.36212280584545398249163300837851019807928503075368609547784225862891170948813 Oct 29 12:27:20 PM PDT 23 Oct 29 12:27:25 PM PDT 23 2023227629 ps
T9 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.106126558494952726569009447894351679420028369958607566690894102829085085532731 Oct 29 12:27:06 PM PDT 23 Oct 29 12:27:10 PM PDT 23 2142012393 ps
T672 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.75807669824975108961725328729609322165414575893083116132222478963341017066227 Oct 29 12:27:05 PM PDT 23 Oct 29 12:27:10 PM PDT 23 2023227629 ps
T67 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.100568833449057829394217659005333389830746566897785181932418026683957894236167 Oct 29 12:27:17 PM PDT 23 Oct 29 12:27:22 PM PDT 23 2074977215 ps
T10 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.53808836435675664297822476799573347584343366029365873931498786060753180367794 Oct 29 12:26:49 PM PDT 23 Oct 29 12:26:53 PM PDT 23 2142012393 ps
T673 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.75537590014876717051015873372445860621829220338277285222793693658505231548611 Oct 29 12:26:57 PM PDT 23 Oct 29 12:27:02 PM PDT 23 2142012393 ps
T68 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.25245316351151554985168951953488440813507491617880196562270743455401532893659 Oct 29 12:26:57 PM PDT 23 Oct 29 12:27:08 PM PDT 23 6030981281 ps
T674 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.71341539770545966582424536427295983811007417143235375238632862581561949447351 Oct 29 12:27:27 PM PDT 23 Oct 29 12:27:32 PM PDT 23 2142012393 ps
T69 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.32747261744931866273744047085860661081904120161756489188362820542574182379284 Oct 29 12:26:51 PM PDT 23 Oct 29 12:26:56 PM PDT 23 2074977215 ps
T675 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.48081152208684483580052720828839169894413323601429579159865372071172452562019 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2023227629 ps
T676 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.20109373682899048203206587057247601036485707549057871547857405190990725377746 Oct 29 12:27:57 PM PDT 23 Oct 29 12:28:01 PM PDT 23 2023227629 ps
T677 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.69100237616557095249643930575559299384246144647176215210605644571400390846256 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2023227629 ps
T678 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.111215621744049402154806399757486219592709760220810175071992057438300999318307 Oct 29 12:26:56 PM PDT 23 Oct 29 12:27:00 PM PDT 23 2023227629 ps
T50 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.18858600764977858619140105434333340276315769874342567443216337137724581948969 Oct 29 12:26:49 PM PDT 23 Oct 29 12:26:55 PM PDT 23 2186637036 ps
T679 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.93107590188985563470424665929492916382669280815401683486180091712741216156039 Oct 29 12:28:54 PM PDT 23 Oct 29 12:28:58 PM PDT 23 2023227629 ps
T70 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.115547461458050422296353466270435902545792888866331729283755570954150250761623 Oct 29 12:28:07 PM PDT 23 Oct 29 12:28:21 PM PDT 23 6030981281 ps
T89 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.66276679130089951132039610905739806124885195453619506296937224162121618281147 Oct 29 12:26:50 PM PDT 23 Oct 29 12:27:15 PM PDT 23 9477310853 ps
T680 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.17022006359864669136626556152105682478812218505914831606698745822886050118102 Oct 29 12:27:12 PM PDT 23 Oct 29 12:27:16 PM PDT 23 2023227629 ps
T51 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.101226382468419450639372530909826586850766332333513812457211384925193119143992 Oct 29 12:27:03 PM PDT 23 Oct 29 12:28:14 PM PDT 23 42510939439 ps
T52 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.9168988826220265908543141683881595792800440460302785867295734021789171470112 Oct 29 12:27:07 PM PDT 23 Oct 29 12:28:17 PM PDT 23 42510939439 ps
T53 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.59756263322121904271309109171090404770214631941481311144722755266506022234169 Oct 29 12:26:29 PM PDT 23 Oct 29 12:27:41 PM PDT 23 42510939439 ps
T71 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.36582799973352552280593802868176106270838948871203809759978074905796836627369 Oct 29 12:27:16 PM PDT 23 Oct 29 12:27:20 PM PDT 23 2074977215 ps
T681 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.29603620724258991002509348387064681563119366935064888607120394433985982095403 Oct 29 12:27:21 PM PDT 23 Oct 29 12:27:47 PM PDT 23 9477310853 ps
T682 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.64034808949721237334878420426306914586052942244013086019096551703819684800693 Oct 29 12:28:54 PM PDT 23 Oct 29 12:29:18 PM PDT 23 9477310853 ps
T54 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.114299704143349052756939828588396775642798933044573945885423440297052977306701 Oct 29 12:25:54 PM PDT 23 Oct 29 12:26:01 PM PDT 23 2186637036 ps
T72 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.62091160196449543666221040351440853848296666030649663117931157008205632927317 Oct 29 12:25:55 PM PDT 23 Oct 29 12:26:04 PM PDT 23 2890827831 ps
T75 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.36526297281338468230177869903404013920747758513802384491314510846199075588960 Oct 29 12:25:44 PM PDT 23 Oct 29 12:26:55 PM PDT 23 42510939439 ps
T76 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.6701906609258280736097113386760253591635078868619605954045045242321393529889 Oct 29 12:25:07 PM PDT 23 Oct 29 12:25:11 PM PDT 23 2023227629 ps
T77 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.100021720595503960975181258652475115018188591651759641311490664476127066419180 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2023227629 ps
T73 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.86616431627139667266058389938054246967329453649067430534194231966675449244575 Oct 29 12:27:00 PM PDT 23 Oct 29 12:27:09 PM PDT 23 2890827831 ps
T55 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.44405985098237562038091676030674703863533574040082130980337290026496986243091 Oct 29 12:26:40 PM PDT 23 Oct 29 12:26:47 PM PDT 23 2186637036 ps
T78 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.81994190428523594610684577839015755838797257628102504123797086951697772415948 Oct 29 12:27:22 PM PDT 23 Oct 29 12:27:26 PM PDT 23 2023227629 ps
T86 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.42850500800235814291210264884351837816895637528005039513567121413772535883322 Oct 29 12:26:09 PM PDT 23 Oct 29 12:26:22 PM PDT 23 6030981281 ps
T79 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.54435396264161755489399453475636097438065306020700985476417387399237920172 Oct 29 12:26:58 PM PDT 23 Oct 29 12:27:07 PM PDT 23 2890827831 ps
T683 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.59617908660042673718388398833139425491104737382784017100835167766255554613234 Oct 29 12:28:39 PM PDT 23 Oct 29 12:28:44 PM PDT 23 2074977215 ps
T80 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.10543351608830789385484597973705035212348044306619844938863282880046432395342 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:24 PM PDT 23 2890827831 ps
T684 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.32823200089795175869459683754499933477059185887264305433482022478496315615312 Oct 29 12:28:39 PM PDT 23 Oct 29 12:28:44 PM PDT 23 2074977215 ps
T56 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.112414214528957477582359430799836455836735242341978846523354918913830165775596 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:21 PM PDT 23 2186637036 ps
T685 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.113164955455362421126185655916856439953379733640423538939684332991136163440754 Oct 29 12:28:07 PM PDT 23 Oct 29 12:28:15 PM PDT 23 2074977215 ps
T686 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.75853268856396933570638656882588939009184194289954109577150944056803440553438 Oct 29 12:27:48 PM PDT 23 Oct 29 12:27:53 PM PDT 23 2023227629 ps
T687 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.34384731080120743948580601417556562420449672524609867664449931285692696182263 Oct 29 12:26:16 PM PDT 23 Oct 29 12:27:29 PM PDT 23 42510939439 ps
T688 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.94725174228385840803871426789234901948638230089160880044300029571676991536936 Oct 29 12:25:49 PM PDT 23 Oct 29 12:25:53 PM PDT 23 2023227629 ps
T689 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.101580550919838061333128731118389964250113341561189616488367811149983763587900 Oct 29 12:27:18 PM PDT 23 Oct 29 12:27:22 PM PDT 23 2023227629 ps
T690 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.57293922197112420508573046605531898708797999871370908486276788434381227723587 Oct 29 12:26:48 PM PDT 23 Oct 29 12:26:53 PM PDT 23 2074977215 ps
T691 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.70101765242889008375527234851148794308062971638122663208034217681363691403140 Oct 29 12:28:00 PM PDT 23 Oct 29 12:28:25 PM PDT 23 9477310853 ps
T692 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.24907508383383729468080900999524855521852589272054597128309665238487278690189 Oct 29 12:26:29 PM PDT 23 Oct 29 12:26:58 PM PDT 23 9477310853 ps
T693 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.91223289177969906305430251696760765161675536020865487917298510242969708330553 Oct 29 12:27:23 PM PDT 23 Oct 29 12:27:27 PM PDT 23 2023227629 ps
T694 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.19390020335794844746406924329173406381266317178253588377890569763133910924930 Oct 29 12:27:03 PM PDT 23 Oct 29 12:28:15 PM PDT 23 42510939439 ps
T695 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.94258105531034597640334818187401579704305790410532620985684577568978518165514 Oct 29 12:28:45 PM PDT 23 Oct 29 12:28:49 PM PDT 23 2023227629 ps
T696 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.5967927957966078134944330534870982397587301768282516988750636410543367753292 Oct 29 12:26:14 PM PDT 23 Oct 29 12:26:20 PM PDT 23 2142012393 ps
T697 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.19569781666848949155691070880770100750354060866806961306115650548549030528812 Oct 29 12:27:17 PM PDT 23 Oct 29 12:27:42 PM PDT 23 9477310853 ps
T698 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.46764106041053324005293813693525311737857573488037186599801625275975548032139 Oct 29 12:27:05 PM PDT 23 Oct 29 12:27:10 PM PDT 23 2074977215 ps
T699 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.18045204979794570695779161232538191410145123459505372295781106062005446022777 Oct 29 12:27:26 PM PDT 23 Oct 29 12:28:36 PM PDT 23 42510939439 ps
T700 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.31982092207770572225022799450161972653615984965501610845895615989663646986739 Oct 29 12:27:27 PM PDT 23 Oct 29 12:28:36 PM PDT 23 42510939439 ps
T701 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.72912550205636437037872476765488082995588335366837229323264817896929105586549 Oct 29 12:27:21 PM PDT 23 Oct 29 12:27:26 PM PDT 23 2142012393 ps
T81 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.47161873410048257785097669500432415365418739962480839537120298991950209010544 Oct 29 12:27:44 PM PDT 23 Oct 29 12:29:36 PM PDT 23 41047879715 ps
T82 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.75844840746053995990158937162102836717019585280239310520526344521907736881887 Oct 29 12:25:13 PM PDT 23 Oct 29 12:27:10 PM PDT 23 41047879715 ps
T702 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.59453859045696784724325337947925957771718131197719144208590401988783872874612 Oct 29 12:26:59 PM PDT 23 Oct 29 12:27:03 PM PDT 23 2074977215 ps
T703 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.85054422538808898044114036946060656710712747037110140313378546492675545494925 Oct 29 12:25:42 PM PDT 23 Oct 29 12:25:46 PM PDT 23 2023227629 ps
T704 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.85789935937574068340978662663820171644596774354724016597955018881802466278518 Oct 29 12:27:05 PM PDT 23 Oct 29 12:27:09 PM PDT 23 2023227629 ps
T705 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.89503360202759348751986312993599477716116686825640504040189524385667013179434 Oct 29 12:27:22 PM PDT 23 Oct 29 12:27:47 PM PDT 23 9477310853 ps
T706 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.37334975776895918073278590505292145878994248095062961274714024358470410777853 Oct 29 12:27:09 PM PDT 23 Oct 29 12:27:13 PM PDT 23 2023227629 ps
T707 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.18590907832652781975412418439652136661853141354317367818447653375208381748797 Oct 29 12:26:40 PM PDT 23 Oct 29 12:26:46 PM PDT 23 2074977215 ps
T708 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.25688064330067292040434818432651044922533056673268589021422873629562347845312 Oct 29 12:26:05 PM PDT 23 Oct 29 12:27:16 PM PDT 23 42510939439 ps
T709 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.39697271880896360777707227236885625473255781686427549197604271696690532063263 Oct 29 12:27:22 PM PDT 23 Oct 29 12:27:26 PM PDT 23 2074977215 ps
T57 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.58411738456036189889698468877072212996532011637024320077872015743856992064702 Oct 29 12:27:44 PM PDT 23 Oct 29 12:27:50 PM PDT 23 2186637036 ps
T710 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.100851404083054464622332851444754144278488384714347423614058415028938581716331 Oct 29 12:25:51 PM PDT 23 Oct 29 12:25:56 PM PDT 23 2142012393 ps
T58 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1060520989371181240589700525356220302232658022808540074670228848113740520463 Oct 29 12:27:12 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2186637036 ps
T711 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.32738275051188695240759551394609955362668003525844972260699738157193150504647 Oct 29 12:25:29 PM PDT 23 Oct 29 12:25:34 PM PDT 23 2142012393 ps
T712 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.86123880261557501628731911712318379352459094170449007771615563840570708255549 Oct 29 12:25:57 PM PDT 23 Oct 29 12:27:07 PM PDT 23 42510939439 ps
T713 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.46933911157767224966370515894544466015472454023207522057556930590719693478907 Oct 29 12:26:44 PM PDT 23 Oct 29 12:27:55 PM PDT 23 42510939439 ps
T714 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.40407484962496367735513545925455526434415731673928709983940112611868823595198 Oct 29 12:28:40 PM PDT 23 Oct 29 12:28:44 PM PDT 23 2023227629 ps
T59 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.91315707539839828250601872379982332833043117814898174493281413313251782646513 Oct 29 12:27:19 PM PDT 23 Oct 29 12:27:25 PM PDT 23 2186637036 ps
T83 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.62770192197073821364197390091314848127428784754950380367643865365656861109019 Oct 29 12:26:57 PM PDT 23 Oct 29 12:28:49 PM PDT 23 41047879715 ps
T715 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.62481004366814547368546881377996632943649789298792364754306692847604160178388 Oct 29 12:27:22 PM PDT 23 Oct 29 12:27:27 PM PDT 23 2142012393 ps
T716 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.76274677997611090348075595454973317282068737027341288217039666594525867060280 Oct 29 12:26:24 PM PDT 23 Oct 29 12:26:49 PM PDT 23 9477310853 ps
T717 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.115546288272402908098708139476258253865087814912539374500013520340945652845077 Oct 29 12:26:03 PM PDT 23 Oct 29 12:26:07 PM PDT 23 2023227629 ps
T718 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.5170236161300378341893477439724409893159904415128537122435145243128521983811 Oct 29 12:27:18 PM PDT 23 Oct 29 12:27:22 PM PDT 23 2023227629 ps
T719 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.99094285648779583111737677263671557867264520361641681705413334702623309754457 Oct 29 12:27:50 PM PDT 23 Oct 29 12:28:16 PM PDT 23 9477310853 ps
T720 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.48292854624911814183268974478480339468744455904532704858874113430521911631629 Oct 29 12:27:17 PM PDT 23 Oct 29 12:27:42 PM PDT 23 9477310853 ps
T721 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.63140723327329978504943126113438954967502389152905128268586869189831328944843 Oct 29 12:26:47 PM PDT 23 Oct 29 12:26:52 PM PDT 23 2074977215 ps
T722 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.5359507587784647484578061173479327295342709805789492074387362781545121240684 Oct 29 12:28:43 PM PDT 23 Oct 29 12:29:54 PM PDT 23 42510939439 ps
T723 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.10012321495163460971355681158350967341359752545855958794180541586668493685379 Oct 29 12:29:06 PM PDT 23 Oct 29 12:29:10 PM PDT 23 2023227629 ps
T724 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.37508304659848254834785095605863221560202057005399048637409919973072617238262 Oct 29 12:27:32 PM PDT 23 Oct 29 12:27:36 PM PDT 23 2074977215 ps
T725 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.46762600258111682432064193423345029282227508690108611617636749921532420386769 Oct 29 12:27:00 PM PDT 23 Oct 29 12:27:25 PM PDT 23 9477310853 ps
T726 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.100145164752615516490291097065431733439100875847678063589733410921136843637680 Oct 29 12:28:39 PM PDT 23 Oct 29 12:28:43 PM PDT 23 2023227629 ps
T727 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.53769716450479365662585404065665529161394800632376482028560696393143889577918 Oct 29 12:26:19 PM PDT 23 Oct 29 12:27:29 PM PDT 23 42510939439 ps
T728 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.80684305624793345338693703340329994677326174153846907331120221700920798372413 Oct 29 12:26:13 PM PDT 23 Oct 29 12:26:18 PM PDT 23 2023227629 ps
T729 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.77057405366480959767373599990780128010850691013671773252600390079497338813210 Oct 29 12:27:34 PM PDT 23 Oct 29 12:27:59 PM PDT 23 9477310853 ps
T730 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.112469863571857070237905262464701391651398870880265999183155864504023061406060 Oct 29 12:28:01 PM PDT 23 Oct 29 12:28:05 PM PDT 23 2023227629 ps
T731 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.40873523801773902597829029052803000227977937051405090843038971191197952180300 Oct 29 12:28:07 PM PDT 23 Oct 29 12:28:15 PM PDT 23 2074977215 ps
T732 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.90165079382914122935151056065243708025698546738750840832797968118821325763878 Oct 29 12:27:16 PM PDT 23 Oct 29 12:27:20 PM PDT 23 2023227629 ps
T84 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.46063710256924559182619561740208918621816886022477171727318385720541922600218 Oct 29 12:26:56 PM PDT 23 Oct 29 12:28:49 PM PDT 23 41047879715 ps
T733 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.67131838341373507514583708445256137791553348352009080216704857632095756018057 Oct 29 12:27:48 PM PDT 23 Oct 29 12:27:53 PM PDT 23 2023227629 ps
T734 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.40979854561560319865969450808988265455972836080760136843870850955096928130472 Oct 29 12:27:04 PM PDT 23 Oct 29 12:27:10 PM PDT 23 2186637036 ps
T735 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.115750757980051561861838853634913209791697828253481867736049521040496700850192 Oct 29 12:28:55 PM PDT 23 Oct 29 12:30:05 PM PDT 23 42510939439 ps
T736 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.36075308213031964952250393873298699350584097163871859895872656895557981712567 Oct 29 12:27:21 PM PDT 23 Oct 29 12:27:27 PM PDT 23 2186637036 ps
T737 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.82525784893892236550833496804765841809090174968039579779457408602695310099233 Oct 29 12:27:33 PM PDT 23 Oct 29 12:28:44 PM PDT 23 42510939439 ps
T738 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.60277739209850242298297992188043465001047368501482123511005558552160691506551 Oct 29 12:25:44 PM PDT 23 Oct 29 12:25:48 PM PDT 23 2142012393 ps
T739 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.6671370778963890211398861733551059190503812879479863728028891285885040118719 Oct 29 12:27:05 PM PDT 23 Oct 29 12:27:10 PM PDT 23 2142012393 ps
T740 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.82900589762696548315622506035270211569413252522843854616248610764863889502326 Oct 29 12:27:07 PM PDT 23 Oct 29 12:27:11 PM PDT 23 2023227629 ps
T741 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.38476090334891615439098078064384983428624829328593292290551590185752626807084 Oct 29 12:27:32 PM PDT 23 Oct 29 12:27:36 PM PDT 23 2023227629 ps
T742 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.58652484565153580266686518091761297747938526920831684265608765564181977568256 Oct 29 12:26:55 PM PDT 23 Oct 29 12:26:59 PM PDT 23 2023227629 ps
T743 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.74660862335916402661167199368559492070951767587777722874137976767870486514741 Oct 29 12:27:18 PM PDT 23 Oct 29 12:27:43 PM PDT 23 9477310853 ps
T744 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.59501360991101202170390751587962977289941411790319853535015190784010297594315 Oct 29 12:26:55 PM PDT 23 Oct 29 12:28:06 PM PDT 23 42510939439 ps
T745 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.18979096578084702286226265517125897137358700655500390971685774795995745049983 Oct 29 12:27:21 PM PDT 23 Oct 29 12:27:28 PM PDT 23 2186637036 ps
T746 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.83650664302198228081613175742128814557027305218065967018046838447149640362951 Oct 29 12:27:14 PM PDT 23 Oct 29 12:27:18 PM PDT 23 2023227629 ps
T747 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.89216108965542246027228099707018906799451365362401659690247046121409767375234 Oct 29 12:28:53 PM PDT 23 Oct 29 12:28:57 PM PDT 23 2074977215 ps
T748 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.72105553222686139077413885470495583654071691855182055742290237979875376085084 Oct 29 12:27:38 PM PDT 23 Oct 29 12:27:42 PM PDT 23 2023227629 ps
T749 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.84296359293313666589421472059686451951440771209028786876213189674872050730088 Oct 29 12:27:54 PM PDT 23 Oct 29 12:28:01 PM PDT 23 2023227629 ps
T750 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.9296295761977617023103072526720018669759624954328235619220781395974023397169 Oct 29 12:27:19 PM PDT 23 Oct 29 12:27:23 PM PDT 23 2142012393 ps
T751 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.19376284140256201349406050277070136589778973481253292238146304110789412855226 Oct 29 12:27:55 PM PDT 23 Oct 29 12:28:01 PM PDT 23 2023227629 ps
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