Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T752 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.35125996942021840325346179388325419742417972387092427706232670428232258039145 Oct 29 12:28:01 PM PDT 23 Oct 29 12:28:06 PM PDT 23 2023227629 ps
T753 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.100766768693484284305290689247358378095985428653718401329538892917722512158253 Oct 29 12:25:48 PM PDT 23 Oct 29 12:25:52 PM PDT 23 2074977215 ps
T754 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.18492911627494540419214551243471254376546808435663431472102174541223219763770 Oct 29 12:28:07 PM PDT 23 Oct 29 12:28:16 PM PDT 23 2142012393 ps
T755 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.58091878652381928593273619780584613190232856317858446432134173115434041867629 Oct 29 12:28:13 PM PDT 23 Oct 29 12:28:20 PM PDT 23 2186637036 ps
T756 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.98376625816629975449258049700993228525608654089853281152456862031242449406669 Oct 29 12:25:57 PM PDT 23 Oct 29 12:26:02 PM PDT 23 2142012393 ps
T757 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.97106634158171463038088523105099586451405902572874689933379545167023287786741 Oct 29 12:27:05 PM PDT 23 Oct 29 12:27:09 PM PDT 23 2142012393 ps
T758 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.109555787659431530105350900408568560020667837475123276092359257328665479058473 Oct 29 12:27:14 PM PDT 23 Oct 29 12:27:18 PM PDT 23 2023227629 ps
T759 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.72139950959627865754558335905028794825967951693361034434703152377172741482830 Oct 29 12:27:04 PM PDT 23 Oct 29 12:27:08 PM PDT 23 2074977215 ps
T760 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.77565815146009306702663435492585215909052239731468236208961780758830138890607 Oct 29 12:27:43 PM PDT 23 Oct 29 12:27:49 PM PDT 23 2186637036 ps
T761 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.66069714646833895833081269503866856817266764096312987626603495450424013689739 Oct 29 12:27:22 PM PDT 23 Oct 29 12:27:26 PM PDT 23 2023227629 ps
T762 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.41454374438325434638300286865827813329524518930879140852928038513674750694500 Oct 29 12:27:11 PM PDT 23 Oct 29 12:27:16 PM PDT 23 2142012393 ps
T763 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.68234849326702074883870790428891855694990555581660982151715418771204549628024 Oct 29 12:25:30 PM PDT 23 Oct 29 12:25:41 PM PDT 23 6030981281 ps
T764 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.9509723032675110145531836204792773381940611646591487735994649583652181484281 Oct 29 12:27:48 PM PDT 23 Oct 29 12:27:55 PM PDT 23 2186637036 ps
T765 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.12953703784015857946732294507490895403341876299674557719579709079848311592995 Oct 29 12:27:19 PM PDT 23 Oct 29 12:27:25 PM PDT 23 2186637036 ps
T766 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.59088042639751556224101628907312068406661258282535637355994388936788625596521 Oct 29 12:26:48 PM PDT 23 Oct 29 12:27:59 PM PDT 23 42510939439 ps
T85 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.86156155270107747372658790370364135708229721313524858447034252799409790332678 Oct 29 12:27:21 PM PDT 23 Oct 29 12:29:17 PM PDT 23 41047879715 ps
T767 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.90619927490215309337098003030170714933074641792365004453433156874384296347469 Oct 29 12:26:14 PM PDT 23 Oct 29 12:26:21 PM PDT 23 2186637036 ps
T768 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.40079526925579888134684052690560934332979274099931222343606009170287525378173 Oct 29 12:27:22 PM PDT 23 Oct 29 12:27:26 PM PDT 23 2023227629 ps
T769 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.14942474032654358164703728545178032297596099664204160329506422446671375620647 Oct 29 12:27:15 PM PDT 23 Oct 29 12:27:19 PM PDT 23 2023227629 ps
T770 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.92412172968277192733813351274154318262412025310249780927476499737693716852888 Oct 29 12:26:59 PM PDT 23 Oct 29 12:27:04 PM PDT 23 2142012393 ps
T771 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.105089410659665033896787199255639608342541707186311474137285023497467575337841 Oct 29 12:27:40 PM PDT 23 Oct 29 12:27:44 PM PDT 23 2142012393 ps
T772 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.39681790597829530357172416221822354855534551265484988833010197476536159601323 Oct 29 12:27:20 PM PDT 23 Oct 29 12:27:27 PM PDT 23 2186637036 ps
T773 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.104896825961338291874160225516187133483276440418908971273699345154986253221516 Oct 29 12:26:14 PM PDT 23 Oct 29 12:26:41 PM PDT 23 9477310853 ps
T774 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.114066914901447354767908104742523302953585243147174417037583332016051331804606 Oct 29 12:27:46 PM PDT 23 Oct 29 12:27:53 PM PDT 23 2023227629 ps
T775 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.84260669502517035238792565032701045465491129321348990234560136809661103153548 Oct 29 12:27:32 PM PDT 23 Oct 29 12:27:36 PM PDT 23 2023227629 ps
T776 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.55410948396270993574812690776269723533293515947533096307519011078469227100651 Oct 29 12:26:05 PM PDT 23 Oct 29 12:26:09 PM PDT 23 2074977215 ps
T777 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3878015759956013953505311128535241837602296788363845467526554827093573718314 Oct 29 12:28:47 PM PDT 23 Oct 29 12:28:51 PM PDT 23 2023227629 ps
T778 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.85413153418497479515039755856013198934940955942429899420946804362446651689389 Oct 29 12:25:49 PM PDT 23 Oct 29 12:25:54 PM PDT 23 2074977215 ps
T779 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.44442732031980708272154545192929894040424892308871367407775748718706191939020 Oct 29 12:25:24 PM PDT 23 Oct 29 12:25:30 PM PDT 23 2186637036 ps
T780 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.11824666287931097530304862088332748884669920826989707854500448634945002601648 Oct 29 12:28:54 PM PDT 23 Oct 29 12:28:58 PM PDT 23 2023227629 ps
T781 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.39664846956826818386882373381143675542829072915948370524504260729021124220188 Oct 29 12:27:10 PM PDT 23 Oct 29 12:27:14 PM PDT 23 2023227629 ps
T782 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.83495636262822881178878733108240312770028248576616865488614823994509602473458 Oct 29 12:27:18 PM PDT 23 Oct 29 12:27:42 PM PDT 23 9477310853 ps

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.104872522240370517126061745610328561826403411056600097932667015549063593638970
Short name T20
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.75 seconds
Started Oct 29 12:30:35 PM PDT 23
Finished Oct 29 12:32:53 PM PDT 23
Peak memory 201296 kb
Host smart-f3342c46-62ae-445f-a464-d6efa44e24de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104872522240370517126061745610328561826403411056600097932667015549063593638970 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.104872522240370517126061745610328561826403411056600097932667015549063593638970
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.17846999750616877003923840425784151179287534061758000085858637428335913199241
Short name T92
Test name
Test status
Simulation time 38606274248 ps
CPU time 59.96 seconds
Started Oct 29 12:27:44 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 200960 kb
Host smart-2b8663d7-306e-4c60-90e3-44405c91fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17846999750616877003923840425784151179287534061758000085858637428335913199241 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.17846999750616877003923840425784151179287534061758000085858637428335913199241
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.68405799128439405326245745428813422772042282477137059628275049835330529548061
Short name T4
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.72 seconds
Started Oct 29 12:26:18 PM PDT 23
Finished Oct 29 12:27:30 PM PDT 23
Peak memory 200944 kb
Host smart-8f0ec045-df2e-4cbf-b79c-65eaaa5fa6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68405799128439405326245745428813422772042282477137059628275049835330529548061 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.68405799128439405326245745428813422772042282477137059628275049
835330529548061
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.106348552531933304580841161423179952785527975319259149206089155058852255932992
Short name T15
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.84 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:15 PM PDT 23
Peak memory 201016 kb
Host smart-efeafbf6-18f2-4527-ac65-80eba364a8e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106348552531933304580841161423179952785527975319259149206089155058852255932992 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.106348552531933304580841161423179952785527975319259149206089
155058852255932992
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.46561081314197299832161244503436589103339724461130224863865463428852107179197
Short name T22
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.59 seconds
Started Oct 29 12:29:39 PM PDT 23
Finished Oct 29 12:32:43 PM PDT 23
Peak memory 201272 kb
Host smart-183e2b09-6b6f-4fe9-b5ef-0e857a1eaa00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46561081314197299832161244503436589103339724461130224863865463428852107179197 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.46561081314197299832161244503436589103339724461130224863865463
428852107179197
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.41072851064838522889900722455220828869773036916134460207826487168529331825564
Short name T8
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.86 seconds
Started Oct 29 12:26:57 PM PDT 23
Finished Oct 29 12:27:03 PM PDT 23
Peak memory 200408 kb
Host smart-ff776106-a127-44a4-a6ff-b26c02c5332a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072851064838522889900722455220828869773036916134460207826487168529331825564 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.41072851064838522889900722455220828869773036916134460207826487168529331825564
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.95809641758915802219638493392382210020656927270288034811750824058975920148653
Short name T96
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.62 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:12 PM PDT 23
Peak memory 201072 kb
Host smart-47d6d336-ef51-4702-8972-25fa1b461dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95809641758915802219638493392382210020656927270288034811750824058975920148653 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.95809641758915802219638493392382210020656927270288034811750824058975920148653
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.8572613820338589971754534086207136224123526545924265959924745642533938438334
Short name T16
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.77 seconds
Started Oct 29 12:28:56 PM PDT 23
Finished Oct 29 12:29:00 PM PDT 23
Peak memory 200980 kb
Host smart-c3d36b60-c95a-4929-9d25-541d7f1234db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8572613820338589971754534086207136224123526545924265959924745642533938438334 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.8572613820338589971754534086207136224123526545924265959924745642533938438334
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.61350446844361873416105021614262774631888754256204871630862128739390113327196
Short name T87
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.39 seconds
Started Oct 29 12:27:33 PM PDT 23
Finished Oct 29 12:27:59 PM PDT 23
Peak memory 201108 kb
Host smart-87fcd8e8-dfbf-4717-afee-79854395781e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61350446844361873416105021614262774631888754256204871630862128739390113327196
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.613504468443618734161050216142627746318887542
56204871630862128739390113327196
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.63738211018155069080698544029570829600375878482960628224430750443909362617742
Short name T133
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 29 12:28:30 PM PDT 23
Finished Oct 29 12:28:37 PM PDT 23
Peak memory 200976 kb
Host smart-67901845-e9ce-4959-ae42-136b4a83a43f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63738211018155069080698544029570829600375878482960628224430750443909362617742 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.6373821101815506908069854402957082960037587848296062822443075044
3909362617742
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.10066353626593167735714336066168623811824808663939793262726020483734027820865
Short name T187
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 29 12:28:31 PM PDT 23
Finished Oct 29 12:28:35 PM PDT 23
Peak memory 200984 kb
Host smart-808740ee-6761-4bab-a1ce-b1f6bd2e3098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10066353626593167735714336066168623811824808663939793262726020483734027820865 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.10066353626593167735714336066168623811824808663939793262726020483734027820865
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.87231356895845107691476088504137452853183695135510639743536696408632350704711
Short name T145
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.24 seconds
Started Oct 29 12:27:31 PM PDT 23
Finished Oct 29 12:28:36 PM PDT 23
Peak memory 221428 kb
Host smart-d8e10c94-7d47-470f-bf3c-621a1a3f8afa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87231356895845107691476088504137452853183695135510639743536696408632350704711 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.87231356895845107691476088504137452853183695135510639743536696408632350704711
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.80578242182541011680641507153334006527114763713179636334193037012648467091515
Short name T671
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 29 12:27:07 PM PDT 23
Finished Oct 29 12:27:12 PM PDT 23
Peak memory 200720 kb
Host smart-afc75830-dd10-4797-9fbd-c88327e4d95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80578242182541011680641507153334006527114763713179636334193037012648467091515 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.80578242182541011680641507153334006527114763713179636334193037012648467091515
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.86616431627139667266058389938054246967329453649067430534194231966675449244575
Short name T73
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.54 seconds
Started Oct 29 12:27:00 PM PDT 23
Finished Oct 29 12:27:09 PM PDT 23
Peak memory 200912 kb
Host smart-91225020-6b47-4b2f-b6cc-82ac5c893245
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86616431627139667266058389938054246967329453649067430534194231966675449244575 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.86616431627139667266058389938054246967329453649067430534194231966675449244575
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.38930469266137633642886222755274929548968257507695180026958544782957959789858
Short name T152
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.32 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:29:07 PM PDT 23
Peak memory 201024 kb
Host smart-6aa115fd-6f7f-400d-8cad-52af193e9cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38930469266137633642886222755274929548968257507695180026958544782957959789858 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.38930469266137633642886222755274929548968257507695180026958544782957959789858
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2678719647937964850537279755538917384867767129968119131719770239948558666144
Short name T164
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 29 12:28:24 PM PDT 23
Finished Oct 29 12:28:32 PM PDT 23
Peak memory 201028 kb
Host smart-6cdd6bf8-e663-4f18-817c-428df6c6b3fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678719647937964850537279755538917384867767129968119131719770239948558666144 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.2678719647937964850537279755538917384867767129968119131719770
239948558666144
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.10543351608830789385484597973705035212348044306619844938863282880046432395342
Short name T80
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.48 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:24 PM PDT 23
Peak memory 201072 kb
Host smart-5c91e121-bfc0-4f55-9b03-e12515dc8b11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543351608830789385484597973705035212348044306619844938863282880046432395342 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.10543351608830789385484597973705035212348044306619844938863282880046432395342
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.46063710256924559182619561740208918621816886022477171727318385720541922600218
Short name T84
Test name
Test status
Simulation time 41047879715 ps
CPU time 112.52 seconds
Started Oct 29 12:26:56 PM PDT 23
Finished Oct 29 12:28:49 PM PDT 23
Peak memory 201052 kb
Host smart-c1106ff1-aeff-45d9-b56d-34e11d60e807
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46063710256924559182619561740208918621816886022477171727318385720541922600218 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.46063710256924559182619561740208918621816886022477171727318385720541922600218
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.42850500800235814291210264884351837816895637528005039513567121413772535883322
Short name T86
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.19 seconds
Started Oct 29 12:26:09 PM PDT 23
Finished Oct 29 12:26:22 PM PDT 23
Peak memory 201252 kb
Host smart-0b9d862f-7f9c-4e63-a277-91d867b08473
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850500800235814291210264884351837816895637528005039513567121413772535883322 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.42850500800235814291210264884351837816895637528005039513567121413772535883322
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.98376625816629975449258049700993228525608654089853281152456862031242449406669
Short name T756
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Oct 29 12:25:57 PM PDT 23
Finished Oct 29 12:26:02 PM PDT 23
Peak memory 200864 kb
Host smart-e29fee14-d84f-4627-b03d-2cfa047cf6ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9837662581662997544925804970099322852560865
4089853281152456862031242449406669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.9837
6625816629975449258049700993228525608654089853281152456862031242449406669
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.63140723327329978504943126113438954967502389152905128268586869189831328944843
Short name T721
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Oct 29 12:26:47 PM PDT 23
Finished Oct 29 12:26:52 PM PDT 23
Peak memory 200656 kb
Host smart-8cfbe655-6510-4aa6-9443-a984efe180af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63140723327329978504943126113438954967502389152905128268586869189831328944843 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.63140723327329978504943126113438954967502389152905128268586869189831328944843
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.111215621744049402154806399757486219592709760220810175071992057438300999318307
Short name T678
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 29 12:26:56 PM PDT 23
Finished Oct 29 12:27:00 PM PDT 23
Peak memory 200808 kb
Host smart-7cabe8fb-9af1-4fdf-b99e-0d41bed036e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111215621744049402154806399757486219592709760220810175071992057438300999318307 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.111215621744049402154806399757486219592709760220810175071992057438300999318307
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1060520989371181240589700525356220302232658022808540074670228848113740520463
Short name T58
Test name
Test status
Simulation time 2186637036 ps
CPU time 6.01 seconds
Started Oct 29 12:27:12 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200696 kb
Host smart-11ee2714-76a2-4833-bca5-55b0f7058fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060520989371181240589700525356220302232658022808540074670228848113740520463 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.1060520989371181240589700525356220302232658022808540074670228848113740520463
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.46933911157767224966370515894544466015472454023207522057556930590719693478907
Short name T713
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.25 seconds
Started Oct 29 12:26:44 PM PDT 23
Finished Oct 29 12:27:55 PM PDT 23
Peak memory 200400 kb
Host smart-94007bdb-6c1e-4db3-a7d9-f368ea6a224e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46933911157767224966370515894544466015472454023207522057556930590719693478907 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.469339111577672249663705158945444660154724540232075220575569305
90719693478907
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.54435396264161755489399453475636097438065306020700985476417387399237920172
Short name T79
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.61 seconds
Started Oct 29 12:26:58 PM PDT 23
Finished Oct 29 12:27:07 PM PDT 23
Peak memory 200952 kb
Host smart-0f398987-9a57-41e5-a4a8-4923ace20e76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54435396264161755489399453475636097438065306020700985476417387399237920172 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.54435396264161755489399453475636097438065306020700985476417387399237920172
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.86156155270107747372658790370364135708229721313524858447034252799409790332678
Short name T85
Test name
Test status
Simulation time 41047879715 ps
CPU time 115.01 seconds
Started Oct 29 12:27:21 PM PDT 23
Finished Oct 29 12:29:17 PM PDT 23
Peak memory 201056 kb
Host smart-67092f08-81b1-4afb-adb8-f0544f041f80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86156155270107747372658790370364135708229721313524858447034252799409790332678 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.86156155270107747372658790370364135708229721313524858447034252799409790332678
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.48724060977145241258348981329745952475059132333084710079266235880890236175541
Short name T65
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.24 seconds
Started Oct 29 12:27:21 PM PDT 23
Finished Oct 29 12:27:32 PM PDT 23
Peak memory 200972 kb
Host smart-d6f2d527-2adb-4a1e-b580-4081c40773a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48724060977145241258348981329745952475059132333084710079266235880890236175541 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.48724060977145241258348981329745952475059132333084710079266235880890236175541
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.53808836435675664297822476799573347584343366029365873931498786060753180367794
Short name T10
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.29 seconds
Started Oct 29 12:26:49 PM PDT 23
Finished Oct 29 12:26:53 PM PDT 23
Peak memory 199800 kb
Host smart-ee91fe36-e2ab-4b49-90d2-8471467c283a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5380883643567566429782247679957334758434336
6029365873931498786060753180367794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.5380
8836435675664297822476799573347584343366029365873931498786060753180367794
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.57293922197112420508573046605531898708797999871370908486276788434381227723587
Short name T690
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.12 seconds
Started Oct 29 12:26:48 PM PDT 23
Finished Oct 29 12:26:53 PM PDT 23
Peak memory 199388 kb
Host smart-cc74e515-7d96-4aac-b4ef-328bc73dbb8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57293922197112420508573046605531898708797999871370908486276788434381227723587 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.57293922197112420508573046605531898708797999871370908486276788434381227723587
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.80684305624793345338693703340329994677326174153846907331120221700920798372413
Short name T728
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 29 12:26:13 PM PDT 23
Finished Oct 29 12:26:18 PM PDT 23
Peak memory 200840 kb
Host smart-662ef5ca-5f21-467e-b824-7d6ea082ee14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80684305624793345338693703340329994677326174153846907331120221700920798372413 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.80684305624793345338693703340329994677326174153846907331120221700920798372413
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.70101765242889008375527234851148794308062971638122663208034217681363691403140
Short name T691
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.21 seconds
Started Oct 29 12:28:00 PM PDT 23
Finished Oct 29 12:28:25 PM PDT 23
Peak memory 201052 kb
Host smart-7b8ddcb1-8bed-46d9-b44d-4aafdda0f2ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70101765242889008375527234851148794308062971638122663208034217681363691403140
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.701017652428890083755272348511487943080629716
38122663208034217681363691403140
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.59088042639751556224101628907312068406661258282535637355994388936788625596521
Short name T766
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.14 seconds
Started Oct 29 12:26:48 PM PDT 23
Finished Oct 29 12:27:59 PM PDT 23
Peak memory 199740 kb
Host smart-c7f60b1d-3785-4a4f-8d76-b8243cbe6053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59088042639751556224101628907312068406661258282535637355994388936788625596521 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.590880426397515562241016289073120684066612582825356373559943889
36788625596521
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.100851404083054464622332851444754144278488384714347423614058415028938581716331
Short name T710
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.32 seconds
Started Oct 29 12:25:51 PM PDT 23
Finished Oct 29 12:25:56 PM PDT 23
Peak memory 200904 kb
Host smart-4313d2a3-2508-4c82-9f0d-47ec65044bba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008514040830544646223328514447541442784883
84714347423614058415028938581716331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.10
0851404083054464622332851444754144278488384714347423614058415028938581716331
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.85413153418497479515039755856013198934940955942429899420946804362446651689389
Short name T778
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.14 seconds
Started Oct 29 12:25:49 PM PDT 23
Finished Oct 29 12:25:54 PM PDT 23
Peak memory 200880 kb
Host smart-9aecaeea-4108-49ae-a41e-8be3e16fcb50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85413153418497479515039755856013198934940955942429899420946804362446651689389 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.85413153418497479515039755856013198934940955942429899420946804362446651689389
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.115546288272402908098708139476258253865087814912539374500013520340945652845077
Short name T717
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 29 12:26:03 PM PDT 23
Finished Oct 29 12:26:07 PM PDT 23
Peak memory 200824 kb
Host smart-fd6772bf-d6c2-429c-b4cb-7424730015c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115546288272402908098708139476258253865087814912539374500013520340945652845077 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.115546288272402908098708139476258253865087814912539374500013520340945652845077
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.76274677997611090348075595454973317282068737027341288217039666594525867060280
Short name T716
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.03 seconds
Started Oct 29 12:26:24 PM PDT 23
Finished Oct 29 12:26:49 PM PDT 23
Peak memory 201080 kb
Host smart-4ded1eb5-aa49-4f5f-a094-23955671967d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76274677997611090348075595454973317282068737027341288217039666594525867060280
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.76274677997611090348075595454973317282068737
027341288217039666594525867060280
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.58091878652381928593273619780584613190232856317858446432134173115434041867629
Short name T755
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.69 seconds
Started Oct 29 12:28:13 PM PDT 23
Finished Oct 29 12:28:20 PM PDT 23
Peak memory 201096 kb
Host smart-900df9d2-27e8-4a28-95cd-6f568463096e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58091878652381928593273619780584613190232856317858446432134173115434041867629 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.58091878652381928593273619780584613190232856317858446432134173115434041867629
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.34384731080120743948580601417556562420449672524609867664449931285692696182263
Short name T687
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.83 seconds
Started Oct 29 12:26:16 PM PDT 23
Finished Oct 29 12:27:29 PM PDT 23
Peak memory 201136 kb
Host smart-cc62fa75-6d1a-4410-941e-39c8e0c37f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34384731080120743948580601417556562420449672524609867664449931285692696182263 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.34384731080120743948580601417556562420449672524609867664449931
285692696182263
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.105089410659665033896787199255639608342541707186311474137285023497467575337841
Short name T771
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Oct 29 12:27:40 PM PDT 23
Finished Oct 29 12:27:44 PM PDT 23
Peak memory 200936 kb
Host smart-11737c69-4d34-4420-b97d-e09f9857c89b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050894106596650338967871992556396083425417
07186311474137285023497467575337841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.10
5089410659665033896787199255639608342541707186311474137285023497467575337841
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.100568833449057829394217659005333389830746566897785181932418026683957894236167
Short name T67
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.26 seconds
Started Oct 29 12:27:17 PM PDT 23
Finished Oct 29 12:27:22 PM PDT 23
Peak memory 200140 kb
Host smart-e9fb9e88-cc6b-4dc6-83c7-6541b4dda275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100568833449057829394217659005333389830746566897785181932418026683957894236167 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.100568833449057829394217659005333389830746566897785181932418026683957894236167
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.94725174228385840803871426789234901948638230089160880044300029571676991536936
Short name T688
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 29 12:25:49 PM PDT 23
Finished Oct 29 12:25:53 PM PDT 23
Peak memory 200840 kb
Host smart-d4ca7328-fca8-427a-84dc-9454435d5f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94725174228385840803871426789234901948638230089160880044300029571676991536936 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.94725174228385840803871426789234901948638230089160880044300029571676991536936
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.66276679130089951132039610905739806124885195453619506296937224162121618281147
Short name T89
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.37 seconds
Started Oct 29 12:26:50 PM PDT 23
Finished Oct 29 12:27:15 PM PDT 23
Peak memory 201020 kb
Host smart-fdfd362a-649a-4af2-91ac-2b6dd8a50ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66276679130089951132039610905739806124885195453619506296937224162121618281147
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.66276679130089951132039610905739806124885195
453619506296937224162121618281147
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.112414214528957477582359430799836455836735242341978846523354918913830165775596
Short name T56
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.67 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:21 PM PDT 23
Peak memory 201080 kb
Host smart-2664072b-9d66-4b16-81dd-f6b08513fd71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112414214528957477582359430799836455836735242341978846523354918913830165775596 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.112414214528957477582359430799836455836735242341978846523354918913830165775596
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.59756263322121904271309109171090404770214631941481311144722755266506022234169
Short name T53
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.37 seconds
Started Oct 29 12:26:29 PM PDT 23
Finished Oct 29 12:27:41 PM PDT 23
Peak memory 201132 kb
Host smart-5a32d6bf-1906-4cbc-aa05-44836949dbc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59756263322121904271309109171090404770214631941481311144722755266506022234169 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.59756263322121904271309109171090404770214631941481311144722755
266506022234169
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.9296295761977617023103072526720018669759624954328235619220781395974023397169
Short name T750
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Oct 29 12:27:19 PM PDT 23
Finished Oct 29 12:27:23 PM PDT 23
Peak memory 200752 kb
Host smart-19927cba-ecbe-4ad5-9876-128e417fe0bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9296295761977617023103072526720018669759624
954328235619220781395974023397169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.9296
295761977617023103072526720018669759624954328235619220781395974023397169
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.18740750677685690768560087419119387950658050945580492193978710164028402956462
Short name T64
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.09 seconds
Started Oct 29 12:27:09 PM PDT 23
Finished Oct 29 12:27:13 PM PDT 23
Peak memory 200840 kb
Host smart-6314daf9-e5db-47cd-b181-a4bfe05d2851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18740750677685690768560087419119387950658050945580492193978710164028402956462 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.18740750677685690768560087419119387950658050945580492193978710164028402956462
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.58652484565153580266686518091761297747938526920831684265608765564181977568256
Short name T742
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 29 12:26:55 PM PDT 23
Finished Oct 29 12:26:59 PM PDT 23
Peak memory 201100 kb
Host smart-b12441e1-21a1-4b8b-83f7-cf0e8749d63a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58652484565153580266686518091761297747938526920831684265608765564181977568256 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.58652484565153580266686518091761297747938526920831684265608765564181977568256
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.74660862335916402661167199368559492070951767587777722874137976767870486514741
Short name T743
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.42 seconds
Started Oct 29 12:27:18 PM PDT 23
Finished Oct 29 12:27:43 PM PDT 23
Peak memory 200892 kb
Host smart-89649f22-1586-4384-bca7-3dd4b1466571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74660862335916402661167199368559492070951767587777722874137976767870486514741
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.74660862335916402661167199368559492070951767
587777722874137976767870486514741
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.114299704143349052756939828588396775642798933044573945885423440297052977306701
Short name T54
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.96 seconds
Started Oct 29 12:25:54 PM PDT 23
Finished Oct 29 12:26:01 PM PDT 23
Peak memory 201096 kb
Host smart-fd790ede-a315-404c-84d0-f801221f4a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114299704143349052756939828588396775642798933044573945885423440297052977306701 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.114299704143349052756939828588396775642798933044573945885423440297052977306701
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.31982092207770572225022799450161972653615984965501610845895615989663646986739
Short name T700
Test name
Test status
Simulation time 42510939439 ps
CPU time 69 seconds
Started Oct 29 12:27:27 PM PDT 23
Finished Oct 29 12:28:36 PM PDT 23
Peak memory 201132 kb
Host smart-7805336c-f207-4859-9eeb-8fec4f9e0915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31982092207770572225022799450161972653615984965501610845895615989663646986739 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.31982092207770572225022799450161972653615984965501610845895615
989663646986739
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.62481004366814547368546881377996632943649789298792364754306692847604160178388
Short name T715
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.2 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:27:27 PM PDT 23
Peak memory 200920 kb
Host smart-dd918964-abda-4c39-a9ed-29dbb08ff469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6248100436681454736854688137799663294364978
9298792364754306692847604160178388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.624
81004366814547368546881377996632943649789298792364754306692847604160178388
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.113164955455362421126185655916856439953379733640423538939684332991136163440754
Short name T685
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.34 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:15 PM PDT 23
Peak memory 198744 kb
Host smart-39fe93e2-c954-40e3-b665-12ab160d421b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113164955455362421126185655916856439953379733640423538939684332991136163440754 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.113164955455362421126185655916856439953379733640423538939684332991136163440754
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.101580550919838061333128731118389964250113341561189616488367811149983763587900
Short name T689
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 29 12:27:18 PM PDT 23
Finished Oct 29 12:27:22 PM PDT 23
Peak memory 200640 kb
Host smart-eb82faa9-2e7f-4675-8681-dda22e2034c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101580550919838061333128731118389964250113341561189616488367811149983763587900 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.101580550919838061333128731118389964250113341561189616488367811149983763587900
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.83495636262822881178878733108240312770028248576616865488614823994509602473458
Short name T782
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.3 seconds
Started Oct 29 12:27:18 PM PDT 23
Finished Oct 29 12:27:42 PM PDT 23
Peak memory 200776 kb
Host smart-c69485cc-1051-414a-8a26-2f966bc48a85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83495636262822881178878733108240312770028248576616865488614823994509602473458
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.83495636262822881178878733108240312770028248
576616865488614823994509602473458
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.91315707539839828250601872379982332833043117814898174493281413313251782646513
Short name T59
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.63 seconds
Started Oct 29 12:27:19 PM PDT 23
Finished Oct 29 12:27:25 PM PDT 23
Peak memory 200924 kb
Host smart-84548c68-692f-4027-b7b7-27ac8081ee8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91315707539839828250601872379982332833043117814898174493281413313251782646513 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.91315707539839828250601872379982332833043117814898174493281413313251782646513
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.86123880261557501628731911712318379352459094170449007771615563840570708255549
Short name T712
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.32 seconds
Started Oct 29 12:25:57 PM PDT 23
Finished Oct 29 12:27:07 PM PDT 23
Peak memory 201088 kb
Host smart-22578520-279b-4971-ba28-d6e5ca7c52d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86123880261557501628731911712318379352459094170449007771615563840570708255549 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.86123880261557501628731911712318379352459094170449007771615563
840570708255549
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.6671370778963890211398861733551059190503812879479863728028891285885040118719
Short name T739
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.12 seconds
Started Oct 29 12:27:05 PM PDT 23
Finished Oct 29 12:27:10 PM PDT 23
Peak memory 200724 kb
Host smart-8153bd7a-c548-4233-9105-cfe0ed6191a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6671370778963890211398861733551059190503812
879479863728028891285885040118719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.6671
370778963890211398861733551059190503812879479863728028891285885040118719
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.32747261744931866273744047085860661081904120161756489188362820542574182379284
Short name T69
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Oct 29 12:26:51 PM PDT 23
Finished Oct 29 12:26:56 PM PDT 23
Peak memory 200680 kb
Host smart-d5e43e00-3ad7-4409-9cab-01935647a32f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32747261744931866273744047085860661081904120161756489188362820542574182379284 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.32747261744931866273744047085860661081904120161756489188362820542574182379284
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.6835868827529897513041583586410734207336480479726563837163174709255305331347
Short name T88
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.72 seconds
Started Oct 29 12:26:00 PM PDT 23
Finished Oct 29 12:26:25 PM PDT 23
Peak memory 201424 kb
Host smart-3ca536ea-1715-4cd4-b77c-c9e2d70c61ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6835868827529897513041583586410734207336480479726563837163174709255305331347 -
assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.683586882752989751304158358641073420733648047
9726563837163174709255305331347
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.12953703784015857946732294507490895403341876299674557719579709079848311592995
Short name T765
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.56 seconds
Started Oct 29 12:27:19 PM PDT 23
Finished Oct 29 12:27:25 PM PDT 23
Peak memory 200924 kb
Host smart-b31a1bf2-8fd1-4459-b915-9ecd8501d750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12953703784015857946732294507490895403341876299674557719579709079848311592995 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.12953703784015857946732294507490895403341876299674557719579709079848311592995
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.5967927957966078134944330534870982397587301768282516988750636410543367753292
Short name T696
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.28 seconds
Started Oct 29 12:26:14 PM PDT 23
Finished Oct 29 12:26:20 PM PDT 23
Peak memory 200864 kb
Host smart-c15d2dd9-b0d3-4eba-86ab-6dde9a5f4801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5967927957966078134944330534870982397587301
768282516988750636410543367753292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.5967
927957966078134944330534870982397587301768282516988750636410543367753292
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.89216108965542246027228099707018906799451365362401659690247046121409767375234
Short name T747
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.01 seconds
Started Oct 29 12:28:53 PM PDT 23
Finished Oct 29 12:28:57 PM PDT 23
Peak memory 200660 kb
Host smart-a0202498-a613-4e59-a700-332b6fe52449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89216108965542246027228099707018906799451365362401659690247046121409767375234 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.89216108965542246027228099707018906799451365362401659690247046121409767375234
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.93107590188985563470424665929492916382669280815401683486180091712741216156039
Short name T679
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:28:58 PM PDT 23
Peak memory 200624 kb
Host smart-c61b6645-9b5d-4ff7-a363-a9961f17e9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93107590188985563470424665929492916382669280815401683486180091712741216156039 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.93107590188985563470424665929492916382669280815401683486180091712741216156039
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.64034808949721237334878420426306914586052942244013086019096551703819684800693
Short name T682
Test name
Test status
Simulation time 9477310853 ps
CPU time 23.91 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 200872 kb
Host smart-ca3709bc-c741-4986-96a6-2a1c375b606d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64034808949721237334878420426306914586052942244013086019096551703819684800693
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.64034808949721237334878420426306914586052942
244013086019096551703819684800693
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.90619927490215309337098003030170714933074641792365004453433156874384296347469
Short name T767
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.84 seconds
Started Oct 29 12:26:14 PM PDT 23
Finished Oct 29 12:26:21 PM PDT 23
Peak memory 201036 kb
Host smart-dd0b1b4a-1f5f-416c-8991-3743d4798aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90619927490215309337098003030170714933074641792365004453433156874384296347469 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.90619927490215309337098003030170714933074641792365004453433156874384296347469
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.5359507587784647484578061173479327295342709805789492074387362781545121240684
Short name T722
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.82 seconds
Started Oct 29 12:28:43 PM PDT 23
Finished Oct 29 12:29:54 PM PDT 23
Peak memory 200012 kb
Host smart-6aa5fcce-e149-4d91-89f3-3de2ed2ccaa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5359507587784647484578061173479327295342709805789492074387362781545121240684 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.535950758778464748457806117347932729534270980578949207438736278
1545121240684
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.18492911627494540419214551243471254376546808435663431472102174541223219763770
Short name T754
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.72 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:16 PM PDT 23
Peak memory 198944 kb
Host smart-ce5bd2fd-4b45-4de4-9484-bbb05e2ffd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849291162749454041921455124347125437654680
8435663431472102174541223219763770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.184
92911627494540419214551243471254376546808435663431472102174541223219763770
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.40873523801773902597829029052803000227977937051405090843038971191197952180300
Short name T731
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.32 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:15 PM PDT 23
Peak memory 198664 kb
Host smart-a3287231-fd5b-4332-b358-5b6cf95176c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873523801773902597829029052803000227977937051405090843038971191197952180300 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.40873523801773902597829029052803000227977937051405090843038971191197952180300
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.36212280584545398249163300837851019807928503075368609547784225862891170948813
Short name T74
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 29 12:27:20 PM PDT 23
Finished Oct 29 12:27:25 PM PDT 23
Peak memory 200808 kb
Host smart-54071e60-20cb-4260-b380-d3d204fe0e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212280584545398249163300837851019807928503075368609547784225862891170948813 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.36212280584545398249163300837851019807928503075368609547784225862891170948813
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.104896825961338291874160225516187133483276440418908971273699345154986253221516
Short name T773
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.6 seconds
Started Oct 29 12:26:14 PM PDT 23
Finished Oct 29 12:26:41 PM PDT 23
Peak memory 201020 kb
Host smart-b0ef1c26-fa7f-4ba6-ab3d-106393378823
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104896825961338291874160225516187133483276440418908971273699345154986253221516
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.1048968259613382918741602255161871334832764
40418908971273699345154986253221516
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.86796427877342593562923662067197257273533195550824506140224689702271043928508
Short name T5
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.87 seconds
Started Oct 29 12:28:08 PM PDT 23
Finished Oct 29 12:28:17 PM PDT 23
Peak memory 200112 kb
Host smart-6bebb62f-7758-425a-986c-09039ec0dd0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86796427877342593562923662067197257273533195550824506140224689702271043928508 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.86796427877342593562923662067197257273533195550824506140224689702271043928508
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.115750757980051561861838853634913209791697828253481867736049521040496700850192
Short name T735
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.37 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:30:05 PM PDT 23
Peak memory 200932 kb
Host smart-fae856d4-5ff7-4563-ac62-aaed1493bfbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115750757980051561861838853634913209791697828253481867736049521040496700850192 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1157507579800515618618388536349132097916978282534818677360495
21040496700850192
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.92412172968277192733813351274154318262412025310249780927476499737693716852888
Short name T770
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.25 seconds
Started Oct 29 12:26:59 PM PDT 23
Finished Oct 29 12:27:04 PM PDT 23
Peak memory 200936 kb
Host smart-fc057fba-1055-49a6-b964-f72dad7a9b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9241217296827719273381335127415431826241202
5310249780927476499737693716852888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.924
12172968277192733813351274154318262412025310249780927476499737693716852888
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.37508304659848254834785095605863221560202057005399048637409919973072617238262
Short name T724
Test name
Test status
Simulation time 2074977215 ps
CPU time 4 seconds
Started Oct 29 12:27:32 PM PDT 23
Finished Oct 29 12:27:36 PM PDT 23
Peak memory 200780 kb
Host smart-776cd6a4-ef93-4ffb-bd63-82c7c3a8e70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37508304659848254834785095605863221560202057005399048637409919973072617238262 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.37508304659848254834785095605863221560202057005399048637409919973072617238262
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.38476090334891615439098078064384983428624829328593292290551590185752626807084
Short name T741
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.67 seconds
Started Oct 29 12:27:32 PM PDT 23
Finished Oct 29 12:27:36 PM PDT 23
Peak memory 200744 kb
Host smart-4a7bab84-5f0b-43ad-b9d0-8c16d08944d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476090334891615439098078064384983428624829328593292290551590185752626807084 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.38476090334891615439098078064384983428624829328593292290551590185752626807084
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.77057405366480959767373599990780128010850691013671773252600390079497338813210
Short name T729
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.19 seconds
Started Oct 29 12:27:34 PM PDT 23
Finished Oct 29 12:27:59 PM PDT 23
Peak memory 201076 kb
Host smart-abfdae53-6228-4fb5-be88-35422c7db259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77057405366480959767373599990780128010850691013671773252600390079497338813210
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.77057405366480959767373599990780128010850691
013671773252600390079497338813210
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.9509723032675110145531836204792773381940611646591487735994649583652181484281
Short name T764
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.96 seconds
Started Oct 29 12:27:48 PM PDT 23
Finished Oct 29 12:27:55 PM PDT 23
Peak memory 201092 kb
Host smart-ead6265b-81aa-42fa-9789-3f3af6345d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9509723032675110145531836204792773381940611646591487735994649583652181484281 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.9509723032675110145531836204792773381940611646591487735994649583652181484281
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.53769716450479365662585404065665529161394800632376482028560696393143889577918
Short name T727
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.38 seconds
Started Oct 29 12:26:19 PM PDT 23
Finished Oct 29 12:27:29 PM PDT 23
Peak memory 201132 kb
Host smart-e00643c0-3d16-4d0b-9774-ead48e1510f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53769716450479365662585404065665529161394800632376482028560696393143889577918 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.53769716450479365662585404065665529161394800632376482028560696
393143889577918
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.75537590014876717051015873372445860621829220338277285222793693658505231548611
Short name T673
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.28 seconds
Started Oct 29 12:26:57 PM PDT 23
Finished Oct 29 12:27:02 PM PDT 23
Peak memory 201196 kb
Host smart-4e3c43d6-98d9-410a-bd07-c984cececd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7553759001487671705101587337244586062182922
0338277285222793693658505231548611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.755
37590014876717051015873372445860621829220338277285222793693658505231548611
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.32823200089795175869459683754499933477059185887264305433482022478496315615312
Short name T684
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.13 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 200104 kb
Host smart-1b1d6912-c8ff-4927-82a2-612a1cf75d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32823200089795175869459683754499933477059185887264305433482022478496315615312 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.32823200089795175869459683754499933477059185887264305433482022478496315615312
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.100145164752615516490291097065431733439100875847678063589733410921136843637680
Short name T726
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.8 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:43 PM PDT 23
Peak memory 200188 kb
Host smart-2e56373f-f783-415b-8584-064413b92c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100145164752615516490291097065431733439100875847678063589733410921136843637680 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.100145164752615516490291097065431733439100875847678063589733410921136843637680
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.99094285648779583111737677263671557867264520361641681705413334702623309754457
Short name T719
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.13 seconds
Started Oct 29 12:27:50 PM PDT 23
Finished Oct 29 12:28:16 PM PDT 23
Peak memory 200860 kb
Host smart-65d03f8c-08e3-4743-80c0-0068de3cee96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99094285648779583111737677263671557867264520361641681705413334702623309754457
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.99094285648779583111737677263671557867264520
361641681705413334702623309754457
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.40979854561560319865969450808988265455972836080760136843870850955096928130472
Short name T734
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.87 seconds
Started Oct 29 12:27:04 PM PDT 23
Finished Oct 29 12:27:10 PM PDT 23
Peak memory 201036 kb
Host smart-790a0b67-3d1f-47c2-8051-6c5f90466fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40979854561560319865969450808988265455972836080760136843870850955096928130472 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.40979854561560319865969450808988265455972836080760136843870850955096928130472
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.87590300110302440246289370051626457617214219963193230153818213919987610531193
Short name T3
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.93 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:29:17 PM PDT 23
Peak memory 200904 kb
Host smart-c2453c9e-d8a2-4d81-bda0-da87b798aebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87590300110302440246289370051626457617214219963193230153818213919987610531193 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.87590300110302440246289370051626457617214219963193230153818213
919987610531193
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.32883684228543872533093974018244450202950586224379349511064256853902665220376
Short name T7
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.29 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:20 PM PDT 23
Peak memory 200880 kb
Host smart-149b897f-6639-4058-8f6d-4f65ea258b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288368422854387253309397401824445020295058
6224379349511064256853902665220376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.328
83684228543872533093974018244450202950586224379349511064256853902665220376
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.59617908660042673718388398833139425491104737382784017100835167766255554613234
Short name T683
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.18 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 199868 kb
Host smart-443d77a9-99b3-49f6-bc67-89891259ae42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59617908660042673718388398833139425491104737382784017100835167766255554613234 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.59617908660042673718388398833139425491104737382784017100835167766255554613234
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.40407484962496367735513545925455526434415731673928709983940112611868823595198
Short name T714
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.81 seconds
Started Oct 29 12:28:40 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 200576 kb
Host smart-b40c54d6-af04-4b8c-92d4-89720e02d460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40407484962496367735513545925455526434415731673928709983940112611868823595198 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.40407484962496367735513545925455526434415731673928709983940112611868823595198
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.46762600258111682432064193423345029282227508690108611617636749921532420386769
Short name T725
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.34 seconds
Started Oct 29 12:27:00 PM PDT 23
Finished Oct 29 12:27:25 PM PDT 23
Peak memory 201060 kb
Host smart-3aa593e3-526f-42d4-bd13-8fac02cc3c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46762600258111682432064193423345029282227508690108611617636749921532420386769
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.46762600258111682432064193423345029282227508
690108611617636749921532420386769
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.39681790597829530357172416221822354855534551265484988833010197476536159601323
Short name T772
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.76 seconds
Started Oct 29 12:27:20 PM PDT 23
Finished Oct 29 12:27:27 PM PDT 23
Peak memory 201088 kb
Host smart-30d42b55-2574-40a0-a018-f512a90b33c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39681790597829530357172416221822354855534551265484988833010197476536159601323 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.39681790597829530357172416221822354855534551265484988833010197476536159601323
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.82525784893892236550833496804765841809090174968039579779457408602695310099233
Short name T737
Test name
Test status
Simulation time 42510939439 ps
CPU time 71.57 seconds
Started Oct 29 12:27:33 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201132 kb
Host smart-240dee5b-7b1b-4225-bc15-27cf05b4e5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82525784893892236550833496804765841809090174968039579779457408602695310099233 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.82525784893892236550833496804765841809090174968039579779457408
602695310099233
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.62770192197073821364197390091314848127428784754950380367643865365656861109019
Short name T83
Test name
Test status
Simulation time 41047879715 ps
CPU time 111.71 seconds
Started Oct 29 12:26:57 PM PDT 23
Finished Oct 29 12:28:49 PM PDT 23
Peak memory 200300 kb
Host smart-4ba3d911-c659-4492-92e6-04f2be5cb2e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62770192197073821364197390091314848127428784754950380367643865365656861109019 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.62770192197073821364197390091314848127428784754950380367643865365656861109019
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.25245316351151554985168951953488440813507491617880196562270743455401532893659
Short name T68
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.16 seconds
Started Oct 29 12:26:57 PM PDT 23
Finished Oct 29 12:27:08 PM PDT 23
Peak memory 200768 kb
Host smart-18b8508b-c4a3-43e2-a919-17b326c36019
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245316351151554985168951953488440813507491617880196562270743455401532893659 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.25245316351151554985168951953488440813507491617880196562270743455401532893659
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.25328328626743172195685027840625386100777447235561414366616386897449918869251
Short name T6
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.24 seconds
Started Oct 29 12:27:01 PM PDT 23
Finished Oct 29 12:27:05 PM PDT 23
Peak memory 200760 kb
Host smart-4f4c8534-1775-4bcc-9f3e-1f1621e564f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532832862674317219568502784062538610077744
7235561414366616386897449918869251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2532
8328626743172195685027840625386100777447235561414366616386897449918869251
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.59453859045696784724325337947925957771718131197719144208590401988783872874612
Short name T702
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.07 seconds
Started Oct 29 12:26:59 PM PDT 23
Finished Oct 29 12:27:03 PM PDT 23
Peak memory 200676 kb
Host smart-351dab72-064c-48f6-9b8d-f298894832c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59453859045696784724325337947925957771718131197719144208590401988783872874612 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.59453859045696784724325337947925957771718131197719144208590401988783872874612
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.6701906609258280736097113386760253591635078868619605954045045242321393529889
Short name T76
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 29 12:25:07 PM PDT 23
Finished Oct 29 12:25:11 PM PDT 23
Peak memory 200780 kb
Host smart-4afb8641-58f8-4121-8c2a-98d6af91b1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6701906609258280736097113386760253591635078868619605954045045242321393529889 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.6701906609258280736097113386760253591635078868619605954045045242321393529889
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.113988886532474216345186542648683543932265640164598498183585031417013941924803
Short name T14
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.44 seconds
Started Oct 29 12:24:50 PM PDT 23
Finished Oct 29 12:25:18 PM PDT 23
Peak memory 201016 kb
Host smart-2d6fa1d6-ee81-4007-aa5d-ffc9c66e1235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113988886532474216345186542648683543932265640164598498183585031417013941924803
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.11398888653247421634518654264868354393226564
0164598498183585031417013941924803
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.18858600764977858619140105434333340276315769874342567443216337137724581948969
Short name T50
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.72 seconds
Started Oct 29 12:26:49 PM PDT 23
Finished Oct 29 12:26:55 PM PDT 23
Peak memory 199972 kb
Host smart-6772d410-0a73-42b6-a594-f1fd19378cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858600764977858619140105434333340276315769874342567443216337137724581948969 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.18858600764977858619140105434333340276315769874342567443216337137724581948969
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.25688064330067292040434818432651044922533056673268589021422873629562347845312
Short name T708
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.4 seconds
Started Oct 29 12:26:05 PM PDT 23
Finished Oct 29 12:27:16 PM PDT 23
Peak memory 201400 kb
Host smart-2473946b-76b0-4129-a69b-72a4707eb433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688064330067292040434818432651044922533056673268589021422873629562347845312 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.256880643300672920404348184326510449225330566732685890214228736
29562347845312
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.90165079382914122935151056065243708025698546738750840832797968118821325763878
Short name T732
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 29 12:27:16 PM PDT 23
Finished Oct 29 12:27:20 PM PDT 23
Peak memory 200816 kb
Host smart-318620fc-e1e2-47ce-a719-6e4bb9128681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90165079382914122935151056065243708025698546738750840832797968118821325763878 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.90165079382914122935151056065243708025698546738750840832797968118821325763878
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.96236588952511530299895815064697085197148435720203147807183373520667796144592
Short name T11
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200660 kb
Host smart-c94abb38-89c1-4b7a-8bf3-b0e7008e9e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96236588952511530299895815064697085197148435720203147807183373520667796144592 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.96236588952511530299895815064697085197148435720203147807183373520667796144592
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.39664846956826818386882373381143675542829072915948370524504260729021124220188
Short name T781
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.83 seconds
Started Oct 29 12:27:10 PM PDT 23
Finished Oct 29 12:27:14 PM PDT 23
Peak memory 201108 kb
Host smart-999e3e93-cb26-4f73-85a6-f51abd998dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664846956826818386882373381143675542829072915948370524504260729021124220188 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.39664846956826818386882373381143675542829072915948370524504260729021124220188
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.67131838341373507514583708445256137791553348352009080216704857632095756018057
Short name T733
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.84 seconds
Started Oct 29 12:27:48 PM PDT 23
Finished Oct 29 12:27:53 PM PDT 23
Peak memory 200812 kb
Host smart-0c9fe626-8687-4cda-8bda-066edf8d52ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67131838341373507514583708445256137791553348352009080216704857632095756018057 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.67131838341373507514583708445256137791553348352009080216704857632095756018057
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.69100237616557095249643930575559299384246144647176215210605644571400390846256
Short name T677
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200680 kb
Host smart-66bdc488-de5f-44f0-9ca1-f7414375ef42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69100237616557095249643930575559299384246144647176215210605644571400390846256 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.69100237616557095249643930575559299384246144647176215210605644571400390846256
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.11824666287931097530304862088332748884669920826989707854500448634945002601648
Short name T780
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:28:58 PM PDT 23
Peak memory 200624 kb
Host smart-22f7befa-6bee-45f2-b6f0-2bc9309e07ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11824666287931097530304862088332748884669920826989707854500448634945002601648 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.11824666287931097530304862088332748884669920826989707854500448634945002601648
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.85789935937574068340978662663820171644596774354724016597955018881802466278518
Short name T704
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.88 seconds
Started Oct 29 12:27:05 PM PDT 23
Finished Oct 29 12:27:09 PM PDT 23
Peak memory 200816 kb
Host smart-5ebf48a8-42d6-4487-ac5d-0f887444c704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85789935937574068340978662663820171644596774354724016597955018881802466278518 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.85789935937574068340978662663820171644596774354724016597955018881802466278518
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.82900589762696548315622506035270211569413252522843854616248610764863889502326
Short name T740
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 29 12:27:07 PM PDT 23
Finished Oct 29 12:27:11 PM PDT 23
Peak memory 200092 kb
Host smart-eb5dfd14-9fb7-4f92-b012-068985e1e9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82900589762696548315622506035270211569413252522843854616248610764863889502326 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.82900589762696548315622506035270211569413252522843854616248610764863889502326
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.10012321495163460971355681158350967341359752545855958794180541586668493685379
Short name T723
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.81 seconds
Started Oct 29 12:29:06 PM PDT 23
Finished Oct 29 12:29:10 PM PDT 23
Peak memory 200800 kb
Host smart-88022c09-af69-4fd4-a619-7bf270f3cc82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012321495163460971355681158350967341359752545855958794180541586668493685379 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.10012321495163460971355681158350967341359752545855958794180541586668493685379
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.100021720595503960975181258652475115018188591651759641311490664476127066419180
Short name T77
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200808 kb
Host smart-fbf65182-f317-4b28-af4d-4aa4c178a5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100021720595503960975181258652475115018188591651759641311490664476127066419180 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.100021720595503960975181258652475115018188591651759641311490664476127066419180
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.62091160196449543666221040351440853848296666030649663117931157008205632927317
Short name T72
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.94 seconds
Started Oct 29 12:25:55 PM PDT 23
Finished Oct 29 12:26:04 PM PDT 23
Peak memory 201092 kb
Host smart-ba623603-4662-4825-bd61-cc985567a17c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62091160196449543666221040351440853848296666030649663117931157008205632927317 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.62091160196449543666221040351440853848296666030649663117931157008205632927317
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.75844840746053995990158937162102836717019585280239310520526344521907736881887
Short name T82
Test name
Test status
Simulation time 41047879715 ps
CPU time 116.28 seconds
Started Oct 29 12:25:13 PM PDT 23
Finished Oct 29 12:27:10 PM PDT 23
Peak memory 201068 kb
Host smart-6b043f74-154b-4807-ab88-3db92a64c20e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75844840746053995990158937162102836717019585280239310520526344521907736881887 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.75844840746053995990158937162102836717019585280239310520526344521907736881887
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.115547461458050422296353466270435902545792888866331729283755570954150250761623
Short name T70
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.42 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:21 PM PDT 23
Peak memory 198960 kb
Host smart-eaf41ff7-1f05-493e-8181-ecc7afca2158
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115547461458050422296353466270435902545792888866331729283755570954150250761623 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.1155474614580504222963534662704359025457928888663317292837555709
54150250761623
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.72912550205636437037872476765488082995588335366837229323264817896929105586549
Short name T701
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.11 seconds
Started Oct 29 12:27:21 PM PDT 23
Finished Oct 29 12:27:26 PM PDT 23
Peak memory 200908 kb
Host smart-df203e10-8c3e-40d3-9eea-24a309d69ba6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7291255020563643703787247676548808299558833
5366837229323264817896929105586549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.7291
2550205636437037872476765488082995588335366837229323264817896929105586549
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.18590907832652781975412418439652136661853141354317367818447653375208381748797
Short name T707
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.16 seconds
Started Oct 29 12:26:40 PM PDT 23
Finished Oct 29 12:26:46 PM PDT 23
Peak memory 199204 kb
Host smart-c608cfa9-247e-405d-a9fc-58f636f6aefc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18590907832652781975412418439652136661853141354317367818447653375208381748797 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.18590907832652781975412418439652136661853141354317367818447653375208381748797
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.109555787659431530105350900408568560020667837475123276092359257328665479058473
Short name T758
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.89 seconds
Started Oct 29 12:27:14 PM PDT 23
Finished Oct 29 12:27:18 PM PDT 23
Peak memory 200644 kb
Host smart-76ae0575-44c0-4a6c-bd23-d3174fd4e1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109555787659431530105350900408568560020667837475123276092359257328665479058473 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.109555787659431530105350900408568560020667837475123276092359257328665479058473
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.111512979836791960401363833279683444249347882218497117821545927027831641847119
Short name T13
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.99 seconds
Started Oct 29 12:25:14 PM PDT 23
Finished Oct 29 12:25:41 PM PDT 23
Peak memory 201344 kb
Host smart-558c5fbf-a846-4b3e-88ec-5c4331b20a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111512979836791960401363833279683444249347882218497117821545927027831641847119
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.11151297983679196040136383327968344424934788
2218497117821545927027831641847119
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.90374568538780407169732116716894499890084523147272784298783430681545797861599
Short name T2
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Oct 29 12:26:55 PM PDT 23
Finished Oct 29 12:27:01 PM PDT 23
Peak memory 201060 kb
Host smart-716ec391-48a3-4a74-80b8-64ef3f3b0c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90374568538780407169732116716894499890084523147272784298783430681545797861599 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.90374568538780407169732116716894499890084523147272784298783430681545797861599
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.59501360991101202170390751587962977289941411790319853535015190784010297594315
Short name T744
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.36 seconds
Started Oct 29 12:26:55 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 201096 kb
Host smart-169b991c-bc40-494e-8c22-fc5d54f06f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59501360991101202170390751587962977289941411790319853535015190784010297594315 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.595013609911012021703907515879629772899414117903198535350151907
84010297594315
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.78454657314770911147833124558631331988089408994663199559834425171230609841478
Short name T143
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200816 kb
Host smart-022c2748-c108-46a4-bb06-8802dd2a3587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78454657314770911147833124558631331988089408994663199559834425171230609841478 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.78454657314770911147833124558631331988089408994663199559834425171230609841478
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.48081152208684483580052720828839169894413323601429579159865372071172452562019
Short name T675
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200788 kb
Host smart-2764e6a7-33a4-4220-82b6-da17f067f179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48081152208684483580052720828839169894413323601429579159865372071172452562019 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.48081152208684483580052720828839169894413323601429579159865372071172452562019
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.14942474032654358164703728545178032297596099664204160329506422446671375620647
Short name T769
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.78 seconds
Started Oct 29 12:27:15 PM PDT 23
Finished Oct 29 12:27:19 PM PDT 23
Peak memory 200788 kb
Host smart-fdba772b-7954-474f-b581-929478ba0b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14942474032654358164703728545178032297596099664204160329506422446671375620647 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.14942474032654358164703728545178032297596099664204160329506422446671375620647
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.37334975776895918073278590505292145878994248095062961274714024358470410777853
Short name T706
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 29 12:27:09 PM PDT 23
Finished Oct 29 12:27:13 PM PDT 23
Peak memory 200644 kb
Host smart-5fb53e39-982d-49c2-bbe0-0cb1dac8ece1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334975776895918073278590505292145878994248095062961274714024358470410777853 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.37334975776895918073278590505292145878994248095062961274714024358470410777853
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.39210560419094884862348027496585345788250383589532822563479277583613880881662
Short name T12
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.91 seconds
Started Oct 29 12:27:50 PM PDT 23
Finished Oct 29 12:27:55 PM PDT 23
Peak memory 200632 kb
Host smart-ce5e2217-b000-4f96-9862-4eccc9839cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39210560419094884862348027496585345788250383589532822563479277583613880881662 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.39210560419094884862348027496585345788250383589532822563479277583613880881662
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.19376284140256201349406050277070136589778973481253292238146304110789412855226
Short name T751
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 29 12:27:55 PM PDT 23
Finished Oct 29 12:28:01 PM PDT 23
Peak memory 200800 kb
Host smart-72105068-2ac7-44ae-b923-a168a30aa1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376284140256201349406050277070136589778973481253292238146304110789412855226 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.19376284140256201349406050277070136589778973481253292238146304110789412855226
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.83650664302198228081613175742128814557027305218065967018046838447149640362951
Short name T746
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.96 seconds
Started Oct 29 12:27:14 PM PDT 23
Finished Oct 29 12:27:18 PM PDT 23
Peak memory 200816 kb
Host smart-f1104e95-5a9f-4041-8efb-591aac169368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83650664302198228081613175742128814557027305218065967018046838447149640362951 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.83650664302198228081613175742128814557027305218065967018046838447149640362951
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3878015759956013953505311128535241837602296788363845467526554827093573718314
Short name T777
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.81 seconds
Started Oct 29 12:28:47 PM PDT 23
Finished Oct 29 12:28:51 PM PDT 23
Peak memory 200596 kb
Host smart-420ab27f-231c-4b31-8391-e03ac6c2695a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878015759956013953505311128535241837602296788363845467526554827093573718314 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.3878015759956013953505311128535241837602296788363845467526554827093573718314
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.75853268856396933570638656882588939009184194289954109577150944056803440553438
Short name T686
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.86 seconds
Started Oct 29 12:27:48 PM PDT 23
Finished Oct 29 12:27:53 PM PDT 23
Peak memory 200816 kb
Host smart-7aab266a-7823-4aa2-9edd-d1f348bd99d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75853268856396933570638656882588939009184194289954109577150944056803440553438 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.75853268856396933570638656882588939009184194289954109577150944056803440553438
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.84296359293313666589421472059686451951440771209028786876213189674872050730088
Short name T749
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 29 12:27:54 PM PDT 23
Finished Oct 29 12:28:01 PM PDT 23
Peak memory 200760 kb
Host smart-bcec55e7-0a9b-4ad9-9c05-d2fb1fc993e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84296359293313666589421472059686451951440771209028786876213189674872050730088 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.84296359293313666589421472059686451951440771209028786876213189674872050730088
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.83419151907892974522475960810928480859070586177087383566696229296757033612698
Short name T66
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.35 seconds
Started Oct 29 12:27:07 PM PDT 23
Finished Oct 29 12:27:15 PM PDT 23
Peak memory 200912 kb
Host smart-d67cddb1-7b56-40c6-bb58-c8435de011d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83419151907892974522475960810928480859070586177087383566696229296757033612698 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.83419151907892974522475960810928480859070586177087383566696229296757033612698
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.47161873410048257785097669500432415365418739962480839537120298991950209010544
Short name T81
Test name
Test status
Simulation time 41047879715 ps
CPU time 111.89 seconds
Started Oct 29 12:27:44 PM PDT 23
Finished Oct 29 12:29:36 PM PDT 23
Peak memory 200992 kb
Host smart-7f724faf-acd1-4f62-a9d6-fa697929f7f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47161873410048257785097669500432415365418739962480839537120298991950209010544 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.47161873410048257785097669500432415365418739962480839537120298991950209010544
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.68234849326702074883870790428891855694990555581660982151715418771204549628024
Short name T763
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.25 seconds
Started Oct 29 12:25:30 PM PDT 23
Finished Oct 29 12:25:41 PM PDT 23
Peak memory 201252 kb
Host smart-e93fd30e-7227-46b9-a4e2-aa5062549627
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68234849326702074883870790428891855694990555581660982151715418771204549628024 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.68234849326702074883870790428891855694990555581660982151715418771204549628024
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.97106634158171463038088523105099586451405902572874689933379545167023287786741
Short name T757
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.28 seconds
Started Oct 29 12:27:05 PM PDT 23
Finished Oct 29 12:27:09 PM PDT 23
Peak memory 200204 kb
Host smart-9ec94fe1-ebca-405c-b37a-4559505855f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9710663415817146303808852310509958645140590
2572874689933379545167023287786741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.9710
6634158171463038088523105099586451405902572874689933379545167023287786741
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.46764106041053324005293813693525311737857573488037186599801625275975548032139
Short name T698
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.13 seconds
Started Oct 29 12:27:05 PM PDT 23
Finished Oct 29 12:27:10 PM PDT 23
Peak memory 201152 kb
Host smart-4ee53d2b-f498-4154-aefa-4c091cb71c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46764106041053324005293813693525311737857573488037186599801625275975548032139 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.46764106041053324005293813693525311737857573488037186599801625275975548032139
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.20109373682899048203206587057247601036485707549057871547857405190990725377746
Short name T676
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.81 seconds
Started Oct 29 12:27:57 PM PDT 23
Finished Oct 29 12:28:01 PM PDT 23
Peak memory 201108 kb
Host smart-b2222914-edb4-42fa-a1de-b1bb66c37556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20109373682899048203206587057247601036485707549057871547857405190990725377746 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.20109373682899048203206587057247601036485707549057871547857405190990725377746
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.43495940574465687857428914556571397854846811190912975568166079387085515413603
Short name T60
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.59 seconds
Started Oct 29 12:27:26 PM PDT 23
Finished Oct 29 12:27:51 PM PDT 23
Peak memory 200876 kb
Host smart-da9e0ef5-246e-42cf-bec8-cf6524a0161a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43495940574465687857428914556571397854846811190912975568166079387085515413603
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.434959405744656878574289145565713978548468111
90912975568166079387085515413603
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.44405985098237562038091676030674703863533574040082130980337290026496986243091
Short name T55
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.68 seconds
Started Oct 29 12:26:40 PM PDT 23
Finished Oct 29 12:26:47 PM PDT 23
Peak memory 199444 kb
Host smart-57f22a7c-601f-41c7-882a-190c726b4200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44405985098237562038091676030674703863533574040082130980337290026496986243091 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.44405985098237562038091676030674703863533574040082130980337290026496986243091
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.36526297281338468230177869903404013920747758513802384491314510846199075588960
Short name T75
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.51 seconds
Started Oct 29 12:25:44 PM PDT 23
Finished Oct 29 12:26:55 PM PDT 23
Peak memory 201400 kb
Host smart-2cad8c97-e2d9-4c75-897c-c52ff3fa4c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526297281338468230177869903404013920747758513802384491314510846199075588960 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.365262972813384682301778699034040139207477585138023844913145108
46199075588960
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.17022006359864669136626556152105682478812218505914831606698745822886050118102
Short name T680
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.84 seconds
Started Oct 29 12:27:12 PM PDT 23
Finished Oct 29 12:27:16 PM PDT 23
Peak memory 200824 kb
Host smart-153b6b44-c227-4036-85ff-75a3babed5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022006359864669136626556152105682478812218505914831606698745822886050118102 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.17022006359864669136626556152105682478812218505914831606698745822886050118102
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.40079526925579888134684052690560934332979274099931222343606009170287525378173
Short name T768
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:27:26 PM PDT 23
Peak memory 200840 kb
Host smart-81827ca7-162e-40b5-975c-e5d2fef1953d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40079526925579888134684052690560934332979274099931222343606009170287525378173 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.40079526925579888134684052690560934332979274099931222343606009170287525378173
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.94258105531034597640334818187401579704305790410532620985684577568978518165514
Short name T695
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.82 seconds
Started Oct 29 12:28:45 PM PDT 23
Finished Oct 29 12:28:49 PM PDT 23
Peak memory 200472 kb
Host smart-0c446db7-7fbe-48b7-bea1-7d14b9aa651d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94258105531034597640334818187401579704305790410532620985684577568978518165514 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.94258105531034597640334818187401579704305790410532620985684577568978518165514
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.66069714646833895833081269503866856817266764096312987626603495450424013689739
Short name T761
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:27:26 PM PDT 23
Peak memory 200808 kb
Host smart-e94db45a-e9cc-4da4-9ce8-d3dbec5093ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66069714646833895833081269503866856817266764096312987626603495450424013689739 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.66069714646833895833081269503866856817266764096312987626603495450424013689739
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.5170236161300378341893477439724409893159904415128537122435145243128521983811
Short name T718
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 29 12:27:18 PM PDT 23
Finished Oct 29 12:27:22 PM PDT 23
Peak memory 200808 kb
Host smart-59c66a74-5080-450b-94c2-318154c716be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5170236161300378341893477439724409893159904415128537122435145243128521983811 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.5170236161300378341893477439724409893159904415128537122435145243128521983811
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.114066914901447354767908104742523302953585243147174417037583332016051331804606
Short name T774
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 29 12:27:46 PM PDT 23
Finished Oct 29 12:27:53 PM PDT 23
Peak memory 200784 kb
Host smart-fec0a656-aac7-4cd2-9b5c-e66e8d069016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114066914901447354767908104742523302953585243147174417037583332016051331804606 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.114066914901447354767908104742523302953585243147174417037583332016051331804606
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.91223289177969906305430251696760765161675536020865487917298510242969708330553
Short name T693
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.8 seconds
Started Oct 29 12:27:23 PM PDT 23
Finished Oct 29 12:27:27 PM PDT 23
Peak memory 200780 kb
Host smart-9e699248-72b0-424f-8822-0504db0e780c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91223289177969906305430251696760765161675536020865487917298510242969708330553 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.91223289177969906305430251696760765161675536020865487917298510242969708330553
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.112469863571857070237905262464701391651398870880265999183155864504023061406060
Short name T730
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:05 PM PDT 23
Peak memory 200808 kb
Host smart-0f94744a-3216-4bfc-93bb-7de3d2a3effd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112469863571857070237905262464701391651398870880265999183155864504023061406060 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.112469863571857070237905262464701391651398870880265999183155864504023061406060
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.84260669502517035238792565032701045465491129321348990234560136809661103153548
Short name T775
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 29 12:27:32 PM PDT 23
Finished Oct 29 12:27:36 PM PDT 23
Peak memory 200816 kb
Host smart-f75e22c1-6ed3-4fd5-9c0c-8be322408006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84260669502517035238792565032701045465491129321348990234560136809661103153548 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.84260669502517035238792565032701045465491129321348990234560136809661103153548
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.72105553222686139077413885470495583654071691855182055742290237979875376085084
Short name T748
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.8 seconds
Started Oct 29 12:27:38 PM PDT 23
Finished Oct 29 12:27:42 PM PDT 23
Peak memory 200788 kb
Host smart-0f716b38-8d5d-49d1-a9f9-33140a68ec3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72105553222686139077413885470495583654071691855182055742290237979875376085084 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.72105553222686139077413885470495583654071691855182055742290237979875376085084
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.106126558494952726569009447894351679420028369958607566690894102829085085532731
Short name T9
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 29 12:27:06 PM PDT 23
Finished Oct 29 12:27:10 PM PDT 23
Peak memory 200924 kb
Host smart-5ff7aedc-9e04-4b75-8a55-d8431fa1d29b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061265584949527265690094478943516794200283
69958607566690894102829085085532731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.106
126558494952726569009447894351679420028369958607566690894102829085085532731
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.55410948396270993574812690776269723533293515947533096307519011078469227100651
Short name T776
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.16 seconds
Started Oct 29 12:26:05 PM PDT 23
Finished Oct 29 12:26:09 PM PDT 23
Peak memory 201152 kb
Host smart-9b433270-7ce7-465f-876f-987d56a0d962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55410948396270993574812690776269723533293515947533096307519011078469227100651 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.55410948396270993574812690776269723533293515947533096307519011078469227100651
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.75807669824975108961725328729609322165414575893083116132222478963341017066227
Short name T672
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.93 seconds
Started Oct 29 12:27:05 PM PDT 23
Finished Oct 29 12:27:10 PM PDT 23
Peak memory 199876 kb
Host smart-4da632e6-3c40-43fc-8194-702ba1e95f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75807669824975108961725328729609322165414575893083116132222478963341017066227 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.75807669824975108961725328729609322165414575893083116132222478963341017066227
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.89503360202759348751986312993599477716116686825640504040189524385667013179434
Short name T705
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.71 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:27:47 PM PDT 23
Peak memory 201084 kb
Host smart-e2c799e7-8c88-4704-aee9-22ae2a3f9f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89503360202759348751986312993599477716116686825640504040189524385667013179434
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.895033602027593487519863129935994777161166868
25640504040189524385667013179434
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.44442732031980708272154545192929894040424892308871367407775748718706191939020
Short name T779
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.79 seconds
Started Oct 29 12:25:24 PM PDT 23
Finished Oct 29 12:25:30 PM PDT 23
Peak memory 201116 kb
Host smart-8ea0e05a-0b16-47b2-afd3-49d07455b4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44442732031980708272154545192929894040424892308871367407775748718706191939020 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.44442732031980708272154545192929894040424892308871367407775748718706191939020
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.18045204979794570695779161232538191410145123459505372295781106062005446022777
Short name T699
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.58 seconds
Started Oct 29 12:27:26 PM PDT 23
Finished Oct 29 12:28:36 PM PDT 23
Peak memory 200384 kb
Host smart-bd7891c4-9913-46cd-8010-42442a2dff67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045204979794570695779161232538191410145123459505372295781106062005446022777 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.180452049797945706957791612325381914101451234595053722957811060
62005446022777
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.41454374438325434638300286865827813329524518930879140852928038513674750694500
Short name T762
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.25 seconds
Started Oct 29 12:27:11 PM PDT 23
Finished Oct 29 12:27:16 PM PDT 23
Peak memory 200200 kb
Host smart-e191658d-8267-4bd7-a0a1-d3344e205aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145437443832543463830028686582781332952451
8930879140852928038513674750694500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4145
4374438325434638300286865827813329524518930879140852928038513674750694500
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.72139950959627865754558335905028794825967951693361034434703152377172741482830
Short name T759
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.07 seconds
Started Oct 29 12:27:04 PM PDT 23
Finished Oct 29 12:27:08 PM PDT 23
Peak memory 200260 kb
Host smart-25752f12-8a18-43f6-87b0-78a7d50461bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72139950959627865754558335905028794825967951693361034434703152377172741482830 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.72139950959627865754558335905028794825967951693361034434703152377172741482830
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.52951574116910956139493834962378097789372962549695808077458859320978942184403
Short name T144
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.85 seconds
Started Oct 29 12:27:17 PM PDT 23
Finished Oct 29 12:27:21 PM PDT 23
Peak memory 200020 kb
Host smart-63db2f6c-b374-4daf-8549-127ecbb4d883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52951574116910956139493834962378097789372962549695808077458859320978942184403 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.52951574116910956139493834962378097789372962549695808077458859320978942184403
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.29603620724258991002509348387064681563119366935064888607120394433985982095403
Short name T681
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.43 seconds
Started Oct 29 12:27:21 PM PDT 23
Finished Oct 29 12:27:47 PM PDT 23
Peak memory 201080 kb
Host smart-608b86ad-302c-461b-83c7-17f7c36d668b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29603620724258991002509348387064681563119366935064888607120394433985982095403
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.296036207242589910025093483870646815631193669
35064888607120394433985982095403
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.18979096578084702286226265517125897137358700655500390971685774795995745049983
Short name T745
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.83 seconds
Started Oct 29 12:27:21 PM PDT 23
Finished Oct 29 12:27:28 PM PDT 23
Peak memory 201088 kb
Host smart-6b43b09d-6cbe-4102-8a86-d462bfaae15e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18979096578084702286226265517125897137358700655500390971685774795995745049983 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.18979096578084702286226265517125897137358700655500390971685774795995745049983
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.101226382468419450639372530909826586850766332333513812457211384925193119143992
Short name T51
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.96 seconds
Started Oct 29 12:27:03 PM PDT 23
Finished Oct 29 12:28:14 PM PDT 23
Peak memory 200044 kb
Host smart-81d62558-816b-42bb-b813-b7a5f4006789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101226382468419450639372530909826586850766332333513812457211384925193119143992 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.10122638246841945063937253090982658685076633233351381245721138
4925193119143992
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.71341539770545966582424536427295983811007417143235375238632862581561949447351
Short name T674
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.27 seconds
Started Oct 29 12:27:27 PM PDT 23
Finished Oct 29 12:27:32 PM PDT 23
Peak memory 200748 kb
Host smart-a57aa032-4e81-47fe-b583-1771b02be27e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7134153977054596658242453642729598381100741
7143235375238632862581561949447351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.7134
1539770545966582424536427295983811007417143235375238632862581561949447351
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.39697271880896360777707227236885625473255781686427549197604271696690532063263
Short name T709
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:27:26 PM PDT 23
Peak memory 200836 kb
Host smart-7666d2da-dc01-4c6e-aa11-c9cf734f0d32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39697271880896360777707227236885625473255781686427549197604271696690532063263 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.39697271880896360777707227236885625473255781686427549197604271696690532063263
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.35125996942021840325346179388325419742417972387092427706232670428232258039145
Short name T752
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 200792 kb
Host smart-f078ed6c-cade-43d1-82be-ab1c8299aa09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35125996942021840325346179388325419742417972387092427706232670428232258039145 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.35125996942021840325346179388325419742417972387092427706232670428232258039145
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.19569781666848949155691070880770100750354060866806961306115650548549030528812
Short name T697
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.89 seconds
Started Oct 29 12:27:17 PM PDT 23
Finished Oct 29 12:27:42 PM PDT 23
Peak memory 200856 kb
Host smart-5d023d1a-9c2e-4b2d-b144-89510a5919fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569781666848949155691070880770100750354060866806961306115650548549030528812
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.195697816668489491556910708807701007503540608
66806961306115650548549030528812
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.77565815146009306702663435492585215909052239731468236208961780758830138890607
Short name T760
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.64 seconds
Started Oct 29 12:27:43 PM PDT 23
Finished Oct 29 12:27:49 PM PDT 23
Peak memory 201088 kb
Host smart-f7554b75-eb04-456d-ba32-18f02604c673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77565815146009306702663435492585215909052239731468236208961780758830138890607 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.77565815146009306702663435492585215909052239731468236208961780758830138890607
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.52611466532483835884185561640788764970746659727173517551193037247673371753203
Short name T1
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.62 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:28:33 PM PDT 23
Peak memory 201104 kb
Host smart-c15b4d4d-8ad3-4d13-b390-d2c64e523b55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52611466532483835884185561640788764970746659727173517551193037247673371753203 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.526114665324838358841855616407887649707466597271735175511930372
47673371753203
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.32738275051188695240759551394609955362668003525844972260699738157193150504647
Short name T711
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.29 seconds
Started Oct 29 12:25:29 PM PDT 23
Finished Oct 29 12:25:34 PM PDT 23
Peak memory 200908 kb
Host smart-9573960e-e7ac-4368-8f4c-c63dbdc2fba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273827505118869524075955139460995536266800
3525844972260699738157193150504647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3273
8275051188695240759551394609955362668003525844972260699738157193150504647
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.36582799973352552280593802868176106270838948871203809759978074905796836627369
Short name T71
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Oct 29 12:27:16 PM PDT 23
Finished Oct 29 12:27:20 PM PDT 23
Peak memory 200872 kb
Host smart-0ed840fe-bc88-49ec-adcf-3aca2ad64218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36582799973352552280593802868176106270838948871203809759978074905796836627369 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.36582799973352552280593802868176106270838948871203809759978074905796836627369
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.81994190428523594610684577839015755838797257628102504123797086951697772415948
Short name T78
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 29 12:27:22 PM PDT 23
Finished Oct 29 12:27:26 PM PDT 23
Peak memory 200812 kb
Host smart-0b1a035a-d218-47e1-b16e-cc2650c82037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81994190428523594610684577839015755838797257628102504123797086951697772415948 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.81994190428523594610684577839015755838797257628102504123797086951697772415948
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.48292854624911814183268974478480339468744455904532704858874113430521911631629
Short name T720
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.89 seconds
Started Oct 29 12:27:17 PM PDT 23
Finished Oct 29 12:27:42 PM PDT 23
Peak memory 200484 kb
Host smart-63f5494b-0e84-437a-9104-91015281a6bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48292854624911814183268974478480339468744455904532704858874113430521911631629
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.482928546249118141832689744784803394687444559
04532704858874113430521911631629
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.58411738456036189889698468877072212996532011637024320077872015743856992064702
Short name T57
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.8 seconds
Started Oct 29 12:27:44 PM PDT 23
Finished Oct 29 12:27:50 PM PDT 23
Peak memory 201072 kb
Host smart-f1348907-0a59-4865-abc9-751dd9624f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58411738456036189889698468877072212996532011637024320077872015743856992064702 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.58411738456036189889698468877072212996532011637024320077872015743856992064702
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.19390020335794844746406924329173406381266317178253588377890569763133910924930
Short name T694
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.93 seconds
Started Oct 29 12:27:03 PM PDT 23
Finished Oct 29 12:28:15 PM PDT 23
Peak memory 200084 kb
Host smart-5db03e05-9b5e-4913-b6f0-a3eac0ecbd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390020335794844746406924329173406381266317178253588377890569763133910924930 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.193900203357948447464069243291734063812663171782535883778905697
63133910924930
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.60277739209850242298297992188043465001047368501482123511005558552160691506551
Short name T738
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Oct 29 12:25:44 PM PDT 23
Finished Oct 29 12:25:48 PM PDT 23
Peak memory 200932 kb
Host smart-0cd656dc-3979-485e-a184-09a17263421d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6027773920985024229829799218804346500104736
8501482123511005558552160691506551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.6027
7739209850242298297992188043465001047368501482123511005558552160691506551
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.100766768693484284305290689247358378095985428653718401329538892917722512158253
Short name T753
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Oct 29 12:25:48 PM PDT 23
Finished Oct 29 12:25:52 PM PDT 23
Peak memory 200848 kb
Host smart-3c79594d-7d1b-4be1-b1ef-54ba54716ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100766768693484284305290689247358378095985428653718401329538892917722512158253 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.100766768693484284305290689247358378095985428653718401329538892917722512158253
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.85054422538808898044114036946060656710712747037110140313378546492675545494925
Short name T703
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.85 seconds
Started Oct 29 12:25:42 PM PDT 23
Finished Oct 29 12:25:46 PM PDT 23
Peak memory 200816 kb
Host smart-892d0f15-4f8b-4565-9804-9f4379727d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85054422538808898044114036946060656710712747037110140313378546492675545494925 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.85054422538808898044114036946060656710712747037110140313378546492675545494925
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.24907508383383729468080900999524855521852589272054597128309665238487278690189
Short name T692
Test name
Test status
Simulation time 9477310853 ps
CPU time 26.74 seconds
Started Oct 29 12:26:29 PM PDT 23
Finished Oct 29 12:26:58 PM PDT 23
Peak memory 201344 kb
Host smart-88c4307f-f68f-444d-8efd-4b7038742fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24907508383383729468080900999524855521852589272054597128309665238487278690189
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.249075083833837294680809009995248555218525892
72054597128309665238487278690189
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.36075308213031964952250393873298699350584097163871859895872656895557981712567
Short name T736
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.68 seconds
Started Oct 29 12:27:21 PM PDT 23
Finished Oct 29 12:27:27 PM PDT 23
Peak memory 201088 kb
Host smart-f2aa731f-b67e-4df7-a948-a6250bd0a723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075308213031964952250393873298699350584097163871859895872656895557981712567 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.36075308213031964952250393873298699350584097163871859895872656895557981712567
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.9168988826220265908543141683881595792800440460302785867295734021789171470112
Short name T52
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.69 seconds
Started Oct 29 12:27:07 PM PDT 23
Finished Oct 29 12:28:17 PM PDT 23
Peak memory 201004 kb
Host smart-024aabcc-a26b-4363-9132-a563e5fb9392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9168988826220265908543141683881595792800440460302785867295734021789171470112 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.9168988826220265908543141683881595792800440460302785867295734021789171470112
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.5134786649222434432728470076359599330271440372043987292358390737369796680201
Short name T425
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.75 seconds
Started Oct 29 12:27:31 PM PDT 23
Finished Oct 29 12:27:35 PM PDT 23
Peak memory 200836 kb
Host smart-3ff429e4-480f-438e-bd07-f51c2333de8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5134786649222434432728470076359599330271440372043987292358390737369796680201 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.5134786649222434432728470076359599330271440372043987292358390737369796680201
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.8721299320539646720876095734846671044947748374108613656599885757759016202694
Short name T641
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Oct 29 12:27:31 PM PDT 23
Finished Oct 29 12:27:36 PM PDT 23
Peak memory 201044 kb
Host smart-5819e9e8-0bdb-4ad0-a329-4e550dd1ab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8721299320539646720876095734846671044947748374108613656599885757759016202694 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.8721299320539646720876095734846671044947748374108613656599885757759016202694
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.35270892602052958978041111094370587510162193209520629276439609089116953737801
Short name T312
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.31 seconds
Started Oct 29 12:27:31 PM PDT 23
Finished Oct 29 12:30:36 PM PDT 23
Peak memory 201132 kb
Host smart-ae8b974d-5950-4c5f-9c54-44284ed11386
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270892602052958978041111094370587510162193209520629276439609089116953737801 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.352708926020529589780411110943705875101621932095206292764396090
89116953737801
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.77847530036574786307820722880897456691020504959817573134049469745300269944840
Short name T93
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.48 seconds
Started Oct 29 12:27:32 PM PDT 23
Finished Oct 29 12:27:37 PM PDT 23
Peak memory 200984 kb
Host smart-062d1486-deae-4836-8264-8bb561de58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77847530036574786307820722880897456691020504959817573134049469745300269944840 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.77847530036574786307820722880897456691020504959817573
134049469745300269944840
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.85323758106978607471842724408541830112279716450809219172590778336419095814600
Short name T543
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.56 seconds
Started Oct 29 12:27:47 PM PDT 23
Finished Oct 29 12:27:57 PM PDT 23
Peak memory 201020 kb
Host smart-55d8d8e3-adbe-456b-83a5-b5cec59d0d84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85323758106978607471842724408541830112279716450809219172590778336419095814600 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.8532375810697860747184272440854183011227971645080921917259077
8336419095814600
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.45934617505725719490248108260515492454918387417581895783482733682386153057156
Short name T670
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.41 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:13 PM PDT 23
Peak memory 201000 kb
Host smart-61748bc6-6924-488e-a315-d521d7637b97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45934617505725719490248108260515492454918387417581895783482733682386153057156 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.45934617505725719490248108260515492454918387417581895783482733682386153057156
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.115370813363816209433303982568898812033404411751299352281455865465770037479853
Short name T292
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:12 PM PDT 23
Peak memory 201012 kb
Host smart-a0e93f5a-3701-4639-85ae-cfe0b06e61f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115370813363816209433303982568898812033404411751299352281455865465770037479853 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.115370813363816209433303982568898812033404411751299352281455865465770037479853
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.35954425439421220508420663543037028535086858480850332751408025550851344159496
Short name T382
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 29 12:27:54 PM PDT 23
Finished Oct 29 12:28:02 PM PDT 23
Peak memory 201044 kb
Host smart-f0437ca3-3514-4287-9861-f567db8b8d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35954425439421220508420663543037028535086858480850332751408025550851344159496 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.35954425439421220508420663543037028535086858480850332751408025550851344159496
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.42074486475593049803753521242315098508086132600282748266828499181975965285867
Short name T431
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 29 12:27:33 PM PDT 23
Finished Oct 29 12:27:37 PM PDT 23
Peak memory 200944 kb
Host smart-f0eb911f-4f21-4bed-b5e2-436f4d1d026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42074486475593049803753521242315098508086132600282748266828499181975965285867 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.42074486475593049803753521242315098508086132600282748266828499181975965285867
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.24868953827735916966721795964664162410495797707565247462995037405546437574245
Short name T568
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.73 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:12 PM PDT 23
Peak memory 200956 kb
Host smart-f7815d04-5077-438b-9114-1418d76fc35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24868953827735916966721795964664162410495797707565247462995037405546437574245 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.24868953827735916966721795964664162410495797707565247462995037405546437574245
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.16987545095764620124073729248658731881403303774944887527940362279408381825067
Short name T185
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:29:06 PM PDT 23
Peak memory 200960 kb
Host smart-1254e96d-5f5f-4b40-8627-03d25fa91724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16987545095764620124073729248658731881403303774944887527940362279408381825067 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_smoke.16987545095764620124073729248658731881403303774944887527940362279408381825067
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.21185032841097460362215175202260329706810390357532785392472557712414932613290
Short name T529
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.7 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:30:25 PM PDT 23
Peak memory 201104 kb
Host smart-da5cddbf-fc36-41ad-a194-4f38a906bf49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185032841097460362215175202260329706810390357532785392472557712414932613290 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.21185032841097460362215175202260329706810390357532785392472557712414932613290
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.62048024651517668586263435271270545740094114213806972172472279992813497662533
Short name T600
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Oct 29 12:28:13 PM PDT 23
Finished Oct 29 12:28:19 PM PDT 23
Peak memory 200996 kb
Host smart-48941f12-8e69-457d-8ad2-3ee7d6e41b1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62048024651517668586263435271270545740094114213806972172472279992813497662533 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.6204802465151766858626343527127054574009411421380697217247227
9992813497662533
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.63287899710821132370127638530920688873934120048733923402791861112351185115899
Short name T642
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.89 seconds
Started Oct 29 12:27:45 PM PDT 23
Finished Oct 29 12:27:52 PM PDT 23
Peak memory 200992 kb
Host smart-a036ccbc-50e0-467e-be07-21a0e065a870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63287899710821132370127638530920688873934120048733923402791861112351185115899 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.63287899710821132370127638530920688873934120048733923402791861112351185115899
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.24008737343310891643172036199776307413000497552227091497410038308707509192555
Short name T487
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.02 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:31:03 PM PDT 23
Peak memory 201260 kb
Host smart-bcc9d898-ea85-4ea4-b14e-dce890189054
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24008737343310891643172036199776307413000497552227091497410038308707509192555 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.240087373433108916431720361997763074130004975522270914974100383
08707509192555
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.48180949549246333955604068353409626254566408881612849618822485246402784076425
Short name T349
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.31 seconds
Started Oct 29 12:28:12 PM PDT 23
Finished Oct 29 12:28:18 PM PDT 23
Peak memory 201036 kb
Host smart-8f6b8ac3-0e07-4b16-984f-10dd93ba6ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48180949549246333955604068353409626254566408881612849618822485246402784076425 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.48180949549246333955604068353409626254566408881612849618822485246402784076425
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.77423100648790329502928825446935832013354952638284365752773118330903930878632
Short name T117
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.6 seconds
Started Oct 29 12:27:30 PM PDT 23
Finished Oct 29 12:27:35 PM PDT 23
Peak memory 201020 kb
Host smart-9546e732-e73c-48fb-889c-e571f5ec6d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77423100648790329502928825446935832013354952638284365752773118330903930878632 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.77423100648790329502928825446935832013354952638284365
752773118330903930878632
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.51256901391847753169867137220544672528684182205233356447180161907795748564820
Short name T264
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.59 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:14 PM PDT 23
Peak memory 201024 kb
Host smart-4d3bbbda-8b2d-41ff-af3a-f022994fe1c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51256901391847753169867137220544672528684182205233356447180161907795748564820 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.5125690139184775316986713722054467252868418220523335644718016
1907795748564820
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.7599512012306679303138972950068283075421956290009180474084359595815118746472
Short name T462
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 29 12:27:38 PM PDT 23
Finished Oct 29 12:27:45 PM PDT 23
Peak memory 201296 kb
Host smart-da22d7fc-341e-454d-94e4-c15581921c95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7599512012306679303138972950068283075421956290009180474084359595815118746472 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.7599512012306679303138972950068283075421956290009180474084359595815118746472
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.43492711947645464839807216687312906943073268121797419630350807102775660107622
Short name T95
Test name
Test status
Simulation time 38606274248 ps
CPU time 60.67 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:29:02 PM PDT 23
Peak memory 200796 kb
Host smart-9f16f1e7-cf0d-4de3-ba77-cde25caa75f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43492711947645464839807216687312906943073268121797419630350807102775660107622 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.43492711947645464839807216687312906943073268121797419630350807102775660107622
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.9735863438950947091740190832349686805099884526880998069291866910146662563754
Short name T508
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Oct 29 12:28:13 PM PDT 23
Finished Oct 29 12:28:19 PM PDT 23
Peak memory 200996 kb
Host smart-2e0b00a0-f953-4b3a-a5c2-1c41904c4a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9735863438950947091740190832349686805099884526880998069291866910146662563754 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.9735863438950947091740190832349686805099884526880998069291866910146662563754
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.45252929994073326261048518447374773072451687168358241516036617828114733330619
Short name T372
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.89 seconds
Started Oct 29 12:27:39 PM PDT 23
Finished Oct 29 12:27:45 PM PDT 23
Peak memory 201340 kb
Host smart-82509081-c1cc-4321-8521-7a6e5ace0e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45252929994073326261048518447374773072451687168358241516036617828114733330619 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.45252929994073326261048518447374773072451687168358241516036617828114733330619
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.99353861007819709644515010336542105627420481547694218170087464775055807157358
Short name T226
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.81 seconds
Started Oct 29 12:27:58 PM PDT 23
Finished Oct 29 12:28:04 PM PDT 23
Peak memory 201128 kb
Host smart-cdc22185-68a7-4ee3-bd30-d3ae4fde612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99353861007819709644515010336542105627420481547694218170087464775055807157358 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.99353861007819709644515010336542105627420481547694218170087464775055807157358
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.46129525117273474606855850868145792670270636357585429949128687809096453038250
Short name T403
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.45 seconds
Started Oct 29 12:28:03 PM PDT 23
Finished Oct 29 12:28:07 PM PDT 23
Peak memory 201016 kb
Host smart-c693df42-2550-4bc8-b96d-c333065d4193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46129525117273474606855850868145792670270636357585429949128687809096453038250 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.46129525117273474606855850868145792670270636357585429949128687809096453038250
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.77233188011802203479086638088821130327387547981566112977212987014663290983001
Short name T140
Test name
Test status
Simulation time 42018621949 ps
CPU time 66.47 seconds
Started Oct 29 12:27:47 PM PDT 23
Finished Oct 29 12:28:56 PM PDT 23
Peak memory 221404 kb
Host smart-1dfb4238-76ea-409d-8f35-de3218df01c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77233188011802203479086638088821130327387547981566112977212987014663290983001 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.77233188011802203479086638088821130327387547981566112977212987014663290983001
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.11893375822557657960973337560031989481191393000921936783121418251574747448269
Short name T455
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 29 12:27:38 PM PDT 23
Finished Oct 29 12:27:42 PM PDT 23
Peak memory 200940 kb
Host smart-751bd938-5326-4dcc-9aaf-eb8cbbc3ace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11893375822557657960973337560031989481191393000921936783121418251574747448269 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_smoke.11893375822557657960973337560031989481191393000921936783121418251574747448269
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.108918541099578533861123237055372621385946045782798555226176926342959264045382
Short name T646
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.13 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:31:19 PM PDT 23
Peak memory 201296 kb
Host smart-f4b71a65-7c5c-42a0-b423-0e0df9ce809b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108918541099578533861123237055372621385946045782798555226176926342959264045382 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.108918541099578533861123237055372621385946045782798555226176926342959264045382
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.44941574339067252192989645387346157898911053179042055814662306065079975715932
Short name T373
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:16 PM PDT 23
Peak memory 200852 kb
Host smart-0788aab5-2fce-4b07-89ba-79133b0b5559
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44941574339067252192989645387346157898911053179042055814662306065079975715932 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.4494157433906725219298964538734615789891105317904205581466230
6065079975715932
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.112452976017445720033607989952447251978327691845150372056054426592027416332743
Short name T364
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 29 12:28:23 PM PDT 23
Finished Oct 29 12:28:27 PM PDT 23
Peak memory 200996 kb
Host smart-8bf44e03-93b4-442a-b10e-63d2e4a90986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112452976017445720033607989952447251978327691845150372056054426592027416332743 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.112452976017445720033607989952447251978327691845150372056054426592027416332743
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.10548380134708162282043268019433314904208173303235103842789757573935543584020
Short name T583
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 29 12:28:33 PM PDT 23
Finished Oct 29 12:28:38 PM PDT 23
Peak memory 201036 kb
Host smart-079d4db6-9e3b-4df3-b2e6-0610a7fb74ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10548380134708162282043268019433314904208173303235103842789757573935543584020 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.10548380134708162282043268019433314904208173303235103842789757573935543584020
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.19721821964701785636090356806338773341977121666121691200336421493386447899189
Short name T322
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.09 seconds
Started Oct 29 12:28:31 PM PDT 23
Finished Oct 29 12:31:34 PM PDT 23
Peak memory 201216 kb
Host smart-7b0fe3ab-da6d-4b50-b373-d15096eb5f4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19721821964701785636090356806338773341977121666121691200336421493386447899189 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.19721821964701785636090356806338773341977121666121691200336421
493386447899189
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.90643795115554212201485585598585363047262542904359496894413900320631087867901
Short name T650
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.43 seconds
Started Oct 29 12:29:00 PM PDT 23
Finished Oct 29 12:29:08 PM PDT 23
Peak memory 201016 kb
Host smart-fc04e94d-985f-4aab-b546-8cd4612acf5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90643795115554212201485585598585363047262542904359496894413900320631087867901 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.906437951155542122014855855985853630472625429043594968944139
00320631087867901
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.43232175814187385189197815375503153753768756178855653467627443674047755065694
Short name T231
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 29 12:28:24 PM PDT 23
Finished Oct 29 12:28:30 PM PDT 23
Peak memory 201044 kb
Host smart-5476cbdc-277a-4b31-92ea-0080c9d9ea89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43232175814187385189197815375503153753768756178855653467627443674047755065694 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.4323217581418738518919781537550315375376875617885565346762744367
4047755065694
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.264255436226855158589518713617433348021687755042651159647756551908378151437
Short name T518
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 29 12:28:40 PM PDT 23
Finished Oct 29 12:28:45 PM PDT 23
Peak memory 200996 kb
Host smart-a32cfc5b-709a-4102-8bba-6f20f983353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264255436226855158589518713617433348021687755042651159647756551908378151437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.264255436226855158589518713617433348021687755042651159647756551908378151437
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.5160924204899428239491710987148784193981904111295363164179579459977691733851
Short name T61
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 29 12:28:22 PM PDT 23
Finished Oct 29 12:28:27 PM PDT 23
Peak memory 201012 kb
Host smart-5d64c130-cfed-487c-9d68-fd5b6963b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5160924204899428239491710987148784193981904111295363164179579459977691733851 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.5160924204899428239491710987148784193981904111295363164179579459977691733851
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.11526515058450647809941200201465696662919909402915077902411383614628843667997
Short name T461
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.85 seconds
Started Oct 29 12:28:34 PM PDT 23
Finished Oct 29 12:28:38 PM PDT 23
Peak memory 200968 kb
Host smart-089112b1-c197-4f0a-a54f-0cb4face412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11526515058450647809941200201465696662919909402915077902411383614628843667997 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.11526515058450647809941200201465696662919909402915077902411383614628843667997
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.100610209048363823119318298629957543616506629560306012063883602617538128853939
Short name T189
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Oct 29 12:28:30 PM PDT 23
Finished Oct 29 12:28:35 PM PDT 23
Peak memory 201296 kb
Host smart-829050b5-2b66-4254-b70e-a8651d4f8dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100610209048363823119318298629957543616506629560306012063883602617538128853939 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.100610209048363823119318298629957543616506629560306012063883602617538128853939
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.29458275211748412128145632279174929197377056110569265503456791300630266749100
Short name T660
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.92 seconds
Started Oct 29 12:28:34 PM PDT 23
Finished Oct 29 12:28:38 PM PDT 23
Peak memory 201244 kb
Host smart-c7ec4376-eb45-4776-95f7-edf0f912b78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29458275211748412128145632279174929197377056110569265503456791300630266749100 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_smoke.29458275211748412128145632279174929197377056110569265503456791300630266749100
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.49964542796989543377743735686747389808877668571316490620935073804781835427244
Short name T444
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.76 seconds
Started Oct 29 12:28:24 PM PDT 23
Finished Oct 29 12:30:42 PM PDT 23
Peak memory 201280 kb
Host smart-54db4a65-17c0-4430-b624-ab6706ae0acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49964542796989543377743735686747389808877668571316490620935073804781835427244 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.49964542796989543377743735686747389808877668571316490620935073804781835427244
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.69197085408436943891723833973601199596978316199517167961192389411618209739639
Short name T410
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201000 kb
Host smart-0c4da47e-14c8-447b-8c7a-a107b911022a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69197085408436943891723833973601199596978316199517167961192389411618209739639 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.691970854084369438917238339736011995969783161995171679611923
89411618209739639
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.102598132612116118404139086524888921987519500189316517405438389488091477725182
Short name T386
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 29 12:28:34 PM PDT 23
Finished Oct 29 12:28:38 PM PDT 23
Peak memory 201012 kb
Host smart-8c0751fc-3f9c-482f-bfcf-78b971dd0148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102598132612116118404139086524888921987519500189316517405438389488091477725182 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.102598132612116118404139086524888921987519500189316517405438389488091477725182
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.77171330921079723168566467340664459483039990309611722548252891970358682466965
Short name T505
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.59 seconds
Started Oct 29 12:28:37 PM PDT 23
Finished Oct 29 12:28:43 PM PDT 23
Peak memory 201088 kb
Host smart-7c16585d-75b5-403e-8926-363eb79c3f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77171330921079723168566467340664459483039990309611722548252891970358682466965 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.77171330921079723168566467340664459483039990309611722548252891970358682466965
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.23298382398039417792394855904010093958446723959257905511183509904741997540805
Short name T299
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.16 seconds
Started Oct 29 12:28:20 PM PDT 23
Finished Oct 29 12:31:25 PM PDT 23
Peak memory 201256 kb
Host smart-c94280b2-b208-4377-83e1-c207c47b3de7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23298382398039417792394855904010093958446723959257905511183509904741997540805 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.23298382398039417792394855904010093958446723959257905511183509
904741997540805
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.44152069812348306970686955846977179043920178638973146022367433919915133709305
Short name T439
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Oct 29 12:28:22 PM PDT 23
Finished Oct 29 12:28:30 PM PDT 23
Peak memory 201020 kb
Host smart-8741c40b-6532-4ac3-9c89-652695d2d72b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44152069812348306970686955846977179043920178638973146022367433919915133709305 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.441520698123483069706869558469771790439201786389731460223674
33919915133709305
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.7274946916348812585520514383988919457314666330794085700238744700813354694312
Short name T640
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.2 seconds
Started Oct 29 12:28:44 PM PDT 23
Finished Oct 29 12:28:51 PM PDT 23
Peak memory 201036 kb
Host smart-d63b4163-bec8-450d-acb1-826883c1c70f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7274946916348812585520514383988919457314666330794085700238744700813354694312 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.7274946916348812585520514383988919457314666330794085700238744700813354694312
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.98750423810331912009833520097020264417902283505239258603721479895032152166479
Short name T412
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 29 12:28:28 PM PDT 23
Finished Oct 29 12:28:33 PM PDT 23
Peak memory 200984 kb
Host smart-7d41067e-7ab9-49c5-aab8-1543b593c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98750423810331912009833520097020264417902283505239258603721479895032152166479 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.98750423810331912009833520097020264417902283505239258603721479895032152166479
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.42548046786900398300251458806261180130900082512258932778330770620120696844471
Short name T224
Test name
Test status
Simulation time 2470384766 ps
CPU time 5.01 seconds
Started Oct 29 12:28:25 PM PDT 23
Finished Oct 29 12:28:30 PM PDT 23
Peak memory 201064 kb
Host smart-bf3a7655-f7c1-42f1-9836-bafb38326d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42548046786900398300251458806261180130900082512258932778330770620120696844471 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.42548046786900398300251458806261180130900082512258932778330770620120696844471
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.66418732200228525250092938619658509239013175560562415107102706854606060681472
Short name T243
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.91 seconds
Started Oct 29 12:28:33 PM PDT 23
Finished Oct 29 12:28:38 PM PDT 23
Peak memory 200964 kb
Host smart-1b0cc63b-99d8-4c1e-a1da-7961488b0952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66418732200228525250092938619658509239013175560562415107102706854606060681472 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.66418732200228525250092938619658509239013175560562415107102706854606060681472
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.38593702440599284163648252789521288530881919622201233977487198747579061522971
Short name T367
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.75 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:29:26 PM PDT 23
Peak memory 198972 kb
Host smart-cb6cb5e4-8448-4ea5-b480-e779130856ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38593702440599284163648252789521288530881919622201233977487198747579061522971 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.38593702440599284163648252789521288530881919622201233977487198747579061522971
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.21252100884800015255116997346174468985429549808626268195322588936633770663555
Short name T239
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 29 12:28:36 PM PDT 23
Finished Oct 29 12:28:40 PM PDT 23
Peak memory 200948 kb
Host smart-fecbb3db-b8d4-4770-9895-7d37f23959cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21252100884800015255116997346174468985429549808626268195322588936633770663555 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_smoke.21252100884800015255116997346174468985429549808626268195322588936633770663555
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.32257732288408748033396214374482924181186756115339077165703630852067802081981
Short name T551
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.48 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:31:36 PM PDT 23
Peak memory 199116 kb
Host smart-e9b22b43-9800-4c47-baa2-f29b368be481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257732288408748033396214374482924181186756115339077165703630852067802081981 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.32257732288408748033396214374482924181186756115339077165703630852067802081981
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.25919004335990630494408453474934901494842051283849762591288719710875420625776
Short name T19
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.8 seconds
Started Oct 29 12:28:45 PM PDT 23
Finished Oct 29 12:28:50 PM PDT 23
Peak memory 201036 kb
Host smart-b716f8f0-4e57-4dab-b650-a70fa5d341b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25919004335990630494408453474934901494842051283849762591288719710875420625776 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.259190043359906304944084534749349014948420512838497625912887
19710875420625776
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.48219472270759398959617324584139898138517341230884908340223087252142937283940
Short name T219
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 29 12:28:28 PM PDT 23
Finished Oct 29 12:28:32 PM PDT 23
Peak memory 201020 kb
Host smart-6df50219-f5c9-49e8-83bf-accc2a9a36c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48219472270759398959617324584139898138517341230884908340223087252142937283940 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.48219472270759398959617324584139898138517341230884908340223087252142937283940
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.108789235879764348410482114351542133739171850029996759434108455354880964151611
Short name T557
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Oct 29 12:28:23 PM PDT 23
Finished Oct 29 12:28:29 PM PDT 23
Peak memory 201044 kb
Host smart-58ac65d0-9f03-4938-859b-4415ac00fab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108789235879764348410482114351542133739171850029996759434108455354880964151611 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.108789235879764348410482114351542133739171850029996759434108455354880964151611
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.107887155021097282961677555604612375907648170504174013818063136971596459285195
Short name T559
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.33 seconds
Started Oct 29 12:28:32 PM PDT 23
Finished Oct 29 12:31:36 PM PDT 23
Peak memory 201220 kb
Host smart-cba8f9b7-848f-442c-926b-c440f29be05f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107887155021097282961677555604612375907648170504174013818063136971596459285195 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.1078871550210972829616775556046123759076481705041740138180631
36971596459285195
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.47918568929940094188451246879889195457230508484916953436070623260325567649390
Short name T329
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 29 12:28:28 PM PDT 23
Finished Oct 29 12:28:34 PM PDT 23
Peak memory 201004 kb
Host smart-b116162c-7b2a-41f9-876a-814da90128d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47918568929940094188451246879889195457230508484916953436070623260325567649390 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.4791856892994009418845124687988919545723050848491695343607062326
0325567649390
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.29616943626792248466652606086590697980009084108904541691741549580464208730733
Short name T175
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.81 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:29:26 PM PDT 23
Peak memory 198936 kb
Host smart-cfcb1639-7da9-45a0-a7bf-3ce87fba0623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29616943626792248466652606086590697980009084108904541691741549580464208730733 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.29616943626792248466652606086590697980009084108904541691741549580464208730733
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.77368566364922110591534313053573648718811241423329821215716182172928632232399
Short name T105
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 29 12:29:21 PM PDT 23
Finished Oct 29 12:29:26 PM PDT 23
Peak memory 200700 kb
Host smart-fe3bf76f-089b-407c-b315-114baf81bf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77368566364922110591534313053573648718811241423329821215716182172928632232399 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.77368566364922110591534313053573648718811241423329821215716182172928632232399
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.96408448408470042116173223396066988179616669898599035516394008187598778026313
Short name T453
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 29 12:28:38 PM PDT 23
Finished Oct 29 12:28:42 PM PDT 23
Peak memory 200960 kb
Host smart-a59a499b-628e-48cc-b29d-6f72f75db581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96408448408470042116173223396066988179616669898599035516394008187598778026313 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.96408448408470042116173223396066988179616669898599035516394008187598778026313
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.17698738084796599874775809223719336316197610096687983068489117858326536042663
Short name T169
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.65 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:29:26 PM PDT 23
Peak memory 199228 kb
Host smart-95561510-7661-4ecd-973e-4fa5a4a0638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17698738084796599874775809223719336316197610096687983068489117858326536042663 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.17698738084796599874775809223719336316197610096687983068489117858326536042663
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.61194004121306568951342313565158234414334257583083698226174405194287454404909
Short name T643
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:29:25 PM PDT 23
Peak memory 198740 kb
Host smart-4b521a8f-51af-449f-bc68-10aae11295dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61194004121306568951342313565158234414334257583083698226174405194287454404909 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_smoke.61194004121306568951342313565158234414334257583083698226174405194287454404909
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.67366174279982506400237220346530521120820380824517361688599399812829220525585
Short name T424
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.44 seconds
Started Oct 29 12:28:24 PM PDT 23
Finished Oct 29 12:30:41 PM PDT 23
Peak memory 201280 kb
Host smart-b60cb420-8a3c-4b59-ae84-d22a784ebed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67366174279982506400237220346530521120820380824517361688599399812829220525585 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.67366174279982506400237220346530521120820380824517361688599399812829220525585
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.37588901387190761760190018540507618787279219271514656170896253778840691836523
Short name T479
Test name
Test status
Simulation time 5189470156 ps
CPU time 5.14 seconds
Started Oct 29 12:28:23 PM PDT 23
Finished Oct 29 12:28:28 PM PDT 23
Peak memory 200996 kb
Host smart-e369bd21-dd64-4691-9fd6-d6a554c6f9da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37588901387190761760190018540507618787279219271514656170896253778840691836523 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.375889013871907617601900185405076187872792192715146561708962
53778840691836523
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.97930155247842593352443650132195810149884737439789869936447421014035718531832
Short name T101
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 29 12:28:29 PM PDT 23
Finished Oct 29 12:28:34 PM PDT 23
Peak memory 201064 kb
Host smart-553721dd-cac7-4c6e-b821-e515a73dff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97930155247842593352443650132195810149884737439789869936447421014035718531832 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.97930155247842593352443650132195810149884737439789869936447421014035718531832
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.18635955617659536098762268026847326297324473858883621635394399854024681939324
Short name T442
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.16 seconds
Started Oct 29 12:28:22 PM PDT 23
Finished Oct 29 12:31:24 PM PDT 23
Peak memory 201296 kb
Host smart-5d8f5d09-1da1-4519-9700-ff884764d315
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18635955617659536098762268026847326297324473858883621635394399854024681939324 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.18635955617659536098762268026847326297324473858883621635394399
854024681939324
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.79344103078583773722068489461759179112396094804405063207517331030521871881869
Short name T108
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.56 seconds
Started Oct 29 12:28:23 PM PDT 23
Finished Oct 29 12:28:31 PM PDT 23
Peak memory 201020 kb
Host smart-06c3875b-9406-41de-96cb-f301f1d25fd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79344103078583773722068489461759179112396094804405063207517331030521871881869 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.793441030785837737220684894617591791123960948044050632075173
31030521871881869
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.7262556779404047209473733670547438942554634428096282469156681803797893495728
Short name T584
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.78 seconds
Started Oct 29 12:28:34 PM PDT 23
Finished Oct 29 12:28:39 PM PDT 23
Peak memory 200984 kb
Host smart-c4f82b30-f994-4c9c-8228-2970a2076def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7262556779404047209473733670547438942554634428096282469156681803797893495728 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.7262556779404047209473733670547438942554634428096282469156681803797893495728
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.56835942783546165787023310217868134789852219494636215367322361346995974160992
Short name T470
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 29 12:28:28 PM PDT 23
Finished Oct 29 12:28:33 PM PDT 23
Peak memory 201056 kb
Host smart-da9a021e-676f-4c99-ab56-2a44de759b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56835942783546165787023310217868134789852219494636215367322361346995974160992 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.56835942783546165787023310217868134789852219494636215367322361346995974160992
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.20424262643460424449042561976056333632766497767198486842636196522558464794167
Short name T334
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 29 12:28:21 PM PDT 23
Finished Oct 29 12:28:25 PM PDT 23
Peak memory 200988 kb
Host smart-44df05e1-de34-45ea-afa8-b8d818dc4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20424262643460424449042561976056333632766497767198486842636196522558464794167 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.20424262643460424449042561976056333632766497767198486842636196522558464794167
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.112942844213358417409065206693190794603123086649923835034899452606587742551514
Short name T577
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.7 seconds
Started Oct 29 12:28:26 PM PDT 23
Finished Oct 29 12:28:32 PM PDT 23
Peak memory 201024 kb
Host smart-e20be94c-af0d-496f-890c-82979a95fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112942844213358417409065206693190794603123086649923835034899452606587742551514 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.112942844213358417409065206693190794603123086649923835034899452606587742551514
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.77153774998378436525695954466883884312054846962820672590956902369700939789950
Short name T634
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 29 12:28:28 PM PDT 23
Finished Oct 29 12:28:32 PM PDT 23
Peak memory 201236 kb
Host smart-8fb1151c-2772-4594-bad6-ac44d7a7c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77153774998378436525695954466883884312054846962820672590956902369700939789950 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_smoke.77153774998378436525695954466883884312054846962820672590956902369700939789950
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.4045521280378170152492328480259983232834631167881192893655007819926446615916
Short name T256
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.58 seconds
Started Oct 29 12:28:26 PM PDT 23
Finished Oct 29 12:30:44 PM PDT 23
Peak memory 201288 kb
Host smart-2ffb7982-e60e-45c9-9787-4e79d27b4804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045521280378170152492328480259983232834631167881192893655007819926446615916 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.4045521280378170152492328480259983232834631167881192893655007819926446615916
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.71037286839186856276508276112872497370978619360153470965558411908855461423400
Short name T599
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201000 kb
Host smart-b9434282-44d2-4c2a-b1e5-c99e3a14fb94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71037286839186856276508276112872497370978619360153470965558411908855461423400 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.710372868391868562765082761128724973709786193601534709655584
11908855461423400
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.102681674429233823866730461168694015360481077072947615880906321348977257889148
Short name T397
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 29 12:28:40 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201004 kb
Host smart-6750a106-44fc-4884-aaee-4a0d737e9f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102681674429233823866730461168694015360481077072947615880906321348977257889148 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.102681674429233823866730461168694015360481077072947615880906321348977257889148
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.113240384115751516347793529538927512641152046564686563276356037863077481961748
Short name T414
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.52 seconds
Started Oct 29 12:28:26 PM PDT 23
Finished Oct 29 12:28:32 PM PDT 23
Peak memory 201080 kb
Host smart-e1cb4a8a-d629-4407-8c0a-9ac1ebfbb4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113240384115751516347793529538927512641152046564686563276356037863077481961748 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.113240384115751516347793529538927512641152046564686563276356037863077481961748
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.30920180497018566831377805400943362237300483726080669281402049633448830243429
Short name T28
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.58 seconds
Started Oct 29 12:28:36 PM PDT 23
Finished Oct 29 12:31:40 PM PDT 23
Peak memory 201240 kb
Host smart-0d9d36e1-9041-431a-8a91-38e49a336a7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30920180497018566831377805400943362237300483726080669281402049633448830243429 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.30920180497018566831377805400943362237300483726080669281402049
633448830243429
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.24755948709979564558758966747671873935230748395344271581339066776339610901667
Short name T320
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.52 seconds
Started Oct 29 12:28:29 PM PDT 23
Finished Oct 29 12:28:37 PM PDT 23
Peak memory 201036 kb
Host smart-3d533e4e-07bf-4cba-a1a6-78f68b8f4fe1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24755948709979564558758966747671873935230748395344271581339066776339610901667 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.247559487099795645587589667476718739352307483953442715813390
66776339610901667
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.92720379723457352010546578376415330344854293367349401327676569117132502156094
Short name T495
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Oct 29 12:28:36 PM PDT 23
Finished Oct 29 12:28:43 PM PDT 23
Peak memory 200992 kb
Host smart-bf2a1365-ccc4-4231-9562-bf8552daf099
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92720379723457352010546578376415330344854293367349401327676569117132502156094 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.9272037972345735201054657837641533034485429336734940132767656911
7132502156094
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.39347497132757802470542608960311264598303222931493452931643498916296663916597
Short name T237
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 29 12:28:29 PM PDT 23
Finished Oct 29 12:28:34 PM PDT 23
Peak memory 201024 kb
Host smart-9f1bc104-8039-4e48-ab0f-e5c746e8182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39347497132757802470542608960311264598303222931493452931643498916296663916597 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.39347497132757802470542608960311264598303222931493452931643498916296663916597
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.80864038167229582427455841153354104822068571862737594205676615283946773607772
Short name T229
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:29:01 PM PDT 23
Peak memory 201044 kb
Host smart-55fee392-68ae-4c29-943c-592f1705285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80864038167229582427455841153354104822068571862737594205676615283946773607772 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.80864038167229582427455841153354104822068571862737594205676615283946773607772
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.30008141661339149858624208215304951389255668713207265053405721484912650070210
Short name T520
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Oct 29 12:28:26 PM PDT 23
Finished Oct 29 12:28:31 PM PDT 23
Peak memory 201016 kb
Host smart-540db2b0-bf44-47c2-8b93-396be98ac84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30008141661339149858624208215304951389255668713207265053405721484912650070210 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.30008141661339149858624208215304951389255668713207265053405721484912650070210
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.69275110437871578486796699923881138588086269391207192594401598995685016546799
Short name T190
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 29 12:28:36 PM PDT 23
Finished Oct 29 12:28:40 PM PDT 23
Peak memory 200888 kb
Host smart-d8693b53-9814-485c-b4b8-bb7b80d785ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69275110437871578486796699923881138588086269391207192594401598995685016546799 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sysrst_ctrl_smoke.69275110437871578486796699923881138588086269391207192594401598995685016546799
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.28095472660189174940394504276152079218242430107958606168894445628358816651220
Short name T358
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.57 seconds
Started Oct 29 12:28:37 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201260 kb
Host smart-d1ec5852-90cf-4bee-b3cb-8c0a54c3a638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28095472660189174940394504276152079218242430107958606168894445628358816651220 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.28095472660189174940394504276152079218242430107958606168894445628358816651220
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.37195960613295070050146389846272657196052625374324478159076966831201554577404
Short name T423
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 29 12:28:49 PM PDT 23
Finished Oct 29 12:28:54 PM PDT 23
Peak memory 200988 kb
Host smart-c615409c-3310-4dc7-8511-5670044b384a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195960613295070050146389846272657196052625374324478159076966831201554577404 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.371959606132950700501463898462726571960526253743244781590769
66831201554577404
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.77481554461362510309327928873183446515131120538891988826334050140387850415313
Short name T275
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.73 seconds
Started Oct 29 12:28:42 PM PDT 23
Finished Oct 29 12:28:51 PM PDT 23
Peak memory 201008 kb
Host smart-9a2230e9-339f-4c7f-b43e-49910f578973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77481554461362510309327928873183446515131120538891988826334050140387850415313 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.77481554461362510309327928873183446515131120538891988826334050140387850415313
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.15539271054049121950629716655216260207413720608777539534937566165991990039783
Short name T151
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.56 seconds
Started Oct 29 12:29:05 PM PDT 23
Finished Oct 29 12:29:11 PM PDT 23
Peak memory 200944 kb
Host smart-52b50d50-18c6-40d1-b59a-ba7970ae80e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15539271054049121950629716655216260207413720608777539534937566165991990039783 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.15539271054049121950629716655216260207413720608777539534937566165991990039783
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.96778834764112166359039889762761579671272668360076292620139043128543841097569
Short name T176
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.02 seconds
Started Oct 29 12:28:40 PM PDT 23
Finished Oct 29 12:31:45 PM PDT 23
Peak memory 201244 kb
Host smart-abc27ffa-a653-4fc7-a26a-28a269b01985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96778834764112166359039889762761579671272668360076292620139043128543841097569 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.96778834764112166359039889762761579671272668360076292620139043
128543841097569
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.15735104205955043724915261906573970843855380050487710165223190699147474373744
Short name T510
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Oct 29 12:28:43 PM PDT 23
Finished Oct 29 12:28:50 PM PDT 23
Peak memory 201052 kb
Host smart-a4556272-9a57-44e9-9d12-2672f9ce8c82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735104205955043724915261906573970843855380050487710165223190699147474373744 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.157351042059550437249152619065739708438553800504877101652231
90699147474373744
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.13919489109487295929860641489366426046542710346918340609317472341346904295482
Short name T501
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 29 12:28:41 PM PDT 23
Finished Oct 29 12:28:47 PM PDT 23
Peak memory 200992 kb
Host smart-0a92c5df-0266-4e99-95d9-c853d15e5a1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919489109487295929860641489366426046542710346918340609317472341346904295482 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1391948910948729592986064148936642604654271034691834060931747234
1346904295482
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.15563110289401641471094372948087280876352555899417196613154810593064382893949
Short name T341
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.73 seconds
Started Oct 29 12:28:40 PM PDT 23
Finished Oct 29 12:28:45 PM PDT 23
Peak memory 201012 kb
Host smart-f223b877-9dfd-44e8-80b8-e1b112dc0e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15563110289401641471094372948087280876352555899417196613154810593064382893949 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.15563110289401641471094372948087280876352555899417196613154810593064382893949
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.10109730480995856799119558467814501297130877066167144249135959246388282374289
Short name T381
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Oct 29 12:28:36 PM PDT 23
Finished Oct 29 12:28:41 PM PDT 23
Peak memory 201052 kb
Host smart-9a33c0bd-9689-4684-8933-2006c95d4199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10109730480995856799119558467814501297130877066167144249135959246388282374289 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.10109730480995856799119558467814501297130877066167144249135959246388282374289
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.30028844774154392080857322097471990175821169875153055191379032386484157292103
Short name T632
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 29 12:28:46 PM PDT 23
Finished Oct 29 12:28:50 PM PDT 23
Peak memory 201016 kb
Host smart-b0a1e7af-3db1-4f3c-9a83-e3354376e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30028844774154392080857322097471990175821169875153055191379032386484157292103 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.30028844774154392080857322097471990175821169875153055191379032386484157292103
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.5456372173224485604102541500350622152690010854413253919369286020970907933206
Short name T656
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.64 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201028 kb
Host smart-f53beceb-1308-44f8-b20e-29abd5356f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5456372173224485604102541500350622152690010854413253919369286020970907933206 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.5456372173224485604102541500350622152690010854413253919369286020970907933206
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.95769387917620715111374195061576475191247972062078110600600791235750542092708
Short name T426
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:43 PM PDT 23
Peak memory 200956 kb
Host smart-51a7d4a4-5c03-4c67-9303-9e38bcbcd365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95769387917620715111374195061576475191247972062078110600600791235750542092708 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_smoke.95769387917620715111374195061576475191247972062078110600600791235750542092708
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.58570945954515798236830559788642574868270335936118711637980010039701396806248
Short name T302
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.51 seconds
Started Oct 29 12:28:41 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201280 kb
Host smart-b6289c8d-356f-41b1-b250-035c8523ebf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58570945954515798236830559788642574868270335936118711637980010039701396806248 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.58570945954515798236830559788642574868270335936118711637980010039701396806248
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.55316403754543707540710718362843278243360509587107013739451124406005112829070
Short name T545
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 29 12:28:47 PM PDT 23
Finished Oct 29 12:28:52 PM PDT 23
Peak memory 200988 kb
Host smart-0c92d504-5f96-4b11-b357-ea3636d9669a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55316403754543707540710718362843278243360509587107013739451124406005112829070 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.553164037545437075407107183628432782433605095871070137394511
24406005112829070
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.59611518147525292722677513728411582882015259628157448892493441297807625131040
Short name T532
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.78 seconds
Started Oct 29 12:28:38 PM PDT 23
Finished Oct 29 12:28:43 PM PDT 23
Peak memory 201060 kb
Host smart-347e5c38-48ce-4c84-84d2-1f73fa1c5f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59611518147525292722677513728411582882015259628157448892493441297807625131040 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.59611518147525292722677513728411582882015259628157448892493441297807625131040
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.72167990470768150584533080227982941969787856836537245072683444593959791237509
Short name T90
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.55 seconds
Started Oct 29 12:28:38 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201096 kb
Host smart-f76f6056-adc0-457b-b01c-54e81516af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72167990470768150584533080227982941969787856836537245072683444593959791237509 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.72167990470768150584533080227982941969787856836537245072683444593959791237509
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.30267237746673318842045322129498396131753643828777201240793335627402667532231
Short name T293
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.33 seconds
Started Oct 29 12:28:49 PM PDT 23
Finished Oct 29 12:31:54 PM PDT 23
Peak memory 201216 kb
Host smart-0ee1784f-b036-46b8-a04e-0ee411ab455f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267237746673318842045322129498396131753643828777201240793335627402667532231 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.30267237746673318842045322129498396131753643828777201240793335
627402667532231
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.22265937363529491398417678184687724912578495202501160693994861686785088192070
Short name T197
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.44 seconds
Started Oct 29 12:28:36 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 200204 kb
Host smart-1e78d73e-5e21-4137-a0e5-a94f8b0158e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22265937363529491398417678184687724912578495202501160693994861686785088192070 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.222659373635294913984176781846877249125784952025011606939948
61686785088192070
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.15083635375707520211285158495021678795561379506784924388274599693596218510776
Short name T347
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Oct 29 12:28:38 PM PDT 23
Finished Oct 29 12:28:45 PM PDT 23
Peak memory 201016 kb
Host smart-36fa0c25-a8a9-430c-b562-9efec5582de1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15083635375707520211285158495021678795561379506784924388274599693596218510776 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.1508363537570752021128515849502167879556137950678492438827459969
3596218510776
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.90402025460565945223947953050519559262905768694574730627591154178181385950390
Short name T553
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 29 12:28:48 PM PDT 23
Finished Oct 29 12:28:53 PM PDT 23
Peak memory 200984 kb
Host smart-890cc27c-6d40-472d-8e72-e976e23661b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90402025460565945223947953050519559262905768694574730627591154178181385950390 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.90402025460565945223947953050519559262905768694574730627591154178181385950390
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.76566956674809175531704190183580501234229542910216354572303725201496963739630
Short name T480
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 29 12:28:49 PM PDT 23
Finished Oct 29 12:28:54 PM PDT 23
Peak memory 201016 kb
Host smart-3db86bab-8258-4107-a03a-3df89c8d4d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76566956674809175531704190183580501234229542910216354572303725201496963739630 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.76566956674809175531704190183580501234229542910216354572303725201496963739630
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.37684071590322485717903274806882744851701924960340044156480046652948877652100
Short name T467
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 29 12:28:46 PM PDT 23
Finished Oct 29 12:28:55 PM PDT 23
Peak memory 201016 kb
Host smart-41e83e90-12ed-463d-b438-614baa6a1e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37684071590322485717903274806882744851701924960340044156480046652948877652100 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.37684071590322485717903274806882744851701924960340044156480046652948877652100
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.7265994957957032520748929584903449662139933360132406342803242738636509861452
Short name T499
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.64 seconds
Started Oct 29 12:28:47 PM PDT 23
Finished Oct 29 12:28:52 PM PDT 23
Peak memory 201052 kb
Host smart-b1151059-bce9-4cb7-83ad-95078ff09b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7265994957957032520748929584903449662139933360132406342803242738636509861452 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.7265994957957032520748929584903449662139933360132406342803242738636509861452
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.59295963596479360729015133845748863465440466686546171037721100865000272429358
Short name T436
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 29 12:28:43 PM PDT 23
Finished Oct 29 12:28:47 PM PDT 23
Peak memory 200932 kb
Host smart-12488347-7002-4bf5-a0a6-156116d37d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59295963596479360729015133845748863465440466686546171037721100865000272429358 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_smoke.59295963596479360729015133845748863465440466686546171037721100865000272429358
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.3466463127295801782521402977490098636600183090201498654660392237528268245588
Short name T150
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.64 seconds
Started Oct 29 12:28:37 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201284 kb
Host smart-efe9acd5-ffc3-49c3-a32a-ac7f53a1f0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466463127295801782521402977490098636600183090201498654660392237528268245588 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.3466463127295801782521402977490098636600183090201498654660392237528268245588
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.10413156420188762536331510513563381371063445793988918556596978186590930898017
Short name T36
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Oct 29 12:28:37 PM PDT 23
Finished Oct 29 12:28:42 PM PDT 23
Peak memory 200972 kb
Host smart-d5e858a6-4787-41a9-ae37-b6056d3c5d5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413156420188762536331510513563381371063445793988918556596978186590930898017 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.104131564201887625363315105135633813710634457939889185565969
78186590930898017
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.57842329323909624659512735165151541812888412785744278849343367882202466533899
Short name T168
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.74 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:28:59 PM PDT 23
Peak memory 201012 kb
Host smart-41c4d3c0-b114-4224-bdf9-8b7420a1bdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57842329323909624659512735165151541812888412785744278849343367882202466533899 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.57842329323909624659512735165151541812888412785744278849343367882202466533899
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.111573051791077974817582009209511324113878014986372285577803485087450105585926
Short name T99
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 29 12:28:52 PM PDT 23
Finished Oct 29 12:28:58 PM PDT 23
Peak memory 201080 kb
Host smart-82da9ebb-518f-4a78-a1f6-6ed3beefe9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111573051791077974817582009209511324113878014986372285577803485087450105585926 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.111573051791077974817582009209511324113878014986372285577803485087450105585926
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.43222881455219344746946291985850181014952965560728523925753352026618504084712
Short name T472
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.55 seconds
Started Oct 29 12:28:40 PM PDT 23
Finished Oct 29 12:31:44 PM PDT 23
Peak memory 201256 kb
Host smart-f9ce50f4-5da3-4435-9a0a-07fd7edfc7d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43222881455219344746946291985850181014952965560728523925753352026618504084712 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.43222881455219344746946291985850181014952965560728523925753352
026618504084712
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.60224361008516233522313724632300244763026198720932545508265004884282605830196
Short name T40
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Oct 29 12:28:50 PM PDT 23
Finished Oct 29 12:28:58 PM PDT 23
Peak memory 201348 kb
Host smart-bdccc913-c7a5-4359-be3e-8b9c52a0c220
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60224361008516233522313724632300244763026198720932545508265004884282605830196 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.602243610085162335223137246323002447630261987209325455082650
04884282605830196
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.56675373801212543351177282463720120246380851432696198297973406055092132028311
Short name T659
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.36 seconds
Started Oct 29 12:29:07 PM PDT 23
Finished Oct 29 12:29:14 PM PDT 23
Peak memory 200980 kb
Host smart-de865539-61af-406a-b5b3-ac55abc0aff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56675373801212543351177282463720120246380851432696198297973406055092132028311 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.5667537380121254335117728246372012024638085143269619829797340605
5092132028311
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.114654705537793332296459020803886995029025524880622145496538953852139542720788
Short name T569
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 29 12:28:47 PM PDT 23
Finished Oct 29 12:28:53 PM PDT 23
Peak memory 201160 kb
Host smart-76d3e9ca-dcf2-4761-972a-b3c0d7d2c557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114654705537793332296459020803886995029025524880622145496538953852139542720788 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.114654705537793332296459020803886995029025524880622145496538953852139542720788
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.810989240405103020622014281847341027288819244828344830731119277506965134597
Short name T576
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 29 12:28:39 PM PDT 23
Finished Oct 29 12:28:44 PM PDT 23
Peak memory 201016 kb
Host smart-cfad78e7-6104-4004-ace4-84c7869ec3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810989240405103020622014281847341027288819244828344830731119277506965134597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.810989240405103020622014281847341027288819244828344830731119277506965134597
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.111817854166764858476653892736272817558715091096697111035399547150166055357777
Short name T277
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 29 12:28:48 PM PDT 23
Finished Oct 29 12:28:52 PM PDT 23
Peak memory 200960 kb
Host smart-ecdd0419-aaee-44e6-b23b-d6d5be6a6246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111817854166764858476653892736272817558715091096697111035399547150166055357777 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.111817854166764858476653892736272817558715091096697111035399547150166055357777
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.50175719635650642641830567268687030579672911655378775038825364089431404821906
Short name T409
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 29 12:28:38 PM PDT 23
Finished Oct 29 12:28:43 PM PDT 23
Peak memory 200996 kb
Host smart-f6fd1ee3-2b98-4257-8a4b-b056eaed6260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50175719635650642641830567268687030579672911655378775038825364089431404821906 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.50175719635650642641830567268687030579672911655378775038825364089431404821906
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.13682895320498955061123500273260418239028040449303223004942515476591196672274
Short name T531
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 29 12:28:50 PM PDT 23
Finished Oct 29 12:28:54 PM PDT 23
Peak memory 200912 kb
Host smart-abca9fa2-09e5-474b-81a9-ee645280c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13682895320498955061123500273260418239028040449303223004942515476591196672274 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_smoke.13682895320498955061123500273260418239028040449303223004942515476591196672274
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.66586749513199017520696920886902331994636002892038299159421645769560693987679
Short name T297
Test name
Test status
Simulation time 87228974549 ps
CPU time 138.2 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:31:13 PM PDT 23
Peak memory 201416 kb
Host smart-aa3d743c-3667-450b-b7dd-7d8c0a4cef54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66586749513199017520696920886902331994636002892038299159421645769560693987679 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.66586749513199017520696920886902331994636002892038299159421645769560693987679
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.94532654495446035014191367722037469798669651458338991795423603359934424299794
Short name T287
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 29 12:28:37 PM PDT 23
Finished Oct 29 12:28:42 PM PDT 23
Peak memory 201036 kb
Host smart-70d015af-a7f3-4fdf-b108-a8de2e6fe275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94532654495446035014191367722037469798669651458338991795423603359934424299794 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.945326544954460350141913677220374697986696514583389917954236
03359934424299794
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.21845112827056074409155851151307376433492514951731420916475662055387345794336
Short name T166
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 29 12:29:00 PM PDT 23
Finished Oct 29 12:29:04 PM PDT 23
Peak memory 201044 kb
Host smart-8e118632-b2ae-4b1f-b099-b47ebbed4d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21845112827056074409155851151307376433492514951731420916475662055387345794336 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.21845112827056074409155851151307376433492514951731420916475662055387345794336
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.49568307001514365510835355782796252580847411739652630798612727801330451196449
Short name T242
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.56 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:29:00 PM PDT 23
Peak memory 201072 kb
Host smart-7127e11c-81bc-489a-ad83-2e89e7ffb848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49568307001514365510835355782796252580847411739652630798612727801330451196449 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.49568307001514365510835355782796252580847411739652630798612727801330451196449
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.81299759542983306587960826239499722986530794352582702013716292709615911113312
Short name T262
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.42 seconds
Started Oct 29 12:28:58 PM PDT 23
Finished Oct 29 12:32:03 PM PDT 23
Peak memory 201252 kb
Host smart-a8c6555b-76f5-4be9-a856-e78d364b070f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81299759542983306587960826239499722986530794352582702013716292709615911113312 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.81299759542983306587960826239499722986530794352582702013716292
709615911113312
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.23303841743470359266135664267218330545514372898721942192454429972466262044609
Short name T471
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.46 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:29:03 PM PDT 23
Peak memory 201028 kb
Host smart-303d4dcc-4c14-48a5-82c7-77558e0a6fcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303841743470359266135664267218330545514372898721942192454429972466262044609 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.233038417434703592661356642672183305455143728987219421924544
29972466262044609
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.23959944495369833201570318560493990991795102258271069302899165557195457126615
Short name T544
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.41 seconds
Started Oct 29 12:29:07 PM PDT 23
Finished Oct 29 12:29:14 PM PDT 23
Peak memory 200980 kb
Host smart-36d461f3-773b-43de-a957-4e2265f97dc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959944495369833201570318560493990991795102258271069302899165557195457126615 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2395994449536983320157031856049399099179510225827106930289916555
7195457126615
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.26095685996908497297090082905775801407218815192002366769131611868568908784733
Short name T103
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:28:59 PM PDT 23
Peak memory 200996 kb
Host smart-8ebbd27a-edf8-4440-958a-acd45d3d85b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26095685996908497297090082905775801407218815192002366769131611868568908784733 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.26095685996908497297090082905775801407218815192002366769131611868568908784733
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.93432965048341117515420617459686312734460741560671835965015365239072700769637
Short name T535
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 29 12:28:52 PM PDT 23
Finished Oct 29 12:28:58 PM PDT 23
Peak memory 201080 kb
Host smart-6f066fa4-8936-4fdb-816a-a3985ee1a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93432965048341117515420617459686312734460741560671835965015365239072700769637 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.93432965048341117515420617459686312734460741560671835965015365239072700769637
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3143375822620348504560171545295443023469051889553562676164402462040395516137
Short name T375
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.84 seconds
Started Oct 29 12:28:56 PM PDT 23
Finished Oct 29 12:29:01 PM PDT 23
Peak memory 200968 kb
Host smart-2bbc7d56-29d1-495b-9bc8-4f09647ca0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143375822620348504560171545295443023469051889553562676164402462040395516137 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3143375822620348504560171545295443023469051889553562676164402462040395516137
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.71986698142218374733290817385424055141272370890698207753603174556761227601914
Short name T625
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 29 12:29:03 PM PDT 23
Finished Oct 29 12:29:08 PM PDT 23
Peak memory 201012 kb
Host smart-9802072b-3a7a-4e20-86ca-224799fc40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71986698142218374733290817385424055141272370890698207753603174556761227601914 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.71986698142218374733290817385424055141272370890698207753603174556761227601914
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.109287721101103088025102179874078328299808204972321760305904561653326961619292
Short name T328
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.94 seconds
Started Oct 29 12:29:06 PM PDT 23
Finished Oct 29 12:29:10 PM PDT 23
Peak memory 200928 kb
Host smart-844057c7-f73f-4ddd-aba3-ba5ac81af9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109287721101103088025102179874078328299808204972321760305904561653326961619292 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.sysrst_ctrl_smoke.109287721101103088025102179874078328299808204972321760305904561653326961619292
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.33356281559213286431304341547574711905227495925525298162866767755258694675174
Short name T259
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.38 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:31:19 PM PDT 23
Peak memory 201284 kb
Host smart-59bbcad1-6f7d-4aa8-8232-ea660f64fcc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356281559213286431304341547574711905227495925525298162866767755258694675174 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.33356281559213286431304341547574711905227495925525298162866767755258694675174
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.22600775370223283977248151063554212890738137219867093062927625510739978763589
Short name T394
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:29:00 PM PDT 23
Peak memory 200996 kb
Host smart-ed5640fa-914c-4938-8551-398c91246c30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22600775370223283977248151063554212890738137219867093062927625510739978763589 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.226007753702232839772481510635542128907381372198670930629276
25510739978763589
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.62086082011776567933680857034809113067586844076255250856028306445795286251132
Short name T523
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:28:59 PM PDT 23
Peak memory 201036 kb
Host smart-03902645-395f-43d9-aa3e-37ee29bf3735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62086082011776567933680857034809113067586844076255250856028306445795286251132 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.62086082011776567933680857034809113067586844076255250856028306445795286251132
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.80775570461644755887393283355364594843368745620648616657594662861857642873389
Short name T481
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.56 seconds
Started Oct 29 12:28:59 PM PDT 23
Finished Oct 29 12:29:05 PM PDT 23
Peak memory 201064 kb
Host smart-c0beeed2-ac8f-4e92-9ce6-bedf8e3fe8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80775570461644755887393283355364594843368745620648616657594662861857642873389 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.80775570461644755887393283355364594843368745620648616657594662861857642873389
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.312833674234592581570445079405757139698489505439454108018416769588535667700
Short name T309
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.04 seconds
Started Oct 29 12:29:05 PM PDT 23
Finished Oct 29 12:32:10 PM PDT 23
Peak memory 201248 kb
Host smart-d5087bf2-8827-400a-8e44-e864e9e5955e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312833674234592581570445079405757139698489505439454108018416769588535667700 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.312833674234592581570445079405757139698489505439454108018416769588535667700
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.91208661225048320843411267792682529711958319026166768180832286032007986007409
Short name T417
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.44 seconds
Started Oct 29 12:29:04 PM PDT 23
Finished Oct 29 12:29:11 PM PDT 23
Peak memory 201024 kb
Host smart-4aa4c6bf-9ed3-42e9-bed0-39fefcb93d0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91208661225048320843411267792682529711958319026166768180832286032007986007409 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.912086612250483208434112677926825297119583190261667681808322
86032007986007409
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.59993411889543194496069545676851849271820092465726148711586985125328736540079
Short name T137
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.4 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:29:01 PM PDT 23
Peak memory 200992 kb
Host smart-94e74224-b337-419c-9a68-177f2cfacd3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59993411889543194496069545676851849271820092465726148711586985125328736540079 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.5999341188954319449606954567685184927182009246572614871158698512
5328736540079
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.80346031662383120648120739612387536968361787284867735723235545521864492682484
Short name T232
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.76 seconds
Started Oct 29 12:28:52 PM PDT 23
Finished Oct 29 12:28:57 PM PDT 23
Peak memory 201016 kb
Host smart-894cf1ac-643b-4f20-bedc-7fee07b23b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80346031662383120648120739612387536968361787284867735723235545521864492682484 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.80346031662383120648120739612387536968361787284867735723235545521864492682484
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.94524642611731196968112556743146098953890873931226448571363106742919721181733
Short name T598
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 29 12:29:04 PM PDT 23
Finished Oct 29 12:29:09 PM PDT 23
Peak memory 201044 kb
Host smart-78405c56-81a5-4546-87cc-2942a23132c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94524642611731196968112556743146098953890873931226448571363106742919721181733 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.94524642611731196968112556743146098953890873931226448571363106742919721181733
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.21329632737115137765501336214268284899625123725195756238356022477141826281896
Short name T435
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.84 seconds
Started Oct 29 12:28:59 PM PDT 23
Finished Oct 29 12:29:03 PM PDT 23
Peak memory 200992 kb
Host smart-dfd192f6-3ede-45de-abef-0de4e2da58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21329632737115137765501336214268284899625123725195756238356022477141826281896 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.21329632737115137765501336214268284899625123725195756238356022477141826281896
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.47990761517470388802895831251626074338270719075580108672776997626744928325860
Short name T460
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Oct 29 12:28:59 PM PDT 23
Finished Oct 29 12:29:04 PM PDT 23
Peak memory 201008 kb
Host smart-68aa2889-cfaf-4c96-a9a4-fb892f12bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47990761517470388802895831251626074338270719075580108672776997626744928325860 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.47990761517470388802895831251626074338270719075580108672776997626744928325860
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.77230393287961863278339416670395410041258805324094147614032545052733816527717
Short name T486
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 29 12:29:01 PM PDT 23
Finished Oct 29 12:29:06 PM PDT 23
Peak memory 200944 kb
Host smart-3c0bb1a8-815a-41b5-842d-8e80a29e9fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77230393287961863278339416670395410041258805324094147614032545052733816527717 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sysrst_ctrl_smoke.77230393287961863278339416670395410041258805324094147614032545052733816527717
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.61605003869737743887323207861573512474495784156180513437236518829197947767506
Short name T477
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.91 seconds
Started Oct 29 12:28:58 PM PDT 23
Finished Oct 29 12:31:16 PM PDT 23
Peak memory 201284 kb
Host smart-43d74afd-9fa6-4939-be23-8dc5bef5e87f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61605003869737743887323207861573512474495784156180513437236518829197947767506 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.61605003869737743887323207861573512474495784156180513437236518829197947767506
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.37837656017064294705537896425137567385043742964935298156765902576795666521780
Short name T35
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.91 seconds
Started Oct 29 12:28:54 PM PDT 23
Finished Oct 29 12:28:59 PM PDT 23
Peak memory 200996 kb
Host smart-943a6ae6-dfb2-48ca-a73f-67bd3c85371d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37837656017064294705537896425137567385043742964935298156765902576795666521780 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.378376560170642947055378964251375673850437429649352981567659
02576795666521780
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.96072437238229336913633265840200454656083865110581486723712263136911420394817
Short name T548
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.76 seconds
Started Oct 29 12:27:47 PM PDT 23
Finished Oct 29 12:27:53 PM PDT 23
Peak memory 201016 kb
Host smart-b59ff558-7946-4f7b-b7df-10585d9c5c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96072437238229336913633265840200454656083865110581486723712263136911420394817 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.96072437238229336913633265840200454656083865110581486723712263136911420394817
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.60131548173692106325329600831334355484877787955130972408811262246440623873314
Short name T100
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.58 seconds
Started Oct 29 12:27:50 PM PDT 23
Finished Oct 29 12:27:56 PM PDT 23
Peak memory 201108 kb
Host smart-ce8fae8f-b311-45fe-89a3-25214664ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60131548173692106325329600831334355484877787955130972408811262246440623873314 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.60131548173692106325329600831334355484877787955130972408811262246440623873314
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.33620353160509477539235173075704542036373347314840218260617612254076991108948
Short name T30
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.5 seconds
Started Oct 29 12:27:47 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201080 kb
Host smart-f1648931-f911-4a2a-be8a-e119a8e1dcc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33620353160509477539235173075704542036373347314840218260617612254076991108948 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.336203531605094775392351730757045420363733473148402182606176122
54076991108948
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.109145887190003380588865047951107041303333771196790168939019041736816243320981
Short name T109
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.26 seconds
Started Oct 29 12:27:46 PM PDT 23
Finished Oct 29 12:27:54 PM PDT 23
Peak memory 201032 kb
Host smart-ee53c82f-0b67-4694-837d-b3c180748736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109145887190003380588865047951107041303333771196790168939019041736816243320981 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.109145887190003380588865047951107041303333771196790168939019041736816243320981
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.11764771769830756356232537126629956017904160076202038927889125306411810718970
Short name T115
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.5 seconds
Started Oct 29 12:27:41 PM PDT 23
Finished Oct 29 12:27:46 PM PDT 23
Peak memory 201300 kb
Host smart-57ffa9bf-e39d-4b13-a73d-8dedaae473a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11764771769830756356232537126629956017904160076202038927889125306411810718970 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.11764771769830756356232537126629956017904160076202038
927889125306411810718970
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.75740051480874577242785147647669658911187945055051147828690200521665494607110
Short name T657
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.44 seconds
Started Oct 29 12:27:39 PM PDT 23
Finished Oct 29 12:27:47 PM PDT 23
Peak memory 201000 kb
Host smart-97248a12-24f2-42af-a77a-0ad5daec5930
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75740051480874577242785147647669658911187945055051147828690200521665494607110 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.7574005148087457724278514764766965891118794505505114782869020
0521665494607110
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.83126675364809318566733956908389027322866777219826880857563939196216287528183
Short name T236
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.35 seconds
Started Oct 29 12:27:43 PM PDT 23
Finished Oct 29 12:27:50 PM PDT 23
Peak memory 200980 kb
Host smart-dd3834ba-1679-46f9-9191-efdce1192b76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83126675364809318566733956908389027322866777219826880857563939196216287528183 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.83126675364809318566733956908389027322866777219826880857563939196216287528183
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.51073211866696430362093478289948873995532797664667615907019105217765591821749
Short name T511
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 29 12:28:15 PM PDT 23
Finished Oct 29 12:28:20 PM PDT 23
Peak memory 200980 kb
Host smart-fbaa77fa-b491-46c3-992e-49d9730b0041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51073211866696430362093478289948873995532797664667615907019105217765591821749 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.51073211866696430362093478289948873995532797664667615907019105217765591821749
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.31648296437672304024940219501233181398844976018159292946730132794854274443405
Short name T582
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 29 12:27:57 PM PDT 23
Finished Oct 29 12:28:02 PM PDT 23
Peak memory 201024 kb
Host smart-8523daf4-08ec-46ed-88cb-d5f6bd046933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31648296437672304024940219501233181398844976018159292946730132794854274443405 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.31648296437672304024940219501233181398844976018159292946730132794854274443405
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.114279455306743299920824427694755223442992721256213605707890477439485927887500
Short name T648
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 29 12:28:55 PM PDT 23
Finished Oct 29 12:28:59 PM PDT 23
Peak memory 200816 kb
Host smart-6e9b5731-9ca9-4f88-a3fe-3c1930a92f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114279455306743299920824427694755223442992721256213605707890477439485927887500 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.114279455306743299920824427694755223442992721256213605707890477439485927887500
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.92411583166809223104724612576935941092654046190760000828438771450018529043058
Short name T317
Test name
Test status
Simulation time 2515402263 ps
CPU time 5.03 seconds
Started Oct 29 12:27:46 PM PDT 23
Finished Oct 29 12:27:54 PM PDT 23
Peak memory 201020 kb
Host smart-0af14707-b275-431c-ab83-fe2e288c64c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92411583166809223104724612576935941092654046190760000828438771450018529043058 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.92411583166809223104724612576935941092654046190760000828438771450018529043058
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.44413734613996707068498353335960952804232726748543372761452983987879754231249
Short name T146
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.4 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:30:08 PM PDT 23
Peak memory 221404 kb
Host smart-d0bb2302-544e-4f12-bf95-a5cb70cd4f6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44413734613996707068498353335960952804232726748543372761452983987879754231249 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.44413734613996707068498353335960952804232726748543372761452983987879754231249
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.110801215914895016989845609031754011180550004438933313412379585813285738458686
Short name T595
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 29 12:27:50 PM PDT 23
Finished Oct 29 12:27:55 PM PDT 23
Peak memory 200980 kb
Host smart-f73fbc15-9046-4010-97b4-2dce6a977122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110801215914895016989845609031754011180550004438933313412379585813285738458686 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.sysrst_ctrl_smoke.110801215914895016989845609031754011180550004438933313412379585813285738458686
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.102599751584523856106233401108793336587008984927592882206174530626356287470090
Short name T129
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.1 seconds
Started Oct 29 12:27:47 PM PDT 23
Finished Oct 29 12:30:06 PM PDT 23
Peak memory 201224 kb
Host smart-5c1b2119-bca9-4bf1-98f2-6ed83584b7ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102599751584523856106233401108793336587008984927592882206174530626356287470090 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.102599751584523856106233401108793336587008984927592882206174530626356287470090
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.106988188400882012790109330526965814490938618171112989222326696874326989428235
Short name T496
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.83 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 200724 kb
Host smart-09778759-8e5f-4be9-a719-5e3b919d5a4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106988188400882012790109330526965814490938618171112989222326696874326989428235 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.106988188400882012790109330526965814490938618171112989222326
696874326989428235
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.61289200990899043042944718816887446157097800791661505449023621252182932992382
Short name T211
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 29 12:29:09 PM PDT 23
Finished Oct 29 12:29:13 PM PDT 23
Peak memory 201472 kb
Host smart-3777ba8d-d775-47a5-ae8f-e7d67609fce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61289200990899043042944718816887446157097800791661505449023621252182932992382 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.61289200990899043042944718816887446157097800791661505449023621252182932992382
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.10571013249088642897729413572981042383837186327606183788321605580078965743564
Short name T363
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.58 seconds
Started Oct 29 12:29:08 PM PDT 23
Finished Oct 29 12:29:14 PM PDT 23
Peak memory 201044 kb
Host smart-6a8cf141-60fe-4172-b5f8-eec109d62ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10571013249088642897729413572981042383837186327606183788321605580078965743564 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.10571013249088642897729413572981042383837186327606183788321605580078965743564
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.36194069094748211367542360739051407722121875743515948612857493915401529445544
Short name T174
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.69 seconds
Started Oct 29 12:29:08 PM PDT 23
Finished Oct 29 12:32:13 PM PDT 23
Peak memory 201252 kb
Host smart-05c10d49-b9c5-47b3-a565-2b8755f2043b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36194069094748211367542360739051407722121875743515948612857493915401529445544 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.36194069094748211367542360739051407722121875743515948612857493
915401529445544
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.108278434408165685350981387730342677281258255184687902271485939434965309236031
Short name T45
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 29 12:29:05 PM PDT 23
Finished Oct 29 12:29:13 PM PDT 23
Peak memory 200892 kb
Host smart-ed3c9458-32e0-4e73-ba1d-e2c2871a4ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108278434408165685350981387730342677281258255184687902271485939434965309236031 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.10827843440816568535098138773034267728125825518468790227148
5939434965309236031
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.105174879759628167651137942331424507073183931934179850801549980554716931119197
Short name T34
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.57 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:20 PM PDT 23
Peak memory 201024 kb
Host smart-cf962fe4-05fa-44d8-8da8-fd6daed03cff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105174879759628167651137942331424507073183931934179850801549980554716931119197 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.105174879759628167651137942331424507073183931934179850801549980
554716931119197
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.98897049513562852468992433987922917077714389128482515979365567104263810703058
Short name T38
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 29 12:30:07 PM PDT 23
Finished Oct 29 12:30:13 PM PDT 23
Peak memory 201016 kb
Host smart-d1e2a121-2cfa-4bc0-85f6-e71e9ce70936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98897049513562852468992433987922917077714389128482515979365567104263810703058 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.98897049513562852468992433987922917077714389128482515979365567104263810703058
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.81238073060049262260326692198297753732965788327340311114912821708201679706897
Short name T305
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 29 12:29:10 PM PDT 23
Finished Oct 29 12:29:16 PM PDT 23
Peak memory 201024 kb
Host smart-55307cb8-f2fe-4d44-8a6b-315ef0d187d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81238073060049262260326692198297753732965788327340311114912821708201679706897 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.81238073060049262260326692198297753732965788327340311114912821708201679706897
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.55313482976034635449951534555924367833466162417751107277278391123196134302244
Short name T148
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.89 seconds
Started Oct 29 12:29:04 PM PDT 23
Finished Oct 29 12:29:09 PM PDT 23
Peak memory 200968 kb
Host smart-d5ab8ec9-4509-4709-9304-2348a7d69a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55313482976034635449951534555924367833466162417751107277278391123196134302244 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.55313482976034635449951534555924367833466162417751107277278391123196134302244
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.114299918638316833245124788053348025764980037782046631510126416688556770468878
Short name T319
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 29 12:29:06 PM PDT 23
Finished Oct 29 12:29:11 PM PDT 23
Peak memory 200756 kb
Host smart-abbd99ee-b0c9-44ea-bec9-b5f5cfa70d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114299918638316833245124788053348025764980037782046631510126416688556770468878 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.114299918638316833245124788053348025764980037782046631510126416688556770468878
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.48733281376793253441300339057633813873325230583490379736461132428129336435216
Short name T106
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:29:06 PM PDT 23
Peak memory 200956 kb
Host smart-7dee7eb2-1025-4a58-b00e-d25383517f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48733281376793253441300339057633813873325230583490379736461132428129336435216 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_smoke.48733281376793253441300339057633813873325230583490379736461132428129336435216
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.60804643071042163942453858464962208296587344713009138123197002049045216617269
Short name T552
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.05 seconds
Started Oct 29 12:29:04 PM PDT 23
Finished Oct 29 12:31:22 PM PDT 23
Peak memory 201268 kb
Host smart-f72bf5bc-81d0-4bc1-8dc9-7f8a505f75d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60804643071042163942453858464962208296587344713009138123197002049045216617269 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.60804643071042163942453858464962208296587344713009138123197002049045216617269
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.10503945284883336184980839216756742620285117445161972488616541887412781632247
Short name T661
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Oct 29 12:29:08 PM PDT 23
Finished Oct 29 12:29:13 PM PDT 23
Peak memory 200796 kb
Host smart-55390e2d-d27c-47ab-89e1-643ad7ad58e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10503945284883336184980839216756742620285117445161972488616541887412781632247 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.105039452848833361849808392167567426202851174451619724886165
41887412781632247
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.33784324801978176533646045996474687832664233334298807352304709790853306542810
Short name T228
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 29 12:29:18 PM PDT 23
Finished Oct 29 12:29:22 PM PDT 23
Peak memory 201008 kb
Host smart-af9d70b5-1729-4d0d-a735-2f3314418acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33784324801978176533646045996474687832664233334298807352304709790853306542810 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.33784324801978176533646045996474687832664233334298807352304709790853306542810
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.24243902798423349290923023819388558836852622149360446047608187644344656535013
Short name T406
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.62 seconds
Started Oct 29 12:29:11 PM PDT 23
Finished Oct 29 12:29:17 PM PDT 23
Peak memory 201044 kb
Host smart-71d5ce94-4144-4d64-9e82-db9c7da509b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24243902798423349290923023819388558836852622149360446047608187644344656535013 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.24243902798423349290923023819388558836852622149360446047608187644344656535013
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.44705851116332920069914904799719438425408056975849938132700461665789588006623
Short name T126
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.93 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:32:19 PM PDT 23
Peak memory 201240 kb
Host smart-cb5578b8-b66b-47d7-920b-91ae8b32d86a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44705851116332920069914904799719438425408056975849938132700461665789588006623 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.44705851116332920069914904799719438425408056975849938132700461
665789588006623
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.9921422731705907115319110061309041568866872688608989645085005343315243320786
Short name T618
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.8 seconds
Started Oct 29 12:29:12 PM PDT 23
Finished Oct 29 12:29:20 PM PDT 23
Peak memory 201028 kb
Host smart-9e30663c-35e9-4ff7-ae27-14a8ae4d9911
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9921422731705907115319110061309041568866872688608989645085005343315243320786 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.9921422731705907115319110061309041568866872688608989645085005
343315243320786
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.76595186488920328920377939688799095270185064468903075045404749507526555336997
Short name T581
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Oct 29 12:29:11 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 200992 kb
Host smart-815aa48c-0f26-4f77-b30b-4fb498188440
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76595186488920328920377939688799095270185064468903075045404749507526555336997 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.7659518648892032892037793968879909527018506446890307504540474950
7526555336997
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.45091240398254979179865714474189042715211963666027644829874489957447993564932
Short name T377
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.75 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:19 PM PDT 23
Peak memory 201064 kb
Host smart-845b561f-df8b-4da3-838a-34a4f374bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45091240398254979179865714474189042715211963666027644829874489957447993564932 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.45091240398254979179865714474189042715211963666027644829874489957447993564932
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.112452792026757988832272410750069976419457323854050671934847929939973328485227
Short name T272
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 29 12:29:13 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 201096 kb
Host smart-8ef0562e-516e-4649-af68-8aa658536988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112452792026757988832272410750069976419457323854050671934847929939973328485227 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.112452792026757988832272410750069976419457323854050671934847929939973328485227
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.38918585974327774881620272601283395699727030609614039953837703460233356718517
Short name T452
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 201032 kb
Host smart-ab48cd3f-43fa-464c-ae8a-883e82073d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38918585974327774881620272601283395699727030609614039953837703460233356718517 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.38918585974327774881620272601283395699727030609614039953837703460233356718517
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.107636891090226478448834016322901235503695283346354380096738946055615868414674
Short name T571
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 29 12:29:10 PM PDT 23
Finished Oct 29 12:29:15 PM PDT 23
Peak memory 201472 kb
Host smart-e4d5247c-4902-489a-b9a4-413c128a7122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107636891090226478448834016322901235503695283346354380096738946055615868414674 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.107636891090226478448834016322901235503695283346354380096738946055615868414674
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.17611731207433198161644166316668251213294074678606260960336260547642835002582
Short name T567
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 200996 kb
Host smart-b7b7f5b4-dd61-419d-9b15-33a3a4171414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17611731207433198161644166316668251213294074678606260960336260547642835002582 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_smoke.17611731207433198161644166316668251213294074678606260960336260547642835002582
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.70391932603397838128641186954914903855076809325439375338616415265311182962598
Short name T130
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.03 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:31:33 PM PDT 23
Peak memory 201284 kb
Host smart-ded63050-63b3-4708-b9c5-b2da85395112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70391932603397838128641186954914903855076809325439375338616415265311182962598 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.70391932603397838128641186954914903855076809325439375338616415265311182962598
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.9187441060532843296302504997596463302143213464666195498808682296539659783882
Short name T280
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 29 12:30:25 PM PDT 23
Finished Oct 29 12:30:30 PM PDT 23
Peak memory 201000 kb
Host smart-fed3972c-ce83-4f4f-adf2-470ad5bcfebc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9187441060532843296302504997596463302143213464666195498808682296539659783882 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.9187441060532843296302504997596463302143213464666195498808682
296539659783882
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.73375880348131447151398099734613872757175375193675032231660870457468348939448
Short name T202
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:29:24 PM PDT 23
Peak memory 201008 kb
Host smart-90de9503-b38d-4610-bc51-5b2536fe465e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73375880348131447151398099734613872757175375193675032231660870457468348939448 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.73375880348131447151398099734613872757175375193675032231660870457468348939448
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.26297637645824327135679493297570831407418086572738528329487107532026322565900
Short name T208
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.58 seconds
Started Oct 29 12:29:13 PM PDT 23
Finished Oct 29 12:29:19 PM PDT 23
Peak memory 201088 kb
Host smart-61f2bd34-f35a-496b-8145-3a898acf70e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26297637645824327135679493297570831407418086572738528329487107532026322565900 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.26297637645824327135679493297570831407418086572738528329487107532026322565900
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.82372717707004730597964221143469289451071476845525872550897074626219142505388
Short name T325
Test name
Test status
Simulation time 118289458206 ps
CPU time 186.55 seconds
Started Oct 29 12:29:08 PM PDT 23
Finished Oct 29 12:32:15 PM PDT 23
Peak memory 201244 kb
Host smart-c068fa4d-3112-4451-849b-cd851210a570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82372717707004730597964221143469289451071476845525872550897074626219142505388 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.82372717707004730597964221143469289451071476845525872550897074
626219142505388
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.40509488589148188323192418150779226734891992832210815042475118007137600109804
Short name T251
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 29 12:29:10 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 201036 kb
Host smart-621f1f0a-bdfb-4f19-9970-59072a436d4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40509488589148188323192418150779226734891992832210815042475118007137600109804 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.405094885891481883231924181507792267348919928322108150424751
18007137600109804
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.73546097193845099272414123614536722899285684080897136713407355379212012738119
Short name T23
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:29:23 PM PDT 23
Peak memory 200988 kb
Host smart-71fd5d28-5d57-4331-9848-7374068888b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73546097193845099272414123614536722899285684080897136713407355379212012738119 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.7354609719384509927241412361453672289928568408089713671340735537
9212012738119
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.92692013058225385550737909779490015017436451201530670944342113195057627390331
Short name T205
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:29:21 PM PDT 23
Peak memory 200996 kb
Host smart-b38d5a71-94b8-4624-b7a1-9915cb2d779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92692013058225385550737909779490015017436451201530670944342113195057627390331 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.92692013058225385550737909779490015017436451201530670944342113195057627390331
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.52242426972861510685929751085695621946144839253886732279244868133979645355433
Short name T43
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.89 seconds
Started Oct 29 12:29:29 PM PDT 23
Finished Oct 29 12:29:36 PM PDT 23
Peak memory 201052 kb
Host smart-0b9041ea-3bba-4b12-a571-2031c170ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52242426972861510685929751085695621946144839253886732279244868133979645355433 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.52242426972861510685929751085695621946144839253886732279244868133979645355433
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.63065809614978641897358992750196311886105559594715914987663734756761516292828
Short name T644
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.96 seconds
Started Oct 29 12:29:08 PM PDT 23
Finished Oct 29 12:29:12 PM PDT 23
Peak memory 200968 kb
Host smart-31ec35bd-3feb-416c-830a-daeaac8ab0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63065809614978641897358992750196311886105559594715914987663734756761516292828 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.63065809614978641897358992750196311886105559594715914987663734756761516292828
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.54889019265994911057144674462527641607380173727333187275763699195647825848965
Short name T536
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 29 12:29:18 PM PDT 23
Finished Oct 29 12:29:23 PM PDT 23
Peak memory 201012 kb
Host smart-9b16fd05-83ad-4256-9f75-ed209a1907fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54889019265994911057144674462527641607380173727333187275763699195647825848965 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.54889019265994911057144674462527641607380173727333187275763699195647825848965
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.83250760595656921372836809599362690718718108959206310442170240207692598963524
Short name T651
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Oct 29 12:29:12 PM PDT 23
Finished Oct 29 12:29:16 PM PDT 23
Peak memory 200956 kb
Host smart-3d805b9a-044a-489f-b696-3731b20b72d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83250760595656921372836809599362690718718108959206310442170240207692598963524 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_smoke.83250760595656921372836809599362690718718108959206310442170240207692598963524
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.76039360730167772715662651519920589975673997261534406897918186727071007846658
Short name T428
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.88 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:31:33 PM PDT 23
Peak memory 201284 kb
Host smart-1af3cb79-1826-4821-ba27-c160a985f1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76039360730167772715662651519920589975673997261534406897918186727071007846658 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.76039360730167772715662651519920589975673997261534406897918186727071007846658
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.40868354609638192558302561965421752773797821894076148856686428483469743834465
Short name T538
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 29 12:29:11 PM PDT 23
Finished Oct 29 12:29:16 PM PDT 23
Peak memory 201452 kb
Host smart-d89c8d29-48fe-4999-aa0c-e83c6a3117e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40868354609638192558302561965421752773797821894076148856686428483469743834465 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.408683546096381925583025619654217527737978218940761488566864
28483469743834465
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.86310891273585076373252352850260426136655977089023780353594332132244627144690
Short name T390
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 200980 kb
Host smart-7d49b744-c039-44d2-9934-9786adcc7ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86310891273585076373252352850260426136655977089023780353594332132244627144690 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.86310891273585076373252352850260426136655977089023780353594332132244627144690
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.91942672692889969383036079523846045421208021186931592850641168412643708196944
Short name T525
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.73 seconds
Started Oct 29 12:29:11 PM PDT 23
Finished Oct 29 12:29:17 PM PDT 23
Peak memory 201072 kb
Host smart-c06019d8-174b-4b46-b2e7-ec0f53ddad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91942672692889969383036079523846045421208021186931592850641168412643708196944 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.91942672692889969383036079523846045421208021186931592850641168412643708196944
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.33661332055067753334113428362136004381031305848981816058645553026221780568194
Short name T405
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.93 seconds
Started Oct 29 12:29:17 PM PDT 23
Finished Oct 29 12:32:21 PM PDT 23
Peak memory 201248 kb
Host smart-fd1ac9f8-44a5-4e14-a93c-91aff10cb95c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661332055067753334113428362136004381031305848981816058645553026221780568194 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.33661332055067753334113428362136004381031305848981816058645553
026221780568194
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.76081831811842915808337288429668695772581988873055235458671357543011386164736
Short name T380
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Oct 29 12:29:22 PM PDT 23
Finished Oct 29 12:29:30 PM PDT 23
Peak memory 201056 kb
Host smart-cfb956c1-0054-4546-8e2a-3d66f7828779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76081831811842915808337288429668695772581988873055235458671357543011386164736 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.760818318118429158083372884296686957725819888730552354586713
57543011386164736
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.24900424940223722553974146765793791827633808000581062819425173806237842270549
Short name T357
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.4 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 199784 kb
Host smart-39fe382d-e439-45bd-b389-e3ae42b8df32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900424940223722553974146765793791827633808000581062819425173806237842270549 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.2490042494022372255397414676579379182763380800058106281942517380
6237842270549
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.71104029266271915581659268501950133137412186071084525447595193698790796761174
Short name T323
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:29:21 PM PDT 23
Peak memory 200984 kb
Host smart-74431f25-265d-4f78-bf44-102d7b8b550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71104029266271915581659268501950133137412186071084525447595193698790796761174 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.71104029266271915581659268501950133137412186071084525447595193698790796761174
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.23264030809319976330081311247763245485550188345810860711630997588751681264707
Short name T546
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 29 12:29:10 PM PDT 23
Finished Oct 29 12:29:15 PM PDT 23
Peak memory 201024 kb
Host smart-4d6fd966-2ec6-40bf-983d-b52c5a194d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23264030809319976330081311247763245485550188345810860711630997588751681264707 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.23264030809319976330081311247763245485550188345810860711630997588751681264707
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.87884635472048768888906081501447495501871589155752395902256175102808979582335
Short name T542
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.98 seconds
Started Oct 29 12:29:11 PM PDT 23
Finished Oct 29 12:29:15 PM PDT 23
Peak memory 200948 kb
Host smart-bc465be9-99c1-418c-8d15-60165f93cdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87884635472048768888906081501447495501871589155752395902256175102808979582335 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.87884635472048768888906081501447495501871589155752395902256175102808979582335
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.104554262861013668270250719857438373791824281968270925071505766189732095192726
Short name T246
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.7 seconds
Started Oct 29 12:29:19 PM PDT 23
Finished Oct 29 12:29:24 PM PDT 23
Peak memory 201296 kb
Host smart-46b0a57b-a282-445a-b6f9-b98eaec8fb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104554262861013668270250719857438373791824281968270925071505766189732095192726 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.104554262861013668270250719857438373791824281968270925071505766189732095192726
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.38993762124172350917636170107296316349276857040723308497929395900155931724291
Short name T42
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.97 seconds
Started Oct 29 12:29:26 PM PDT 23
Finished Oct 29 12:29:31 PM PDT 23
Peak memory 200952 kb
Host smart-906aa7b3-3a29-4b97-ad57-21bea7676ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38993762124172350917636170107296316349276857040723308497929395900155931724291 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sysrst_ctrl_smoke.38993762124172350917636170107296316349276857040723308497929395900155931724291
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.6544937540860344471949310546217203318538027607795095868737592760315895340163
Short name T29
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.57 seconds
Started Oct 29 12:29:15 PM PDT 23
Finished Oct 29 12:31:33 PM PDT 23
Peak memory 201292 kb
Host smart-9dae277e-adb7-442a-a5b3-4aec8c0a8d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6544937540860344471949310546217203318538027607795095868737592760315895340163 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.6544937540860344471949310546217203318538027607795095868737592760315895340163
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2109843453012328031247838114235664379257089566036353685016647697007373113127
Short name T617
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 29 12:29:23 PM PDT 23
Finished Oct 29 12:29:29 PM PDT 23
Peak memory 201148 kb
Host smart-5c90958f-0052-40cd-bdb7-972e90ef0316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109843453012328031247838114235664379257089566036353685016647697007373113127 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.2109843453012328031247838114235664379257089566036353685016647
697007373113127
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.29725960584941025594163108495843734187769654414051665072094401187942029619437
Short name T615
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 29 12:29:31 PM PDT 23
Finished Oct 29 12:29:36 PM PDT 23
Peak memory 201020 kb
Host smart-3a35f1c7-23fa-4b7d-8cea-40ce83582384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29725960584941025594163108495843734187769654414051665072094401187942029619437 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.29725960584941025594163108495843734187769654414051665072094401187942029619437
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.11311779100470047792651015410447054519060879804020946360348584771678713208834
Short name T402
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Oct 29 12:29:18 PM PDT 23
Finished Oct 29 12:29:24 PM PDT 23
Peak memory 201364 kb
Host smart-eff51aa0-166e-46e0-a0ad-78d37f0cd68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11311779100470047792651015410447054519060879804020946360348584771678713208834 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.11311779100470047792651015410447054519060879804020946360348584771678713208834
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.42394115360734487591047957195861281751547722336320962621729053750793241626786
Short name T666
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.8 seconds
Started Oct 29 12:29:23 PM PDT 23
Finished Oct 29 12:32:26 PM PDT 23
Peak memory 201396 kb
Host smart-826fc8d5-6844-454f-9d24-5b2a35909b3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42394115360734487591047957195861281751547722336320962621729053750793241626786 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.42394115360734487591047957195861281751547722336320962621729053
750793241626786
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.53392895744805212257256137353504212218852020638336091157959959091505439475949
Short name T366
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 29 12:29:15 PM PDT 23
Finished Oct 29 12:29:23 PM PDT 23
Peak memory 201072 kb
Host smart-28a6ac28-5bc9-40c3-a971-f348cdb409be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53392895744805212257256137353504212218852020638336091157959959091505439475949 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.533928957448052122572561373535042122188520206383360911579599
59091505439475949
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2647709651276833788678757723313798710197050700833327976894966781350893707966
Short name T240
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Oct 29 12:29:25 PM PDT 23
Finished Oct 29 12:29:32 PM PDT 23
Peak memory 200996 kb
Host smart-745073b7-7baa-4e5b-a5a3-aa088032d330
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647709651276833788678757723313798710197050700833327976894966781350893707966 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.2647709651276833788678757723313798710197050700833327976894966781350893707966
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.45876718392821770277353196095647236604590333654848148396101354786322338194453
Short name T355
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 29 12:29:17 PM PDT 23
Finished Oct 29 12:29:22 PM PDT 23
Peak memory 201008 kb
Host smart-1f6c9e8e-4b92-4ee8-930d-1eb60fdc78aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45876718392821770277353196095647236604590333654848148396101354786322338194453 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.45876718392821770277353196095647236604590333654848148396101354786322338194453
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.98155196913309217516145710630778596901031089406335754953292115837071227098177
Short name T215
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.95 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:29:22 PM PDT 23
Peak memory 201040 kb
Host smart-7623c7d1-0fb6-430a-ade7-18646dcbf014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98155196913309217516145710630778596901031089406335754953292115837071227098177 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.98155196913309217516145710630778596901031089406335754953292115837071227098177
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.65819336568320582491309448571734436419700574133385284095150624242364944268804
Short name T267
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.88 seconds
Started Oct 29 12:29:21 PM PDT 23
Finished Oct 29 12:29:25 PM PDT 23
Peak memory 200952 kb
Host smart-01b51074-e6b2-4bac-9c5e-6e023470f7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65819336568320582491309448571734436419700574133385284095150624242364944268804 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.65819336568320582491309448571734436419700574133385284095150624242364944268804
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.15996196507976342432614392475985415770230241529960177592562602607349647422439
Short name T492
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.69 seconds
Started Oct 29 12:29:20 PM PDT 23
Finished Oct 29 12:29:25 PM PDT 23
Peak memory 201012 kb
Host smart-bc031c93-1d0f-4296-b034-49af1069228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15996196507976342432614392475985415770230241529960177592562602607349647422439 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.15996196507976342432614392475985415770230241529960177592562602607349647422439
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.90897036262496135195234843397304457582836488414824496113774785457254849537400
Short name T188
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 29 12:29:16 PM PDT 23
Finished Oct 29 12:29:20 PM PDT 23
Peak memory 200916 kb
Host smart-4427e050-fe36-45b9-8b85-dc86be481c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90897036262496135195234843397304457582836488414824496113774785457254849537400 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_smoke.90897036262496135195234843397304457582836488414824496113774785457254849537400
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.34621612340624347999583879126686495006653686268506513364900300620814568335301
Short name T333
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.96 seconds
Started Oct 29 12:29:29 PM PDT 23
Finished Oct 29 12:31:49 PM PDT 23
Peak memory 201296 kb
Host smart-f204b6ed-503b-4edc-8b9e-a103b838e3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34621612340624347999583879126686495006653686268506513364900300620814568335301 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.34621612340624347999583879126686495006653686268506513364900300620814568335301
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.35798202761355984804646486849748615201234132792881748430303159847212966872545
Short name T411
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.82 seconds
Started Oct 29 12:29:15 PM PDT 23
Finished Oct 29 12:29:20 PM PDT 23
Peak memory 201016 kb
Host smart-2c623a38-9d41-4018-a058-e8920e9579c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35798202761355984804646486849748615201234132792881748430303159847212966872545 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.357982027613559848046464868497486152012341327928817484303031
59847212966872545
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.25716707840852290327324852698767955872283558253433534013052998363515848054549
Short name T241
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:45 PM PDT 23
Peak memory 201020 kb
Host smart-e23aea2d-a982-4b45-b488-6090ba57ff1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25716707840852290327324852698767955872283558253433534013052998363515848054549 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.25716707840852290327324852698767955872283558253433534013052998363515848054549
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.114936926663815791881149023262274815959317186181395211419225297978346265949571
Short name T234
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 29 12:29:28 PM PDT 23
Finished Oct 29 12:29:37 PM PDT 23
Peak memory 201084 kb
Host smart-bbe83ec9-5ada-4469-8bd3-945e1daa01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114936926663815791881149023262274815959317186181395211419225297978346265949571 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.114936926663815791881149023262274815959317186181395211419225297978346265949571
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.76548210047975946006791892125081359605637095896433449772600944359444873561407
Short name T608
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.78 seconds
Started Oct 29 12:29:35 PM PDT 23
Finished Oct 29 12:32:42 PM PDT 23
Peak memory 201260 kb
Host smart-3123276c-2ab5-4e2f-89f6-f8f00a2aed45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76548210047975946006791892125081359605637095896433449772600944359444873561407 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.76548210047975946006791892125081359605637095896433449772600944
359444873561407
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.88259361360721800334845969239893004083051490260627258666845477525276396978374
Short name T555
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.73 seconds
Started Oct 29 12:29:23 PM PDT 23
Finished Oct 29 12:29:31 PM PDT 23
Peak memory 201040 kb
Host smart-8a21e769-dd20-4b40-8d01-a5e5639b86f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88259361360721800334845969239893004083051490260627258666845477525276396978374 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.882593613607218003348459692398930040830514902606272586668454
77525276396978374
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.104252408318706036132607918121996247880264915034456035034155280598591605553902
Short name T639
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 29 12:30:07 PM PDT 23
Finished Oct 29 12:30:13 PM PDT 23
Peak memory 200984 kb
Host smart-9b067549-59a8-4aaf-9780-a9551e177da0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104252408318706036132607918121996247880264915034456035034155280598591605553902 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.104252408318706036132607918121996247880264915034456035034155280
598591605553902
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.39218591618435369004294039858735461255938260496134076195525830737130619669433
Short name T41
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 29 12:29:22 PM PDT 23
Finished Oct 29 12:29:27 PM PDT 23
Peak memory 201012 kb
Host smart-0b8d0ac0-898a-41c7-8de4-7e430a0c7722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39218591618435369004294039858735461255938260496134076195525830737130619669433 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.39218591618435369004294039858735461255938260496134076195525830737130619669433
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.21297700815493571999008705029886386160174022644919688381170102386362071418831
Short name T332
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.93 seconds
Started Oct 29 12:29:21 PM PDT 23
Finished Oct 29 12:29:27 PM PDT 23
Peak memory 201008 kb
Host smart-9058c0e6-b66b-40d3-804a-7d44cc0e3479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21297700815493571999008705029886386160174022644919688381170102386362071418831 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.21297700815493571999008705029886386160174022644919688381170102386362071418831
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.62780380978113645872855778580903759540612122431404771574659483508710398741174
Short name T560
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Oct 29 12:29:30 PM PDT 23
Finished Oct 29 12:29:35 PM PDT 23
Peak memory 200992 kb
Host smart-a3c86ab7-1918-4886-a573-eade97831a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62780380978113645872855778580903759540612122431404771574659483508710398741174 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.62780380978113645872855778580903759540612122431404771574659483508710398741174
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.16656244042588008240464725831793266289162008917923625683350995129704730897279
Short name T534
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 29 12:29:38 PM PDT 23
Finished Oct 29 12:29:44 PM PDT 23
Peak memory 200240 kb
Host smart-f96d7884-fe2a-477f-82c2-e2ed32dafb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16656244042588008240464725831793266289162008917923625683350995129704730897279 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.16656244042588008240464725831793266289162008917923625683350995129704730897279
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.72927589339568709918612561487981240828271819860581059277577888329022296840055
Short name T313
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Oct 29 12:29:22 PM PDT 23
Finished Oct 29 12:29:26 PM PDT 23
Peak memory 200924 kb
Host smart-0222d145-c385-49d0-b565-c703c68b288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72927589339568709918612561487981240828271819860581059277577888329022296840055 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_smoke.72927589339568709918612561487981240828271819860581059277577888329022296840055
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.24106991895273466272034422684393656152712689349560823364017963621834767793234
Short name T663
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.26 seconds
Started Oct 29 12:29:18 PM PDT 23
Finished Oct 29 12:31:34 PM PDT 23
Peak memory 201432 kb
Host smart-79fdbea6-b4d4-4db7-a02d-358e8d4f6a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24106991895273466272034422684393656152712689349560823364017963621834767793234 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.24106991895273466272034422684393656152712689349560823364017963621834767793234
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.28649712700347382181559749345743147106052652791164590644593374075184672704767
Short name T125
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:46 PM PDT 23
Peak memory 201004 kb
Host smart-692473a8-7bbe-4856-b297-c14df9b19e87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28649712700347382181559749345743147106052652791164590644593374075184672704767 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.286497127003473821815597493457431471060526527911645906445933
74075184672704767
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.42171727291405574451936116361964775281744733552380794207217299861788596822267
Short name T278
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.76 seconds
Started Oct 29 12:29:24 PM PDT 23
Finished Oct 29 12:29:28 PM PDT 23
Peak memory 201008 kb
Host smart-d9f5eacb-2aeb-4445-a855-01462054038e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42171727291405574451936116361964775281744733552380794207217299861788596822267 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.42171727291405574451936116361964775281744733552380794207217299861788596822267
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.64480847594257618193804488893481734009512334904661151248992483176654922418212
Short name T591
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 29 12:29:23 PM PDT 23
Finished Oct 29 12:29:29 PM PDT 23
Peak memory 201096 kb
Host smart-9f1a52b3-7deb-4389-9f37-e49b21625def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64480847594257618193804488893481734009512334904661151248992483176654922418212 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.64480847594257618193804488893481734009512334904661151248992483176654922418212
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.86768139858286401087223615710177176558343429370749554080450955061834122908338
Short name T549
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.35 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:33:02 PM PDT 23
Peak memory 199028 kb
Host smart-f3c24b03-78ae-4cd0-831d-e9fabe3658a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86768139858286401087223615710177176558343429370749554080450955061834122908338 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.86768139858286401087223615710177176558343429370749554080450955
061834122908338
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.53750717708475519276403273606713169482732653735579381950005451931805513976561
Short name T398
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.47 seconds
Started Oct 29 12:30:07 PM PDT 23
Finished Oct 29 12:30:14 PM PDT 23
Peak memory 200892 kb
Host smart-1068e40b-1059-48d7-ba56-cbb637964c89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53750717708475519276403273606713169482732653735579381950005451931805513976561 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.537507177084755192764032736067131694827326537355793819500054
51931805513976561
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.101841361397527769721555154093473160810226134701112285304725426256449418160010
Short name T348
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 29 12:29:22 PM PDT 23
Finished Oct 29 12:29:29 PM PDT 23
Peak memory 201020 kb
Host smart-62e43c2a-b9c1-493b-93ec-0aa65d1dbafc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101841361397527769721555154093473160810226134701112285304725426256449418160010 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.101841361397527769721555154093473160810226134701112285304725426
256449418160010
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.112258003302921879126178241432206546857872754011157744636958299232561480728131
Short name T550
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 29 12:29:26 PM PDT 23
Finished Oct 29 12:29:32 PM PDT 23
Peak memory 201016 kb
Host smart-1ab1fcb8-e151-428d-bf78-f6b230287ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112258003302921879126178241432206546857872754011157744636958299232561480728131 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.112258003302921879126178241432206546857872754011157744636958299232561480728131
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.50734861632537744163686288994399340995014412981733799042240929788177259340348
Short name T110
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 29 12:29:24 PM PDT 23
Finished Oct 29 12:29:29 PM PDT 23
Peak memory 201080 kb
Host smart-09b52ba6-28ef-446a-b384-a28ba1bfa643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50734861632537744163686288994399340995014412981733799042240929788177259340348 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.50734861632537744163686288994399340995014412981733799042240929788177259340348
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.62518067303841348851439291379401857056038725506052310345291150830986199102037
Short name T122
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.91 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 198728 kb
Host smart-72dbcce3-653c-47f9-8220-4faca966b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62518067303841348851439291379401857056038725506052310345291150830986199102037 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.62518067303841348851439291379401857056038725506052310345291150830986199102037
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.105866074571303687847135775740216724217506093874425021835963209639480034354994
Short name T118
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.76 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:02 PM PDT 23
Peak memory 198724 kb
Host smart-c275c1fa-8ad6-41e7-86db-d367b06c5092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105866074571303687847135775740216724217506093874425021835963209639480034354994 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.105866074571303687847135775740216724217506093874425021835963209639480034354994
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.16898983285670695833026301175559338052517156934264650218579877134841615459436
Short name T227
Test name
Test status
Simulation time 2116887594 ps
CPU time 4.04 seconds
Started Oct 29 12:29:24 PM PDT 23
Finished Oct 29 12:29:29 PM PDT 23
Peak memory 200936 kb
Host smart-ca2d77b9-b33d-4361-8bbe-cb997e587cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16898983285670695833026301175559338052517156934264650218579877134841615459436 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_smoke.16898983285670695833026301175559338052517156934264650218579877134841615459436
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.31100079846553562706338004852850298291812726139236099385892056159341443115488
Short name T24
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.99 seconds
Started Oct 29 12:29:26 PM PDT 23
Finished Oct 29 12:31:43 PM PDT 23
Peak memory 201292 kb
Host smart-6e964898-2f14-4e52-bdfd-14b354dd3745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31100079846553562706338004852850298291812726139236099385892056159341443115488 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.31100079846553562706338004852850298291812726139236099385892056159341443115488
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.76701947875657230825064616729144942938477955965711007212630201759716553163785
Short name T649
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.85 seconds
Started Oct 29 12:29:31 PM PDT 23
Finished Oct 29 12:29:37 PM PDT 23
Peak memory 200980 kb
Host smart-2998894e-b3e1-475c-8d65-5162a883d6e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76701947875657230825064616729144942938477955965711007212630201759716553163785 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.767019478756572308250646167291449429384779559657110072126302
01759716553163785
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.41153726289195918882233368276491256123469688590078300353749843053169979415092
Short name T343
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:45 PM PDT 23
Peak memory 201004 kb
Host smart-164f8b2f-cb8b-4fe3-bbcc-2205e84ebda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153726289195918882233368276491256123469688590078300353749843053169979415092 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.41153726289195918882233368276491256123469688590078300353749843053169979415092
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.78047240764495584251318431069864434119623909201364204313601553378239500870867
Short name T238
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.78 seconds
Started Oct 29 12:29:24 PM PDT 23
Finished Oct 29 12:29:30 PM PDT 23
Peak memory 201056 kb
Host smart-47775fdb-fb70-4c97-b44b-6bcbff8aded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78047240764495584251318431069864434119623909201364204313601553378239500870867 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.78047240764495584251318431069864434119623909201364204313601553378239500870867
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.60607175630606394542119668020593507850635839497156798663887261154814309769710
Short name T221
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.05 seconds
Started Oct 29 12:29:37 PM PDT 23
Finished Oct 29 12:32:41 PM PDT 23
Peak memory 201244 kb
Host smart-7d615e4f-315c-476c-9724-4808c74d4e9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60607175630606394542119668020593507850635839497156798663887261154814309769710 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.60607175630606394542119668020593507850635839497156798663887261
154814309769710
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.91197473908997558138721666479539281906852139769370279792609652592891353606837
Short name T590
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 29 12:29:27 PM PDT 23
Finished Oct 29 12:29:38 PM PDT 23
Peak memory 201028 kb
Host smart-6e3fc5e8-66ef-4bd9-a000-571381075d68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91197473908997558138721666479539281906852139769370279792609652592891353606837 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.911974739089975581387216664795392819068521397693702797926096
52592891353606837
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.98916426134721530561351868103387292893789124199117199824325389776871874833112
Short name T445
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.41 seconds
Started Oct 29 12:29:40 PM PDT 23
Finished Oct 29 12:29:47 PM PDT 23
Peak memory 200980 kb
Host smart-2ffc3150-79e3-4f65-b11d-68391b620441
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98916426134721530561351868103387292893789124199117199824325389776871874833112 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.9891642613472153056135186810338729289378912419911719982432538977
6871874833112
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.40151708456558209818887848071028759943081147330139039118377115658532083068020
Short name T589
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.74 seconds
Started Oct 29 12:29:24 PM PDT 23
Finished Oct 29 12:29:29 PM PDT 23
Peak memory 201012 kb
Host smart-0f2cd385-5d83-4458-8220-05f637f3bc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40151708456558209818887848071028759943081147330139039118377115658532083068020 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.40151708456558209818887848071028759943081147330139039118377115658532083068020
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.65752937946914315446799070161288199074317142454485409877047444214493508028421
Short name T352
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 29 12:30:07 PM PDT 23
Finished Oct 29 12:30:12 PM PDT 23
Peak memory 201036 kb
Host smart-bd23f849-e3f4-4b5f-9bfb-5222c8daa7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65752937946914315446799070161288199074317142454485409877047444214493508028421 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.65752937946914315446799070161288199074317142454485409877047444214493508028421
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.103851676010661558360858192030322039138876297055751256766963945279281508766512
Short name T351
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 29 12:30:07 PM PDT 23
Finished Oct 29 12:30:11 PM PDT 23
Peak memory 200908 kb
Host smart-501557f4-f294-4c40-ad40-b5a5e3b445cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103851676010661558360858192030322039138876297055751256766963945279281508766512 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.103851676010661558360858192030322039138876297055751256766963945279281508766512
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.112546360317039037339058630734899759343340659121585492873204607308431975599049
Short name T217
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Oct 29 12:29:26 PM PDT 23
Finished Oct 29 12:29:32 PM PDT 23
Peak memory 201008 kb
Host smart-947ce2fd-10ca-4757-ab38-689cb8b0d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112546360317039037339058630734899759343340659121585492873204607308431975599049 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.112546360317039037339058630734899759343340659121585492873204607308431975599049
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.52709748609840759315021898312018290791219497927322247992591196081198865609127
Short name T623
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 29 12:29:26 PM PDT 23
Finished Oct 29 12:29:31 PM PDT 23
Peak memory 200956 kb
Host smart-6f60111b-1f15-4791-aa09-820c4d26a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52709748609840759315021898312018290791219497927322247992591196081198865609127 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_smoke.52709748609840759315021898312018290791219497927322247992591196081198865609127
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.53548656332594398738164043518406768929063704162960057514655449113307279440477
Short name T418
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.81 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:31:58 PM PDT 23
Peak memory 201308 kb
Host smart-d3d5aa42-866d-4858-955f-7ddeb826dbb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53548656332594398738164043518406768929063704162960057514655449113307279440477 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.53548656332594398738164043518406768929063704162960057514655449113307279440477
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.54767700357525388607028789375794969181201117961340531673303982968117232105784
Short name T628
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:29:59 PM PDT 23
Peak memory 199700 kb
Host smart-9e4f5093-9826-4868-9af2-9f09b0c6c8c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54767700357525388607028789375794969181201117961340531673303982968117232105784 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.547677003575253886070287893757949691812011179613405316733039
82968117232105784
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.4007329486526847637129402179029512336839564843617367267123253282531329001060
Short name T213
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:45 PM PDT 23
Peak memory 201004 kb
Host smart-6e98bf6a-da19-419f-899a-7af22a37a348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007329486526847637129402179029512336839564843617367267123253282531329001060 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.4007329486526847637129402179029512336839564843617367267123253282531329001060
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.22739730466583357555480478463578545939444934970619390830748401787040649633960
Short name T667
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 29 12:29:45 PM PDT 23
Finished Oct 29 12:29:51 PM PDT 23
Peak memory 201088 kb
Host smart-37683108-68e3-43b1-985a-28f4829d89a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22739730466583357555480478463578545939444934970619390830748401787040649633960 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.22739730466583357555480478463578545939444934970619390830748401787040649633960
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.10982484432588153404783645324546090411672901200852854011593786324992977671398
Short name T273
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.65 seconds
Started Oct 29 12:29:38 PM PDT 23
Finished Oct 29 12:29:46 PM PDT 23
Peak memory 201076 kb
Host smart-97f30c03-51c0-4d5f-813c-45609fb07565
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982484432588153404783645324546090411672901200852854011593786324992977671398 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.109824844325881534047836453245460904116729012008528540115937
86324992977671398
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.16926137487091566579940704409390559209847218373224159702001982120955027124333
Short name T21
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 29 12:29:39 PM PDT 23
Finished Oct 29 12:29:46 PM PDT 23
Peak memory 201020 kb
Host smart-08ddec07-6338-45bd-943b-dd77ba6012b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16926137487091566579940704409390559209847218373224159702001982120955027124333 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.1692613748709156657994070440939055920984721837322415970200198212
0955027124333
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.71923138413250081550938477239478676520935815453064052441941159216746348438762
Short name T497
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:46 PM PDT 23
Peak memory 200976 kb
Host smart-91fe293c-62e3-4ac7-a07a-a398fe79d4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71923138413250081550938477239478676520935815453064052441941159216746348438762 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.71923138413250081550938477239478676520935815453064052441941159216746348438762
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.49081613681935499491358179350729098251116130628600470303779391970277132766216
Short name T178
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 29 12:30:06 PM PDT 23
Finished Oct 29 12:30:12 PM PDT 23
Peak memory 201048 kb
Host smart-8d44fa26-1545-4dbc-a05a-da8645c2134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49081613681935499491358179350729098251116130628600470303779391970277132766216 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.49081613681935499491358179350729098251116130628600470303779391970277132766216
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.40156679189577318691838058640154463263714765418771760439099139481278679673640
Short name T456
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 29 12:29:45 PM PDT 23
Finished Oct 29 12:29:50 PM PDT 23
Peak memory 200992 kb
Host smart-e873ef8c-fa50-47a7-bbfa-97a4b7a53f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40156679189577318691838058640154463263714765418771760439099139481278679673640 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.40156679189577318691838058640154463263714765418771760439099139481278679673640
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.77745861293671763546319305446299825701695387028808243181010760567656235894460
Short name T491
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.81 seconds
Started Oct 29 12:29:38 PM PDT 23
Finished Oct 29 12:29:43 PM PDT 23
Peak memory 200992 kb
Host smart-eb91573d-f8ca-4565-a0a2-42455486e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77745861293671763546319305446299825701695387028808243181010760567656235894460 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.77745861293671763546319305446299825701695387028808243181010760567656235894460
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.40780058701097789232137616345040181867899630195966985125826959286867847628265
Short name T331
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 29 12:29:38 PM PDT 23
Finished Oct 29 12:29:42 PM PDT 23
Peak memory 200944 kb
Host smart-46490185-4e83-4feb-b68b-625182a8f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40780058701097789232137616345040181867899630195966985125826959286867847628265 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_smoke.40780058701097789232137616345040181867899630195966985125826959286867847628265
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.111940179497105447728656508383945290512384366106790480997862352588257809668841
Short name T614
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.62 seconds
Started Oct 29 12:29:37 PM PDT 23
Finished Oct 29 12:31:53 PM PDT 23
Peak memory 201320 kb
Host smart-1cf1c2e5-e984-4fed-b73f-fd32efc514bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111940179497105447728656508383945290512384366106790480997862352588257809668841 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.111940179497105447728656508383945290512384366106790480997862352588257809668841
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.33260642486738737437660007105855386151300203889096157816597345082335747553316
Short name T637
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.92 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:46 PM PDT 23
Peak memory 201016 kb
Host smart-0dbb0c14-b70d-4383-80e2-02405ed54d04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33260642486738737437660007105855386151300203889096157816597345082335747553316 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.332606424867387374376600071058553861513002038890961578165973
45082335747553316
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.7833438339374987785164408246579604013858860442085583361991514537899811242406
Short name T120
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 29 12:29:48 PM PDT 23
Finished Oct 29 12:29:53 PM PDT 23
Peak memory 201152 kb
Host smart-df64ecec-8d5a-4ee5-8808-22e24cb5881f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7833438339374987785164408246579604013858860442085583361991514537899811242406 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.7833438339374987785164408246579604013858860442085583361991514537899811242406
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.90910613687267018400911259578049529914473654417379538818609591869244548833624
Short name T315
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.56 seconds
Started Oct 29 12:29:44 PM PDT 23
Finished Oct 29 12:29:51 PM PDT 23
Peak memory 201108 kb
Host smart-c05baa23-fafe-4ed7-8212-c1f0eb466062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90910613687267018400911259578049529914473654417379538818609591869244548833624 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.90910613687267018400911259578049529914473654417379538818609591869244548833624
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.98024462869616495981016019336385010122176223111273329388889317143117724746806
Short name T594
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.82 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:32:59 PM PDT 23
Peak memory 201032 kb
Host smart-67bc4922-103a-44cd-b044-509778a015d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98024462869616495981016019336385010122176223111273329388889317143117724746806 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.98024462869616495981016019336385010122176223111273329388889317
143117724746806
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.94550660317487566861626363861648741726642239959969522620167317798387112257843
Short name T541
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 29 12:29:36 PM PDT 23
Finished Oct 29 12:29:45 PM PDT 23
Peak memory 201144 kb
Host smart-f6a119fb-c16c-4c65-be0a-41b9ba4b289a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94550660317487566861626363861648741726642239959969522620167317798387112257843 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.945506603174875668616263638616487417266422399599695226201673
17798387112257843
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.84793120324517781910204820008145773219422305332092976924609478920376769953676
Short name T514
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.7 seconds
Started Oct 29 12:29:48 PM PDT 23
Finished Oct 29 12:29:56 PM PDT 23
Peak memory 201004 kb
Host smart-9c023070-aaf9-4924-91c6-e2037b6c444e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84793120324517781910204820008145773219422305332092976924609478920376769953676 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.8479312032451778191020482000814577321942230533209297692460947892
0376769953676
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.26376655156181364026008453434685514255298151558955660072590713151177713949241
Short name T490
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 29 12:29:38 PM PDT 23
Finished Oct 29 12:29:44 PM PDT 23
Peak memory 201016 kb
Host smart-90236a87-172e-4dfc-8006-37a6be06da1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26376655156181364026008453434685514255298151558955660072590713151177713949241 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.26376655156181364026008453434685514255298151558955660072590713151177713949241
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.60544370305064062940734352553183737468912726853061214122152308140944587325618
Short name T193
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:47 PM PDT 23
Peak memory 201056 kb
Host smart-26ccc8e3-02a6-4d1e-ae3f-b155cf48e9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60544370305064062940734352553183737468912726853061214122152308140944587325618 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.60544370305064062940734352553183737468912726853061214122152308140944587325618
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.79705076524493257625542152776035315803523063837133290935911562301764447919360
Short name T365
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.88 seconds
Started Oct 29 12:29:37 PM PDT 23
Finished Oct 29 12:29:42 PM PDT 23
Peak memory 200984 kb
Host smart-e8d8eeba-0224-472b-85f6-8a8270e8353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79705076524493257625542152776035315803523063837133290935911562301764447919360 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.79705076524493257625542152776035315803523063837133290935911562301764447919360
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.81222846760892527321168156834253860124939180918490684577564164234748129331541
Short name T356
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 29 12:29:40 PM PDT 23
Finished Oct 29 12:29:45 PM PDT 23
Peak memory 200976 kb
Host smart-843a1e42-585f-40b1-9e10-cee35e0b1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81222846760892527321168156834253860124939180918490684577564164234748129331541 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.81222846760892527321168156834253860124939180918490684577564164234748129331541
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.103633272843094977162135621037686824756407710116310032494082161742799856300060
Short name T160
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.95 seconds
Started Oct 29 12:29:41 PM PDT 23
Finished Oct 29 12:29:45 PM PDT 23
Peak memory 200916 kb
Host smart-ba05f105-c808-48ce-a59b-3391ba35f6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103633272843094977162135621037686824756407710116310032494082161742799856300060 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.sysrst_ctrl_smoke.103633272843094977162135621037686824756407710116310032494082161742799856300060
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.15458618050165499472137277299993413557595013270850288787474902941782192115649
Short name T605
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.23 seconds
Started Oct 29 12:29:45 PM PDT 23
Finished Oct 29 12:32:02 PM PDT 23
Peak memory 201304 kb
Host smart-78a74109-eee7-4a99-86bf-5e8be0f83adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15458618050165499472137277299993413557595013270850288787474902941782192115649 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.15458618050165499472137277299993413557595013270850288787474902941782192115649
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.82386586493545077365182673092228176880486282468523288901536824378908458995048
Short name T489
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Oct 29 12:29:44 PM PDT 23
Finished Oct 29 12:29:49 PM PDT 23
Peak memory 201016 kb
Host smart-bce6dcb7-aedb-46b3-a31b-2dbbed668741
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82386586493545077365182673092228176880486282468523288901536824378908458995048 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.823865864935450773651826730922281768804862824685232889015368
24378908458995048
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.74503326663220159430581614303947346902990431923891770257082405206614969881702
Short name T562
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 201016 kb
Host smart-530f0231-6bd2-495a-a0aa-f1ea27a262ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74503326663220159430581614303947346902990431923891770257082405206614969881702 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.74503326663220159430581614303947346902990431923891770257082405206614969881702
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.73869572417872116899059662025011485403339423819568052388834239536639464743469
Short name T441
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Oct 29 12:28:00 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 201036 kb
Host smart-64247460-c4dc-4335-ae2d-b8635f2751b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73869572417872116899059662025011485403339423819568052388834239536639464743469 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.73869572417872116899059662025011485403339423819568052388834239536639464743469
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.8571810625771991518815057127850873103976012390248412422099540526695734107901
Short name T318
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.72 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:31:12 PM PDT 23
Peak memory 201248 kb
Host smart-282e3f3e-b9eb-40b3-8d7b-bec389d4ae83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8571810625771991518815057127850873103976012390248412422099540526695734107901 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.8571810625771991518815057127850873103976012390248412422099540526695734107901
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.63754815049462982556616386347923520011562282323890988424721415751870507750908
Short name T515
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.31 seconds
Started Oct 29 12:28:43 PM PDT 23
Finished Oct 29 12:28:48 PM PDT 23
Peak memory 200208 kb
Host smart-95261224-6e0a-4d79-b84b-bf282253cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63754815049462982556616386347923520011562282323890988424721415751870507750908 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.63754815049462982556616386347923520011562282323890988424721415751870507750908
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.112246071808755127069678384423228354538306046926492469094666576129647425901429
Short name T94
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.47 seconds
Started Oct 29 12:28:15 PM PDT 23
Finished Oct 29 12:28:19 PM PDT 23
Peak memory 200980 kb
Host smart-4c4e053a-1fd9-418b-abf7-4f205355bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112246071808755127069678384423228354538306046926492469094666576129647425901429 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1122460718087551270696783844232283545383060469264924
69094666576129647425901429
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.109036827401447330852771215935228327527460426337619373727523053030605430636043
Short name T638
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.87 seconds
Started Oct 29 12:27:55 PM PDT 23
Finished Oct 29 12:28:05 PM PDT 23
Peak memory 201024 kb
Host smart-93dc86dc-6537-4973-9c51-a4fb381d7c07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109036827401447330852771215935228327527460426337619373727523053030605430636043 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.109036827401447330852771215935228327527460426337619373727523
053030605430636043
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.34169215612584550928683256006134259107295704916448063677113804763540064432925
Short name T261
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.41 seconds
Started Oct 29 12:27:53 PM PDT 23
Finished Oct 29 12:28:03 PM PDT 23
Peak memory 201052 kb
Host smart-6d345948-919e-4199-8670-7e026d57bc8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34169215612584550928683256006134259107295704916448063677113804763540064432925 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.34169215612584550928683256006134259107295704916448063677113804763540064432925
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.51565744380212522468790620857903075300632188360906841709821783852031227628360
Short name T522
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 200984 kb
Host smart-d7232ebf-ae14-42f7-8039-d47d80a1d943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51565744380212522468790620857903075300632188360906841709821783852031227628360 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.51565744380212522468790620857903075300632188360906841709821783852031227628360
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.99312581971408424656338499882481761482567060718133031748692187286495788375516
Short name T498
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.89 seconds
Started Oct 29 12:27:35 PM PDT 23
Finished Oct 29 12:27:41 PM PDT 23
Peak memory 201064 kb
Host smart-26963075-048a-4dc0-990c-6881926dcbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99312581971408424656338499882481761482567060718133031748692187286495788375516 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.99312581971408424656338499882481761482567060718133031748692187286495788375516
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.18219810203489020008672512018305908253195662377422460117563435437776011783445
Short name T124
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.81 seconds
Started Oct 29 12:28:44 PM PDT 23
Finished Oct 29 12:28:48 PM PDT 23
Peak memory 200740 kb
Host smart-80618f78-12cc-444a-8afb-e252e5e6fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18219810203489020008672512018305908253195662377422460117563435437776011783445 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.18219810203489020008672512018305908253195662377422460117563435437776011783445
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.108566732215252029613644481187891540120404377406039636986529477790548903241716
Short name T281
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 201008 kb
Host smart-f2f53f57-12f8-4be8-8bb3-bbca05064ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108566732215252029613644481187891540120404377406039636986529477790548903241716 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.108566732215252029613644481187891540120404377406039636986529477790548903241716
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.42834782996491474666552591230875437080942439414213117565203791331574370546352
Short name T142
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.72 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:29:10 PM PDT 23
Peak memory 221360 kb
Host smart-0d57efef-76d9-4d85-ab4a-6f9cd94b6113
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834782996491474666552591230875437080942439414213117565203791331574370546352 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.42834782996491474666552591230875437080942439414213117565203791331574370546352
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.7637416279336774568775880481789929559316347019088969299335504185360739615348
Short name T157
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Oct 29 12:27:49 PM PDT 23
Finished Oct 29 12:27:54 PM PDT 23
Peak memory 200980 kb
Host smart-f6e1a6c3-449f-4f6f-a785-1d2f6fb4d70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7637416279336774568775880481789929559316347019088969299335504185360739615348 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sysrst_ctrl_smoke.7637416279336774568775880481789929559316347019088969299335504185360739615348
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.23243255370896280907401725985444556627680979042204553898546067130150372151985
Short name T255
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.08 seconds
Started Oct 29 12:27:49 PM PDT 23
Finished Oct 29 12:30:06 PM PDT 23
Peak memory 201052 kb
Host smart-3c6cc1d1-f35b-4e3e-9fe7-2a038706363c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23243255370896280907401725985444556627680979042204553898546067130150372151985 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.23243255370896280907401725985444556627680979042204553898546067130150372151985
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.5293466100603834871341950123859802506136479120209451204183507940379993945862
Short name T286
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.89 seconds
Started Oct 29 12:27:59 PM PDT 23
Finished Oct 29 12:28:05 PM PDT 23
Peak memory 201312 kb
Host smart-b8a88c01-6d78-486a-9aed-ec4310fcd763
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5293466100603834871341950123859802506136479120209451204183507940379993945862 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.52934661006038348713419501238598025061364791202094512041835079
40379993945862
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.29895634371567015348975413914345690388485937845413944861082104351580231961074
Short name T156
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 201012 kb
Host smart-f8694663-7c3d-4284-a5a9-8930b905598e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29895634371567015348975413914345690388485937845413944861082104351580231961074 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.29895634371567015348975413914345690388485937845413944861082104351580231961074
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.12837085758978632297974902049386873655461984129589312518521744358564353850119
Short name T396
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Oct 29 12:29:46 PM PDT 23
Finished Oct 29 12:29:55 PM PDT 23
Peak memory 201044 kb
Host smart-3ed95962-9296-40e2-a65a-a71a122d6e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12837085758978632297974902049386873655461984129589312518521744358564353850119 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.12837085758978632297974902049386873655461984129589312518521744358564353850119
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.50414807290618110478935747716748446668324816012126402962190112585268028952979
Short name T26
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.91 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:32:58 PM PDT 23
Peak memory 201364 kb
Host smart-987b8867-887b-438d-ba6b-ac6c0b7d1560
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50414807290618110478935747716748446668324816012126402962190112585268028952979 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.50414807290618110478935747716748446668324816012126402962190112
585268028952979
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.10145922504653963914880524008548412310406052144835951065795656411434321948862
Short name T337
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.56 seconds
Started Oct 29 12:29:44 PM PDT 23
Finished Oct 29 12:29:52 PM PDT 23
Peak memory 201060 kb
Host smart-b40b8fb1-cbdd-454b-97b2-65751465dc68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145922504653963914880524008548412310406052144835951065795656411434321948862 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.101459225046539639148805240085484123104060521448359510657956
56411434321948862
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.4213588787661412923095510420313834100723379553173562550630043130282926671095
Short name T345
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.35 seconds
Started Oct 29 12:29:48 PM PDT 23
Finished Oct 29 12:29:56 PM PDT 23
Peak memory 201144 kb
Host smart-7f6ee51a-5765-4b0e-bbef-197511282515
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213588787661412923095510420313834100723379553173562550630043130282926671095 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.4213588787661412923095510420313834100723379553173562550630043130282926671095
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.49759494329554234103514354662763468596180942207724836018132048833829179320519
Short name T596
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.74 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 200984 kb
Host smart-c95b76d7-89ea-4681-b369-a4631c40ad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49759494329554234103514354662763468596180942207724836018132048833829179320519 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.49759494329554234103514354662763468596180942207724836018132048833829179320519
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.67797333371482212293955742708198007599771055802377363499800602784258485147499
Short name T454
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 29 12:29:53 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 201016 kb
Host smart-3477e5f5-aa17-403c-8496-2231b27d6c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67797333371482212293955742708198007599771055802377363499800602784258485147499 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.67797333371482212293955742708198007599771055802377363499800602784258485147499
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.83525931747955668950862833165641631516399063977270941619657796113525886134917
Short name T362
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Oct 29 12:29:47 PM PDT 23
Finished Oct 29 12:29:53 PM PDT 23
Peak memory 201128 kb
Host smart-5ec0a625-3ba3-4177-a647-72b80a357c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83525931747955668950862833165641631516399063977270941619657796113525886134917 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.83525931747955668950862833165641631516399063977270941619657796113525886134917
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.28216087508144230223415176507952570642045238042010243154363306417897343731979
Short name T540
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 200980 kb
Host smart-38515f5b-f1ba-429d-9e51-4d8d35e7acee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28216087508144230223415176507952570642045238042010243154363306417897343731979 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.28216087508144230223415176507952570642045238042010243154363306417897343731979
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.2727975008353291982998924510422670616073388576179163677340102698377219167396
Short name T574
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 29 12:29:48 PM PDT 23
Finished Oct 29 12:29:53 PM PDT 23
Peak memory 201092 kb
Host smart-4e03bed1-6206-4fa2-a04d-95938ab101e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727975008353291982998924510422670616073388576179163677340102698377219167396 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sysrst_ctrl_smoke.2727975008353291982998924510422670616073388576179163677340102698377219167396
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.29325212164900555788149132758132232431268477126137234825660479471661262995318
Short name T494
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.29 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:32:09 PM PDT 23
Peak memory 201296 kb
Host smart-41ddc025-c428-4710-9e3e-7eb37e769b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29325212164900555788149132758132232431268477126137234825660479471661262995318 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.29325212164900555788149132758132232431268477126137234825660479471661262995318
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.29695035405835490826884995068536155214036192706880797519423586187565859067959
Short name T399
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 200988 kb
Host smart-a997138d-bf87-4c9e-8776-00e8d3e859c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29695035405835490826884995068536155214036192706880797519423586187565859067959 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.296950354058354908268849950685361552140361927068807975194235
86187565859067959
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.5790392177924089723862831854330446732995248103854238776682668209567292133117
Short name T561
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Oct 29 12:29:49 PM PDT 23
Finished Oct 29 12:29:53 PM PDT 23
Peak memory 201004 kb
Host smart-eda7c898-7a00-4d6f-9dda-8cb70d2afb99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5790392177924089723862831854330446732995248103854238776682668209567292133117 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.5790392177924089723862831854330446732995248103854238776682668209567292133117
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.114303559853509274534507527413617836805343859727704136058600726710010409462241
Short name T276
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.62 seconds
Started Oct 29 12:29:48 PM PDT 23
Finished Oct 29 12:29:55 PM PDT 23
Peak memory 201088 kb
Host smart-7a47153c-2bcd-47d1-ab4c-7a7c63d075bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114303559853509274534507527413617836805343859727704136058600726710010409462241 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.114303559853509274534507527413617836805343859727704136058600726710010409462241
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.58770410212717530239870436871608680191537487935405729388790480622826491104208
Short name T173
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.04 seconds
Started Oct 29 12:29:58 PM PDT 23
Finished Oct 29 12:33:03 PM PDT 23
Peak memory 201244 kb
Host smart-77ea06ed-8c84-4951-9e9f-eb6eb9f3ad08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58770410212717530239870436871608680191537487935405729388790480622826491104208 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.58770410212717530239870436871608680191537487935405729388790480
622826491104208
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.9706971503818475584129468238782252481616548426409540971513501678969352836156
Short name T184
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 29 12:29:47 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 201028 kb
Host smart-f161d0ac-5d3a-4ce0-a071-66c1303051eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9706971503818475584129468238782252481616548426409540971513501678969352836156 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.9706971503818475584129468238782252481616548426409540971513501
678969352836156
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.31440112455069666472623585047157504276446536131337576798883258419259764498020
Short name T665
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:04 PM PDT 23
Peak memory 198460 kb
Host smart-8c6cef66-135b-44ab-bb9c-f4641c2f6122
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440112455069666472623585047157504276446536131337576798883258419259764498020 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.3144011245506966647262358504715750427644653613133757679888325841
9259764498020
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.20384455264680261258464107463487576913617966436695552211165433272815175368944
Short name T310
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.83 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:02 PM PDT 23
Peak memory 198628 kb
Host smart-cc074163-9f85-4ce8-ab2e-a63f638d406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20384455264680261258464107463487576913617966436695552211165433272815175368944 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.20384455264680261258464107463487576913617966436695552211165433272815175368944
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.53827034771326420903892473426045787015745491547807964334102374297872794514896
Short name T572
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 201016 kb
Host smart-676f5ef6-1c5d-45fa-b2e8-d71f5b55c2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53827034771326420903892473426045787015745491547807964334102374297872794514896 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.53827034771326420903892473426045787015745491547807964334102374297872794514896
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.62084929937775607615219116644897271874295275361229808454561261648629111225125
Short name T170
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:00 PM PDT 23
Peak memory 200844 kb
Host smart-4e7367a0-1df7-4da8-9123-e52459c07493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62084929937775607615219116644897271874295275361229808454561261648629111225125 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.62084929937775607615219116644897271874295275361229808454561261648629111225125
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.91410241368688552233296762768056925406229443025138522751052075552594189152333
Short name T370
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 201000 kb
Host smart-b5dfce1a-98b5-4b4d-becf-418cd570d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91410241368688552233296762768056925406229443025138522751052075552594189152333 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.91410241368688552233296762768056925406229443025138522751052075552594189152333
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.61646218405027127172039152786548179334739234104297103841903337513757107658714
Short name T401
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 29 12:29:47 PM PDT 23
Finished Oct 29 12:29:53 PM PDT 23
Peak memory 200956 kb
Host smart-3907a35e-f0ae-4629-a571-43bcc17e3d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61646218405027127172039152786548179334739234104297103841903337513757107658714 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_smoke.61646218405027127172039152786548179334739234104297103841903337513757107658714
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.115277263582340863010786458276494049498872275074046084628076753573133738829961
Short name T210
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.41 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:32:09 PM PDT 23
Peak memory 201248 kb
Host smart-b3094a9e-8634-4e50-87ed-f6969b716189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115277263582340863010786458276494049498872275074046084628076753573133738829961 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.115277263582340863010786458276494049498872275074046084628076753573133738829961
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.53130654496165732918981008429922124828403014671543415710238290340329297602163
Short name T330
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 29 12:29:50 PM PDT 23
Finished Oct 29 12:29:56 PM PDT 23
Peak memory 200980 kb
Host smart-1a2843c3-987a-4bee-b9e4-6e035dea8af6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53130654496165732918981008429922124828403014671543415710238290340329297602163 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.531306544961657329189810084299221248284030146715434157102382
90340329297602163
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.97944468346544324472328367718305841594445962462270241809529995840374388946096
Short name T620
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.74 seconds
Started Oct 29 12:29:55 PM PDT 23
Finished Oct 29 12:29:59 PM PDT 23
Peak memory 201004 kb
Host smart-e73ed511-0ea3-4b71-a691-a9e935004c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97944468346544324472328367718305841594445962462270241809529995840374388946096 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.97944468346544324472328367718305841594445962462270241809529995840374388946096
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.102663436170025282432669833742671518148900609266265785438296090693418144451989
Short name T285
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.62 seconds
Started Oct 29 12:29:55 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 201072 kb
Host smart-5efcb02b-a7ed-42dd-a213-ccd189192a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102663436170025282432669833742671518148900609266265785438296090693418144451989 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.102663436170025282432669833742671518148900609266265785438296090693418144451989
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.115769366834169972436666056435857577524298962695173101110267888910858321611484
Short name T616
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.1 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:32:58 PM PDT 23
Peak memory 201276 kb
Host smart-655b8b4c-4c82-41cf-897a-94506e13e979
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115769366834169972436666056435857577524298962695173101110267888910858321611484 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.1157693668341699724366660564358575775242989626951731011102678
88910858321611484
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.50457958473051593188196580695505767828434792230350622502894579850749160856037
Short name T653
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.61 seconds
Started Oct 29 12:29:53 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 201028 kb
Host smart-8a195a0e-7897-45b7-bee3-0ae22f4d21ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50457958473051593188196580695505767828434792230350622502894579850749160856037 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.504579584730515931881965806955057678284347922303506225028945
79850749160856037
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.100630494150462742880076956030092621953494372010897143075752395759576545141548
Short name T601
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.39 seconds
Started Oct 29 12:29:53 PM PDT 23
Finished Oct 29 12:30:00 PM PDT 23
Peak memory 201012 kb
Host smart-afe2dcfe-2702-44b9-a67c-e8c0c140e388
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100630494150462742880076956030092621953494372010897143075752395759576545141548 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.100630494150462742880076956030092621953494372010897143075752395
759576545141548
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.83846439689720303210057386581690776581128920606422859491398663674406676066743
Short name T407
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 201012 kb
Host smart-70c4765e-59c7-4873-a900-3d6bd73ecab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83846439689720303210057386581690776581128920606422859491398663674406676066743 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.83846439689720303210057386581690776581128920606422859491398663674406676066743
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.13327911842367928547046772067789258429583022882283180377273838154002607940320
Short name T438
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 201332 kb
Host smart-3f3ee306-a159-499b-b050-a65f9f9ce973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13327911842367928547046772067789258429583022882283180377273838154002607940320 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.13327911842367928547046772067789258429583022882283180377273838154002607940320
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.91261980105119248736280379310329706610018803949535518144281418148655691500745
Short name T506
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 201008 kb
Host smart-91008dbd-2bc9-434c-b3df-9800c0d3cb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91261980105119248736280379310329706610018803949535518144281418148655691500745 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.91261980105119248736280379310329706610018803949535518144281418148655691500745
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.144899618004156787376897157431634005417364200544503824055744598660045475845
Short name T186
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.65 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 201148 kb
Host smart-24d8586d-1e15-4260-9e55-bfb1151e74f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144899618004156787376897157431634005417364200544503824055744598660045475845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.144899618004156787376897157431634005417364200544503824055744598660045475845
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.54756418700401103264226596392502931709658083258248070682878489460989595750011
Short name T353
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 201032 kb
Host smart-0b760c51-637a-4e1e-aaaf-8b7e3c643787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54756418700401103264226596392502931709658083258248070682878489460989595750011 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_smoke.54756418700401103264226596392502931709658083258248070682878489460989595750011
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.7487323803594687804926517066251119756197361977139123040278505057580179273502
Short name T354
Test name
Test status
Simulation time 87228974549 ps
CPU time 138.04 seconds
Started Oct 29 12:30:00 PM PDT 23
Finished Oct 29 12:32:18 PM PDT 23
Peak memory 201304 kb
Host smart-6a3bd192-4b71-4171-b961-9dcdd581933a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7487323803594687804926517066251119756197361977139123040278505057580179273502 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.7487323803594687804926517066251119756197361977139123040278505057580179273502
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.107990395676666315893059965213893874322427407050560020036996646771237124886317
Short name T369
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:29:59 PM PDT 23
Peak memory 200980 kb
Host smart-4c7338bd-c9f9-438c-a612-99bf7a1329de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107990395676666315893059965213893874322427407050560020036996646771237124886317 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.10799039567666631589305996521389387432242740705056002003699
6646771237124886317
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.103837114389417174621059927561945573478337600106489181404091686792033841728746
Short name T212
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 29 12:29:59 PM PDT 23
Finished Oct 29 12:30:03 PM PDT 23
Peak memory 201016 kb
Host smart-b46332ce-6e25-4edd-a143-fcbb0eaea656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103837114389417174621059927561945573478337600106489181404091686792033841728746 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.103837114389417174621059927561945573478337600106489181404091686792033841728746
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.26148840207907767036759392881734412657571020161782094708644374327563332225095
Short name T604
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.55 seconds
Started Oct 29 12:30:03 PM PDT 23
Finished Oct 29 12:30:09 PM PDT 23
Peak memory 201048 kb
Host smart-84cce6b5-75d1-441b-a61b-e8a87bda562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26148840207907767036759392881734412657571020161782094708644374327563332225095 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.26148840207907767036759392881734412657571020161782094708644374327563332225095
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.107520105009715377837807440367560467224878657832273175626287992348284676161213
Short name T31
Test name
Test status
Simulation time 118289458206 ps
CPU time 186.13 seconds
Started Oct 29 12:30:00 PM PDT 23
Finished Oct 29 12:33:06 PM PDT 23
Peak memory 201240 kb
Host smart-20a672e0-2c1f-4c93-b4d2-3fdbcc3fe531
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107520105009715377837807440367560467224878657832273175626287992348284676161213 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.1075201050097153778378074403675604672248786578322731756262879
92348284676161213
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.30834984629946701371620721456300204022358332044057308490165748937339319894395
Short name T588
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.52 seconds
Started Oct 29 12:30:04 PM PDT 23
Finished Oct 29 12:30:12 PM PDT 23
Peak memory 201032 kb
Host smart-083f7f09-3346-41a7-90cc-0ded6750fb8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834984629946701371620721456300204022358332044057308490165748937339319894395 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.308349846299467013716207214563002040223583320440573084901657
48937339319894395
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.71271063183228826746531786730111457943400122510286380442132727653908905337752
Short name T451
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Oct 29 12:29:59 PM PDT 23
Finished Oct 29 12:30:06 PM PDT 23
Peak memory 200992 kb
Host smart-16527251-1351-4f3a-8058-9cb18ae48d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271063183228826746531786730111457943400122510286380442132727653908905337752 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.7127106318322882674653178673011145794340012251028638044213272765
3908905337752
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.92395177613608856109575740324363483663336561670057577140368366426313543832209
Short name T298
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 29 12:30:03 PM PDT 23
Finished Oct 29 12:30:09 PM PDT 23
Peak memory 200996 kb
Host smart-9cc1b386-8b25-4c71-b74d-5d43d995ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92395177613608856109575740324363483663336561670057577140368366426313543832209 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.92395177613608856109575740324363483663336561670057577140368366426313543832209
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.57286550675293284853677156992009924676677769389845058639874134901791689201977
Short name T658
Test name
Test status
Simulation time 2470384766 ps
CPU time 5 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 201024 kb
Host smart-eb9dd18d-30c0-49af-b3ec-c0179ae8056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57286550675293284853677156992009924676677769389845058639874134901791689201977 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.57286550675293284853677156992009924676677769389845058639874134901791689201977
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.103043025714300985047161775471584707099294830870592918086308850789053933492785
Short name T153
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 29 12:30:03 PM PDT 23
Finished Oct 29 12:30:08 PM PDT 23
Peak memory 200952 kb
Host smart-2ee489f9-389f-4033-b340-2f08b8f662df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103043025714300985047161775471584707099294830870592918086308850789053933492785 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.103043025714300985047161775471584707099294830870592918086308850789053933492785
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.31569376376939470884163059044666779519615814299040937930940971696217488820647
Short name T209
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 29 12:29:59 PM PDT 23
Finished Oct 29 12:30:04 PM PDT 23
Peak memory 201008 kb
Host smart-c6cf8701-9b3c-449c-9c3e-73daee3d8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31569376376939470884163059044666779519615814299040937930940971696217488820647 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.31569376376939470884163059044666779519615814299040937930940971696217488820647
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.29952202476644501598546030925443618608465881055874006100094133494178124698842
Short name T260
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 29 12:29:55 PM PDT 23
Finished Oct 29 12:29:59 PM PDT 23
Peak memory 200944 kb
Host smart-3037073c-11ca-4899-9808-7f3a414620f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29952202476644501598546030925443618608465881055874006100094133494178124698842 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_smoke.29952202476644501598546030925443618608465881055874006100094133494178124698842
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.89912756139068522511089773130570401397938069937696065871165892630432337498941
Short name T218
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.26 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:32:12 PM PDT 23
Peak memory 201272 kb
Host smart-c07e7354-d8ba-4ca2-95a7-048d5f2f6f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89912756139068522511089773130570401397938069937696065871165892630432337498941 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.89912756139068522511089773130570401397938069937696065871165892630432337498941
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.12085796009409738560141632129384031033107865159807468894999920501812361932797
Short name T46
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.9 seconds
Started Oct 29 12:29:57 PM PDT 23
Finished Oct 29 12:30:03 PM PDT 23
Peak memory 200992 kb
Host smart-404733f3-1c79-40b5-a543-abb6bea3303a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085796009409738560141632129384031033107865159807468894999920501812361932797 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.120857960094097385601416321293840310331078651598074688949999
20501812361932797
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.88919775931202015556460992982046532674086190198252391142076803902647962620905
Short name T488
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 29 12:30:04 PM PDT 23
Finished Oct 29 12:30:08 PM PDT 23
Peak memory 201024 kb
Host smart-20bf2030-1da2-41c9-958c-4f49ed9cc99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88919775931202015556460992982046532674086190198252391142076803902647962620905 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.88919775931202015556460992982046532674086190198252391142076803902647962620905
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.83324919844171759860794307778795181855161667917985712631656536813045656216379
Short name T612
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:30:00 PM PDT 23
Peak memory 201056 kb
Host smart-fbe5c54c-127e-4e56-b947-7cf00df5e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83324919844171759860794307778795181855161667917985712631656536813045656216379 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.83324919844171759860794307778795181855161667917985712631656536813045656216379
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.42623555627882396527352730819640728120964665764001662712734945699296154299602
Short name T464
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.58 seconds
Started Oct 29 12:30:04 PM PDT 23
Finished Oct 29 12:33:10 PM PDT 23
Peak memory 201248 kb
Host smart-10520f58-5e87-4448-9998-3025b6d56920
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42623555627882396527352730819640728120964665764001662712734945699296154299602 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.42623555627882396527352730819640728120964665764001662712734945
699296154299602
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.85511353451525833695957548907255131448463197180894108162168793354063663691537
Short name T180
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 29 12:29:53 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 201484 kb
Host smart-9951a068-2f57-44fb-ab07-ce1f73cf1a96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85511353451525833695957548907255131448463197180894108162168793354063663691537 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.855113534515258336959575489072551314484631971808941081621687
93354063663691537
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.46711206634304067088156931640176426379471906224559179886339052790907019049476
Short name T457
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 29 12:30:03 PM PDT 23
Finished Oct 29 12:30:10 PM PDT 23
Peak memory 201004 kb
Host smart-9fe84438-a9db-4863-9170-867abed15f6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46711206634304067088156931640176426379471906224559179886339052790907019049476 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.4671120663430406708815693164017642637947190622455917988633905279
0907019049476
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3066907902048660972583840800843164348097659697561874677625115990546744536094
Short name T437
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:02 PM PDT 23
Peak memory 201000 kb
Host smart-a1bd9b38-6455-4bc9-8593-ea4dc5bfb5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066907902048660972583840800843164348097659697561874677625115990546744536094 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3066907902048660972583840800843164348097659697561874677625115990546744536094
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.28964835046520850375424376443086627471125013297941166532207091537139360234338
Short name T269
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.85 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:58 PM PDT 23
Peak memory 201004 kb
Host smart-2d59b478-b656-4b4e-81fe-8df6c5fba1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28964835046520850375424376443086627471125013297941166532207091537139360234338 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.28964835046520850375424376443086627471125013297941166532207091537139360234338
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.109846712012000915780897075185548703140690308020320415168047570677613754376918
Short name T420
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 29 12:29:59 PM PDT 23
Finished Oct 29 12:30:03 PM PDT 23
Peak memory 200976 kb
Host smart-6f07e8a2-4d48-4836-ae9c-3ab5f36c743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109846712012000915780897075185548703140690308020320415168047570677613754376918 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.109846712012000915780897075185548703140690308020320415168047570677613754376918
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.95058820476905193879620374676522890539817126922316451905317865021232804624625
Short name T112
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.71 seconds
Started Oct 29 12:29:56 PM PDT 23
Finished Oct 29 12:30:01 PM PDT 23
Peak memory 201008 kb
Host smart-587efb0d-377d-454e-857d-032c47479176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95058820476905193879620374676522890539817126922316451905317865021232804624625 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.95058820476905193879620374676522890539817126922316451905317865021232804624625
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.106212438069941718604721267876091661651998870775187732088281663202752715163748
Short name T633
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.9 seconds
Started Oct 29 12:29:51 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 200912 kb
Host smart-42881ed7-5f56-4af6-aabb-4e35ecd10cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106212438069941718604721267876091661651998870775187732088281663202752715163748 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.sysrst_ctrl_smoke.106212438069941718604721267876091661651998870775187732088281663202752715163748
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.30635564070271870480703953309173221814702916083671841679645301812474753181787
Short name T33
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.86 seconds
Started Oct 29 12:29:57 PM PDT 23
Finished Oct 29 12:32:15 PM PDT 23
Peak memory 201416 kb
Host smart-f630136f-41da-4556-a956-9d7586c394a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635564070271870480703953309173221814702916083671841679645301812474753181787 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.30635564070271870480703953309173221814702916083671841679645301812474753181787
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.98909583167444355117266822033072614814930971799462372327588896589123408032199
Short name T295
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 29 12:29:54 PM PDT 23
Finished Oct 29 12:29:59 PM PDT 23
Peak memory 201040 kb
Host smart-3a9fc5bc-184b-4f4d-b7eb-dda656a74c5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98909583167444355117266822033072614814930971799462372327588896589123408032199 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.989095831674443551172668220330726148149309717994623723275888
96589123408032199
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.31450799181980384688962764795724105235933569455502579657281349537456156147003
Short name T400
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 29 12:30:19 PM PDT 23
Finished Oct 29 12:30:23 PM PDT 23
Peak memory 201008 kb
Host smart-7a3b2de9-416b-4e93-bad5-e7a2f53f5e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31450799181980384688962764795724105235933569455502579657281349537456156147003 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.31450799181980384688962764795724105235933569455502579657281349537456156147003
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.42828100151633982901656393461319108479376562579051091939082222751819177376729
Short name T123
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.63 seconds
Started Oct 29 12:30:15 PM PDT 23
Finished Oct 29 12:30:21 PM PDT 23
Peak memory 201076 kb
Host smart-1f714f63-c432-49b8-8531-ad17c873c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42828100151633982901656393461319108479376562579051091939082222751819177376729 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.42828100151633982901656393461319108479376562579051091939082222751819177376729
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2744068295490443121559831635249582130490788661899951558239422259109111059136
Short name T463
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.54 seconds
Started Oct 29 12:30:17 PM PDT 23
Finished Oct 29 12:33:21 PM PDT 23
Peak memory 201560 kb
Host smart-883405ab-b4d8-4b37-82ec-b60636e68270
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744068295490443121559831635249582130490788661899951558239422259109111059136 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.274406829549044312155983163524958213049078866189995155823942225
9109111059136
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.73774690430461656665623833485854691177265938597844463221358673596658981846377
Short name T339
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Oct 29 12:30:16 PM PDT 23
Finished Oct 29 12:30:23 PM PDT 23
Peak memory 201048 kb
Host smart-8f0f6782-3529-462f-812b-54de1b9121f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73774690430461656665623833485854691177265938597844463221358673596658981846377 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.737746904304616566656238334858546911772659385978444632213586
73596658981846377
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.90009420921486111159195206668350235929517664745587557424020893072808765511011
Short name T421
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.35 seconds
Started Oct 29 12:30:19 PM PDT 23
Finished Oct 29 12:30:26 PM PDT 23
Peak memory 200992 kb
Host smart-46cd08be-6fd6-45c0-a978-8806d39ed65c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90009420921486111159195206668350235929517664745587557424020893072808765511011 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.9000942092148611115919520666835023592951766474558755742402089307
2808765511011
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.71342155835610202015008717788821203982493722591561814529881264344039932860425
Short name T195
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.79 seconds
Started Oct 29 12:30:11 PM PDT 23
Finished Oct 29 12:30:16 PM PDT 23
Peak memory 201056 kb
Host smart-dff6c927-4316-4245-aa56-768c41096620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71342155835610202015008717788821203982493722591561814529881264344039932860425 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.71342155835610202015008717788821203982493722591561814529881264344039932860425
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.51717230441935187854703703668664523503957027188861606914362117179734442635694
Short name T201
Test name
Test status
Simulation time 2470384766 ps
CPU time 5.05 seconds
Started Oct 29 12:29:58 PM PDT 23
Finished Oct 29 12:30:03 PM PDT 23
Peak memory 201176 kb
Host smart-d8c4069f-a502-4907-a56b-e3d02270c961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51717230441935187854703703668664523503957027188861606914362117179734442635694 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.51717230441935187854703703668664523503957027188861606914362117179734442635694
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.99732292507695005933134595104847718855580576212477943873717666912056796609991
Short name T668
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Oct 29 12:29:52 PM PDT 23
Finished Oct 29 12:29:57 PM PDT 23
Peak memory 201000 kb
Host smart-eb0d823b-4084-4c97-b5e9-9548a4f607bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99732292507695005933134595104847718855580576212477943873717666912056796609991 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.99732292507695005933134595104847718855580576212477943873717666912056796609991
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.16592265934070894047121416773289924250372461083486973032027418068018007817386
Short name T655
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.64 seconds
Started Oct 29 12:29:57 PM PDT 23
Finished Oct 29 12:30:02 PM PDT 23
Peak memory 201016 kb
Host smart-db9c8757-b3c5-46cd-b7f9-4c152bd454ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16592265934070894047121416773289924250372461083486973032027418068018007817386 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.16592265934070894047121416773289924250372461083486973032027418068018007817386
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.65173990410380599411820081393267528101761651472758767311279582689238175360307
Short name T149
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 29 12:29:58 PM PDT 23
Finished Oct 29 12:30:02 PM PDT 23
Peak memory 201076 kb
Host smart-99115cba-6b2a-4abf-960d-6bb53b4175fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65173990410380599411820081393267528101761651472758767311279582689238175360307 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_smoke.65173990410380599411820081393267528101761651472758767311279582689238175360307
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.113308395361051967480849565705863982691786678691025554102231274532556001882948
Short name T266
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.02 seconds
Started Oct 29 12:30:10 PM PDT 23
Finished Oct 29 12:32:28 PM PDT 23
Peak memory 201320 kb
Host smart-4c232725-f4b5-449c-a3d6-87e6ed96a471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113308395361051967480849565705863982691786678691025554102231274532556001882948 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.113308395361051967480849565705863982691786678691025554102231274532556001882948
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.51222283833284754188501890475403520898575473353711064915755490418174803049197
Short name T37
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.8 seconds
Started Oct 29 12:30:09 PM PDT 23
Finished Oct 29 12:30:14 PM PDT 23
Peak memory 200972 kb
Host smart-b8a37eea-cedf-4799-ac59-cc623c4f8cc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51222283833284754188501890475403520898575473353711064915755490418174803049197 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.512222838332847541885018904754035208985754733537110649157554
90418174803049197
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.22123269257916167457302410255050495181932644522027840385172554477040780788812
Short name T250
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.77 seconds
Started Oct 29 12:30:08 PM PDT 23
Finished Oct 29 12:30:12 PM PDT 23
Peak memory 201052 kb
Host smart-1e006382-a238-4110-91dc-e8cfac63ba0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22123269257916167457302410255050495181932644522027840385172554477040780788812 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.22123269257916167457302410255050495181932644522027840385172554477040780788812
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.18620466557738070570767944199689158369175523674478924175763283484320500356774
Short name T469
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.54 seconds
Started Oct 29 12:30:17 PM PDT 23
Finished Oct 29 12:30:23 PM PDT 23
Peak memory 201032 kb
Host smart-79214e64-e755-4688-b382-5f3cb2c3d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18620466557738070570767944199689158369175523674478924175763283484320500356774 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.18620466557738070570767944199689158369175523674478924175763283484320500356774
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.106824835434666536142942115548156390349334320106311068486252242983546315506240
Short name T419
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.98 seconds
Started Oct 29 12:30:14 PM PDT 23
Finished Oct 29 12:33:19 PM PDT 23
Peak memory 201372 kb
Host smart-deeb96d4-ed95-470b-a46f-ca020c4d8355
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106824835434666536142942115548156390349334320106311068486252242983546315506240 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.1068248354346665361429421155481563903493343201063110684862522
42983546315506240
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.22632612092871289311343252881780895529170168673075896355705766543059411216661
Short name T107
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Oct 29 12:30:11 PM PDT 23
Finished Oct 29 12:30:19 PM PDT 23
Peak memory 201012 kb
Host smart-14c2d071-3204-45f1-8986-c3213f7adad3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22632612092871289311343252881780895529170168673075896355705766543059411216661 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.226326120928712893113432528817808955291701686730758963557057
66543059411216661
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.55872510628660560754710929725670049042393062876709401587547147330163900780068
Short name T139
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Oct 29 12:30:13 PM PDT 23
Finished Oct 29 12:30:19 PM PDT 23
Peak memory 201028 kb
Host smart-6c0e312a-1208-45c4-a4f1-3ec11c637bca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55872510628660560754710929725670049042393062876709401587547147330163900780068 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.5587251062866056075471092972567004904239306287670940158754714733
0163900780068
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.55995022352749872651116683938541267886282664211179584566087558038612201778255
Short name T613
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 29 12:30:16 PM PDT 23
Finished Oct 29 12:30:21 PM PDT 23
Peak memory 201020 kb
Host smart-5678146e-a0c9-46f4-94b8-dcefc4186742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55995022352749872651116683938541267886282664211179584566087558038612201778255 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.55995022352749872651116683938541267886282664211179584566087558038612201778255
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.69659000956431281226185403305975574940293801876715185420018753835442327812256
Short name T191
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 29 12:30:16 PM PDT 23
Finished Oct 29 12:30:21 PM PDT 23
Peak memory 201036 kb
Host smart-fcafb155-f84c-4c3f-becc-5ed04e5a455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69659000956431281226185403305975574940293801876715185420018753835442327812256 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.69659000956431281226185403305975574940293801876715185420018753835442327812256
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.24522156858705166936629135210633835883008931950881732430855309051923484453242
Short name T249
Test name
Test status
Simulation time 2074566504 ps
CPU time 4.05 seconds
Started Oct 29 12:30:11 PM PDT 23
Finished Oct 29 12:30:16 PM PDT 23
Peak memory 200980 kb
Host smart-43db1aa7-b808-4cfa-9fad-521f1a7d8dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24522156858705166936629135210633835883008931950881732430855309051923484453242 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.24522156858705166936629135210633835883008931950881732430855309051923484453242
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.87065324903770069379485197026731867024742392980087529485839502976604288881240
Short name T564
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Oct 29 12:30:12 PM PDT 23
Finished Oct 29 12:30:17 PM PDT 23
Peak memory 201008 kb
Host smart-cf4992e1-f778-49fd-a74a-d991087b508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87065324903770069379485197026731867024742392980087529485839502976604288881240 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.87065324903770069379485197026731867024742392980087529485839502976604288881240
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.4665547552558029489401117647202766352464532799888947521836793255489551611940
Short name T306
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.89 seconds
Started Oct 29 12:30:14 PM PDT 23
Finished Oct 29 12:30:19 PM PDT 23
Peak memory 200944 kb
Host smart-c77458eb-0b08-460d-b325-8dcf6720c07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4665547552558029489401117647202766352464532799888947521836793255489551611940 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sysrst_ctrl_smoke.4665547552558029489401117647202766352464532799888947521836793255489551611940
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.75411780384809932281410348299959991287659924522743873902251442013156549733595
Short name T573
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.23 seconds
Started Oct 29 12:30:14 PM PDT 23
Finished Oct 29 12:32:31 PM PDT 23
Peak memory 201416 kb
Host smart-e7274254-f985-4ff7-9002-f658f647dd0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75411780384809932281410348299959991287659924522743873902251442013156549733595 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.75411780384809932281410348299959991287659924522743873902251442013156549733595
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.96283426189112632551863089318442855738936794476625850915610029764776647680897
Short name T274
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.88 seconds
Started Oct 29 12:30:15 PM PDT 23
Finished Oct 29 12:30:20 PM PDT 23
Peak memory 201004 kb
Host smart-5d1b95da-754c-4e3c-8b0c-2b33a9546830
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96283426189112632551863089318442855738936794476625850915610029764776647680897 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.962834261891126325518630893184428557389367944766258509156100
29764776647680897
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.92222547192617923798109355241012416082766588625316670339126157069286485693317
Short name T304
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Oct 29 12:30:21 PM PDT 23
Finished Oct 29 12:30:25 PM PDT 23
Peak memory 201048 kb
Host smart-8ba98ae9-0e0e-477f-ad5f-7a71de43a198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92222547192617923798109355241012416082766588625316670339126157069286485693317 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.92222547192617923798109355241012416082766588625316670339126157069286485693317
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.60876353155118376881452798265493629590490560883377817530371461721967021656460
Short name T556
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.55 seconds
Started Oct 29 12:30:17 PM PDT 23
Finished Oct 29 12:30:23 PM PDT 23
Peak memory 201064 kb
Host smart-4845556f-017b-44d3-8e79-07b56bf91bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60876353155118376881452798265493629590490560883377817530371461721967021656460 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.60876353155118376881452798265493629590490560883377817530371461721967021656460
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.42271115011786461140582588892591058709921377995567087916099404709588614921210
Short name T387
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.03 seconds
Started Oct 29 12:30:16 PM PDT 23
Finished Oct 29 12:33:22 PM PDT 23
Peak memory 201364 kb
Host smart-b835d631-9728-4a60-bd20-3a7517653a9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271115011786461140582588892591058709921377995567087916099404709588614921210 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.42271115011786461140582588892591058709921377995567087916099404
709588614921210
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.96840841918043583192851224764735656095613724723760227591033123941919073184918
Short name T603
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.76 seconds
Started Oct 29 12:30:18 PM PDT 23
Finished Oct 29 12:30:26 PM PDT 23
Peak memory 201048 kb
Host smart-1ef19dcd-6042-4c2b-a6ba-3c13a6a2e29b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96840841918043583192851224764735656095613724723760227591033123941919073184918 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.968408419180435831928512247647356560956137247237602275910331
23941919073184918
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.77803061278607136338519152152069290916373139917429486844468981184781020250367
Short name T135
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.4 seconds
Started Oct 29 12:30:17 PM PDT 23
Finished Oct 29 12:30:24 PM PDT 23
Peak memory 201016 kb
Host smart-ceaa3275-ba05-4ae1-b5b4-87b2e1c3db96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77803061278607136338519152152069290916373139917429486844468981184781020250367 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.7780306127860713633851915215206929091637313991742948684446898118
4781020250367
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.42499933143649295891522507518198055750616200773493710511328492085178614015296
Short name T493
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.75 seconds
Started Oct 29 12:30:11 PM PDT 23
Finished Oct 29 12:30:17 PM PDT 23
Peak memory 201012 kb
Host smart-15ee4ef0-84de-4d90-9255-95a3a3cbd5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42499933143649295891522507518198055750616200773493710511328492085178614015296 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.42499933143649295891522507518198055750616200773493710511328492085178614015296
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.87690270373429774355218516309774639413583848571087085893218820924010295873222
Short name T647
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Oct 29 12:30:12 PM PDT 23
Finished Oct 29 12:30:17 PM PDT 23
Peak memory 201004 kb
Host smart-eb59c93b-8fa0-4bd3-9111-80acd2cd0760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87690270373429774355218516309774639413583848571087085893218820924010295873222 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.87690270373429774355218516309774639413583848571087085893218820924010295873222
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.95852221520148495620014683401066402134699551896985617617305842120369564171839
Short name T311
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 29 12:30:08 PM PDT 23
Finished Oct 29 12:30:12 PM PDT 23
Peak memory 200980 kb
Host smart-4770d56b-456e-4866-bb7a-d1e08d7198b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95852221520148495620014683401066402134699551896985617617305842120369564171839 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.95852221520148495620014683401066402134699551896985617617305842120369564171839
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.71142432146181009599869698031364197632760661589548663324001105142421043649290
Short name T519
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.49 seconds
Started Oct 29 12:30:19 PM PDT 23
Finished Oct 29 12:30:24 PM PDT 23
Peak memory 201012 kb
Host smart-15ff8b85-85d3-4126-9165-a82db9cbfa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71142432146181009599869698031364197632760661589548663324001105142421043649290 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.71142432146181009599869698031364197632760661589548663324001105142421043649290
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.2569018058192851754055081178645563379967300837535011874281125634863187389972
Short name T592
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 29 12:30:13 PM PDT 23
Finished Oct 29 12:30:17 PM PDT 23
Peak memory 200960 kb
Host smart-ffaf2c82-aa85-4fd2-bb6a-c5e6e535cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569018058192851754055081178645563379967300837535011874281125634863187389972 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sysrst_ctrl_smoke.2569018058192851754055081178645563379967300837535011874281125634863187389972
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.113913970092295310151011778404085005721324287413385814790947534952303888957558
Short name T378
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.15 seconds
Started Oct 29 12:30:15 PM PDT 23
Finished Oct 29 12:32:33 PM PDT 23
Peak memory 201272 kb
Host smart-1f2aeace-572c-49e8-8e05-b68f782c5d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113913970092295310151011778404085005721324287413385814790947534952303888957558 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.113913970092295310151011778404085005721324287413385814790947534952303888957558
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.13983422651063914222830420922925151212833394724164905262831804033164870873336
Short name T379
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 29 12:30:15 PM PDT 23
Finished Oct 29 12:30:20 PM PDT 23
Peak memory 200992 kb
Host smart-4e200978-59f6-4c80-8def-94905965be4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13983422651063914222830420922925151212833394724164905262831804033164870873336 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.139834226510639142228304209229251512128333947241649052628318
04033164870873336
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.65936922022721137082586119332989972573604899168887605516710188636537429037806
Short name T547
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.88 seconds
Started Oct 29 12:30:17 PM PDT 23
Finished Oct 29 12:30:21 PM PDT 23
Peak memory 201008 kb
Host smart-7da12e05-3be7-46d7-99bf-2da8b3a72a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65936922022721137082586119332989972573604899168887605516710188636537429037806 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.65936922022721137082586119332989972573604899168887605516710188636537429037806
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.22564780330830350275089295816222480877257750718443585244334743416883239286029
Short name T565
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.76 seconds
Started Oct 29 12:30:26 PM PDT 23
Finished Oct 29 12:30:32 PM PDT 23
Peak memory 201044 kb
Host smart-e993f122-b615-4609-b2fd-c2f5a9433977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22564780330830350275089295816222480877257750718443585244334743416883239286029 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.22564780330830350275089295816222480877257750718443585244334743416883239286029
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.23931156477052656590046114358391161176639595502671832639640023068236382141631
Short name T383
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.75 seconds
Started Oct 29 12:30:24 PM PDT 23
Finished Oct 29 12:33:27 PM PDT 23
Peak memory 201216 kb
Host smart-dedad153-0533-4949-b3fb-01bd2378a22d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931156477052656590046114358391161176639595502671832639640023068236382141631 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.23931156477052656590046114358391161176639595502671832639640023
068236382141631
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1116436074076137062783604108124417821497608361237234031733072789021490640336
Short name T483
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 29 12:30:22 PM PDT 23
Finished Oct 29 12:30:30 PM PDT 23
Peak memory 201040 kb
Host smart-bbf3dc2d-da3a-435b-872c-af6e2d7a6857
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116436074076137062783604108124417821497608361237234031733072789021490640336 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.1116436074076137062783604108124417821497608361237234031733072
789021490640336
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.113762470496024515723436394713963845205528913037602061464217615596431758258240
Short name T301
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 29 12:30:29 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 200672 kb
Host smart-51915845-d5f6-4690-867f-ce557a589082
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113762470496024515723436394713963845205528913037602061464217615596431758258240 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.113762470496024515723436394713963845205528913037602061464217615
596431758258240
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.7063663123228080752324384649592605956360766090287600051043145956307850334925
Short name T114
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.84 seconds
Started Oct 29 12:30:25 PM PDT 23
Finished Oct 29 12:30:30 PM PDT 23
Peak memory 201324 kb
Host smart-c90d408a-16b2-4aa1-8992-789564258bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7063663123228080752324384649592605956360766090287600051043145956307850334925 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.7063663123228080752324384649592605956360766090287600051043145956307850334925
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.92499467890296591996613181821292575841622848151581236415830460744756822276509
Short name T111
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.95 seconds
Started Oct 29 12:30:25 PM PDT 23
Finished Oct 29 12:30:30 PM PDT 23
Peak memory 201340 kb
Host smart-2bda24d2-3c81-491e-ac8b-0dc881f71ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92499467890296591996613181821292575841622848151581236415830460744756822276509 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.92499467890296591996613181821292575841622848151581236415830460744756822276509
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.93404252059769808452813746419057430959666620648844386858137509129801948311515
Short name T448
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 29 12:30:21 PM PDT 23
Finished Oct 29 12:30:25 PM PDT 23
Peak memory 200992 kb
Host smart-93e55e93-ffa9-4036-b4ad-c4da65efb140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93404252059769808452813746419057430959666620648844386858137509129801948311515 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.93404252059769808452813746419057430959666620648844386858137509129801948311515
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.88592027112147325765310303039334623308178599294491362381586575416116506785097
Short name T528
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 29 12:30:22 PM PDT 23
Finished Oct 29 12:30:27 PM PDT 23
Peak memory 201024 kb
Host smart-d03ec6af-28ca-4704-91bb-330bb3a36518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88592027112147325765310303039334623308178599294491362381586575416116506785097 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.88592027112147325765310303039334623308178599294491362381586575416116506785097
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.10826883434786228900724390045792179585512634076245642705497617626974054782045
Short name T360
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 29 12:30:16 PM PDT 23
Finished Oct 29 12:30:20 PM PDT 23
Peak memory 200980 kb
Host smart-418cae9b-9427-4459-a0ac-4fe164e4aa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10826883434786228900724390045792179585512634076245642705497617626974054782045 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_smoke.10826883434786228900724390045792179585512634076245642705497617626974054782045
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.19105229393022387026216690390626511262512886948181367615616758161314585027409
Short name T459
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.32 seconds
Started Oct 29 12:30:21 PM PDT 23
Finished Oct 29 12:32:38 PM PDT 23
Peak memory 201296 kb
Host smart-0db5268d-5522-4df1-882f-07e88c5139c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105229393022387026216690390626511262512886948181367615616758161314585027409 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.19105229393022387026216690390626511262512886948181367615616758161314585027409
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.45406738960129737614549041095466933189684156663238721238755318535956750211717
Short name T48
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 29 12:30:28 PM PDT 23
Finished Oct 29 12:30:33 PM PDT 23
Peak memory 200596 kb
Host smart-944f9836-1f96-4552-9f99-c92b716329fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45406738960129737614549041095466933189684156663238721238755318535956750211717 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.454067389601297376145490410954669331896841566632387212387553
18535956750211717
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.80993507455459158784217305977321565753217345155962131562776499969031020860037
Short name T44
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.74 seconds
Started Oct 29 12:30:25 PM PDT 23
Finished Oct 29 12:30:29 PM PDT 23
Peak memory 201032 kb
Host smart-cafe9a3e-0ebf-4e83-a3b4-034711b8dd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80993507455459158784217305977321565753217345155962131562776499969031020860037 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.80993507455459158784217305977321565753217345155962131562776499969031020860037
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.95735928664040745848779868925974694528223794960133685177548149141026811468507
Short name T468
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 29 12:30:23 PM PDT 23
Finished Oct 29 12:30:29 PM PDT 23
Peak memory 201044 kb
Host smart-2db62d67-6f61-4375-9bb9-23cc8c8ab775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95735928664040745848779868925974694528223794960133685177548149141026811468507 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.95735928664040745848779868925974694528223794960133685177548149141026811468507
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.57125741931548895805867436124123200120005909405722873729229425331344780593337
Short name T429
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.96 seconds
Started Oct 29 12:30:24 PM PDT 23
Finished Oct 29 12:33:27 PM PDT 23
Peak memory 201248 kb
Host smart-e50c0b96-0495-4c9b-b192-8eedf69c44bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57125741931548895805867436124123200120005909405722873729229425331344780593337 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.57125741931548895805867436124123200120005909405722873729229425
331344780593337
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.69792054853618826089049875235874741491545737274022940540575680398032876312943
Short name T253
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Oct 29 12:30:16 PM PDT 23
Finished Oct 29 12:30:24 PM PDT 23
Peak memory 201056 kb
Host smart-7db32d7d-8bc0-47a6-85b0-ed2856c1e907
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69792054853618826089049875235874741491545737274022940540575680398032876312943 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.697920548536188260890498752358747414915457372740229405405756
80398032876312943
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.108055495386681818966983418491090764547590440382038214441904338382059668763725
Short name T27
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.41 seconds
Started Oct 29 12:30:24 PM PDT 23
Finished Oct 29 12:30:31 PM PDT 23
Peak memory 201028 kb
Host smart-3cd8147a-0cfa-48af-a105-6f2b268142de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108055495386681818966983418491090764547590440382038214441904338382059668763725 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.108055495386681818966983418491090764547590440382038214441904338
382059668763725
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.17035051619780956321536264441347586572338074393048405966613428003713549482030
Short name T233
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 29 12:30:24 PM PDT 23
Finished Oct 29 12:30:29 PM PDT 23
Peak memory 201000 kb
Host smart-5bf9695b-8706-4382-9b70-6858da242698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17035051619780956321536264441347586572338074393048405966613428003713549482030 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.17035051619780956321536264441347586572338074393048405966613428003713549482030
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.97239242661462691178282567114684599213121525447725203190633144569571798924686
Short name T607
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.94 seconds
Started Oct 29 12:30:25 PM PDT 23
Finished Oct 29 12:30:30 PM PDT 23
Peak memory 201036 kb
Host smart-82857958-0753-4378-83a5-b7ffccc739a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97239242661462691178282567114684599213121525447725203190633144569571798924686 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.97239242661462691178282567114684599213121525447725203190633144569571798924686
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.4582651617903251341731056572167123207351681120283754608169117379171705118014
Short name T611
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Oct 29 12:30:29 PM PDT 23
Finished Oct 29 12:30:35 PM PDT 23
Peak memory 200968 kb
Host smart-2c65bbcd-6b88-4585-a954-8223a7142f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4582651617903251341731056572167123207351681120283754608169117379171705118014 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.4582651617903251341731056572167123207351681120283754608169117379171705118014
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.69809050612302774377230601063770362755024469039776704539877700686304636783750
Short name T268
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 29 12:30:22 PM PDT 23
Finished Oct 29 12:30:27 PM PDT 23
Peak memory 201012 kb
Host smart-acce29ff-5594-4d53-97d8-fba5286c91ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69809050612302774377230601063770362755024469039776704539877700686304636783750 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.69809050612302774377230601063770362755024469039776704539877700686304636783750
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.101791623935525219884845001053770927816855524025117455068883282914390680466160
Short name T172
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 29 12:30:26 PM PDT 23
Finished Oct 29 12:30:30 PM PDT 23
Peak memory 200912 kb
Host smart-5d6e0201-59c2-4375-bdbf-d1c82bb21b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101791623935525219884845001053770927816855524025117455068883282914390680466160 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.sysrst_ctrl_smoke.101791623935525219884845001053770927816855524025117455068883282914390680466160
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.18603217502256416788787243300963946223283709088212516312546973148579946656994
Short name T391
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.08 seconds
Started Oct 29 12:30:23 PM PDT 23
Finished Oct 29 12:32:41 PM PDT 23
Peak memory 201280 kb
Host smart-4b0e5ac0-7f00-4ff6-b385-02969390c2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18603217502256416788787243300963946223283709088212516312546973148579946656994 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.18603217502256416788787243300963946223283709088212516312546973148579946656994
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.23190909670855724063171086239955225940349720041728797978170147034907386820832
Short name T619
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 29 12:30:18 PM PDT 23
Finished Oct 29 12:30:23 PM PDT 23
Peak memory 201004 kb
Host smart-4c4be3bd-d9f4-4d24-b7f2-ce48f3004254
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23190909670855724063171086239955225940349720041728797978170147034907386820832 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.231909096708557240631710862399552259403497200417287979781701
47034907386820832
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.39282014820391028319629249135276225710692765500271253829832624911116657039345
Short name T138
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 29 12:27:48 PM PDT 23
Finished Oct 29 12:27:53 PM PDT 23
Peak memory 200984 kb
Host smart-ade6b654-a91b-40cf-a31d-3c5d546b0db4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282014820391028319629249135276225710692765500271253829832624911116657039345 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.39282014820391028319629249135276225710692765500271253829832624911116657039345
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.44863063060153289803574547053759851295338818101628870147949956573635902538
Short name T91
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 29 12:27:50 PM PDT 23
Finished Oct 29 12:27:57 PM PDT 23
Peak memory 201032 kb
Host smart-c0bdc729-718e-4801-922f-811d4bf2271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44863063060153289803574547053759851295338818101628870147949956573635902538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_
base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.44863063060153289803574547053759851295338818101628870147949956573635902538
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.89052571028535028745457357278374875141721074814038023054429372640546291842269
Short name T509
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.98 seconds
Started Oct 29 12:27:51 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201276 kb
Host smart-dc2d4646-100f-4902-997d-7dbbe3c96db2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89052571028535028745457357278374875141721074814038023054429372640546291842269 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.890525710285350287454573572783748751417210748140380230544293726
40546291842269
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.84549906797469193418428867202797425422688375173310584580670457529125690981251
Short name T524
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.39 seconds
Started Oct 29 12:27:51 PM PDT 23
Finished Oct 29 12:27:57 PM PDT 23
Peak memory 201036 kb
Host smart-dafdb31a-6ae4-4e4d-815b-f4a380657add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84549906797469193418428867202797425422688375173310584580670457529125690981251 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.84549906797469193418428867202797425422688375173310584580670457529125690981251
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.682965099757158857013882880628841421880609390947613661124951876945227017558
Short name T116
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.49 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 200996 kb
Host smart-02923ca0-d5f2-4995-84a8-be5d7dc56a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682965099757158857013882880628841421880609390947613661124951876945227017558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.6829650997571588570138828806288414218806093909476136611
24951876945227017558
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.27441933906994916890508129557133930816896366873776902984090317611902929772271
Short name T388
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:18 PM PDT 23
Peak memory 201040 kb
Host smart-29640ce0-be53-43e9-a0bd-6b3dadb6a97a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27441933906994916890508129557133930816896366873776902984090317611902929772271 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.2744193390699491689050812955713393081689636687377690298409031
7611902929772271
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.47688270441623669882929232439861120218814608607831310767578069174321058214291
Short name T134
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.56 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 200984 kb
Host smart-d884395d-12ae-47f2-add1-e1254031e3a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47688270441623669882929232439861120218814608607831310767578069174321058214291 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.47688270441623669882929232439861120218814608607831310767578069174321058214291
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.31957060478101177713848435152348613978290179613991672395533110703654756070705
Short name T389
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:12 PM PDT 23
Peak memory 200968 kb
Host smart-aa94bc32-aef0-4a4e-8320-3095bdcf743d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31957060478101177713848435152348613978290179613991672395533110703654756070705 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.31957060478101177713848435152348613978290179613991672395533110703654756070705
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.50999836261005036170555042839326694364615877214268011917785850132262075468239
Short name T167
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 29 12:27:55 PM PDT 23
Finished Oct 29 12:28:02 PM PDT 23
Peak memory 200984 kb
Host smart-c58ee8eb-f465-450c-a451-69f09ea14555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50999836261005036170555042839326694364615877214268011917785850132262075468239 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.50999836261005036170555042839326694364615877214268011917785850132262075468239
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.112479699746314293007317402249282636155307143831665166861666959870126473535959
Short name T245
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 29 12:28:03 PM PDT 23
Finished Oct 29 12:28:07 PM PDT 23
Peak memory 200948 kb
Host smart-8f349eb1-9e4e-4db6-9e2c-829956527229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112479699746314293007317402249282636155307143831665166861666959870126473535959 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.112479699746314293007317402249282636155307143831665166861666959870126473535959
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.112117051111417563751271902304892426292028162815766770175926480649831634665378
Short name T252
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.76 seconds
Started Oct 29 12:27:48 PM PDT 23
Finished Oct 29 12:27:54 PM PDT 23
Peak memory 201052 kb
Host smart-132877aa-58da-4514-a6fa-bbf14ab3c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112117051111417563751271902304892426292028162815766770175926480649831634665378 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.112117051111417563751271902304892426292028162815766770175926480649831634665378
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.69922131034804414354342370661412428572085566388169502601088681547787760535146
Short name T141
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.42 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:29:09 PM PDT 23
Peak memory 221400 kb
Host smart-a35dfa3f-4cd7-4248-8983-40b4fa1c5b2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69922131034804414354342370661412428572085566388169502601088681547787760535146 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.69922131034804414354342370661412428572085566388169502601088681547787760535146
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.26811446523363060829296597582875092493492192042777716644399842173928142614177
Short name T296
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.89 seconds
Started Oct 29 12:27:51 PM PDT 23
Finished Oct 29 12:27:57 PM PDT 23
Peak memory 200932 kb
Host smart-ee90447a-7534-45ce-8fef-cff3245c90fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26811446523363060829296597582875092493492192042777716644399842173928142614177 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_smoke.26811446523363060829296597582875092493492192042777716644399842173928142614177
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.17506657220065787381405932899519029160595049133301549431199698116011428211128
Short name T316
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.59 seconds
Started Oct 29 12:27:48 PM PDT 23
Finished Oct 29 12:30:05 PM PDT 23
Peak memory 201432 kb
Host smart-046c42a6-a68a-4a86-b50f-ddcf1f9f3fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506657220065787381405932899519029160595049133301549431199698116011428211128 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.17506657220065787381405932899519029160595049133301549431199698116011428211128
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.30606221653715843138902668948738603627628361996993496955602606019903723097915
Short name T563
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 29 12:27:55 PM PDT 23
Finished Oct 29 12:28:02 PM PDT 23
Peak memory 201000 kb
Host smart-9c179b45-9120-4540-b6ee-bdc9b33b7ab3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30606221653715843138902668948738603627628361996993496955602606019903723097915 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.3060622165371584313890266894873860362762836199699349695560260
6019903723097915
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.93514260189422511315593016831869033694646843354780766673334256360695884256915
Short name T450
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 29 12:30:33 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 201020 kb
Host smart-f048f200-5e14-4194-a21d-4e0f50e7c07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93514260189422511315593016831869033694646843354780766673334256360695884256915 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.93514260189422511315593016831869033694646843354780766673334256360695884256915
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.6310017806508385510382542435872365898868957284252148062755505143295502408545
Short name T432
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 29 12:30:26 PM PDT 23
Finished Oct 29 12:30:31 PM PDT 23
Peak memory 201540 kb
Host smart-13a31414-b4e1-4d4a-a815-e2f52d71b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6310017806508385510382542435872365898868957284252148062755505143295502408545 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.6310017806508385510382542435872365898868957284252148062755505143295502408545
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.31440992305692922363156215189138654864339876767475962460505838962604308537064
Short name T430
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.63 seconds
Started Oct 29 12:30:34 PM PDT 23
Finished Oct 29 12:33:40 PM PDT 23
Peak memory 201364 kb
Host smart-68d6dc3f-5839-40a0-907c-c84451fcc17d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440992305692922363156215189138654864339876767475962460505838962604308537064 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.31440992305692922363156215189138654864339876767475962460505838
962604308537064
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.22905363241987876004564186986358985244418084990598185041398236099475527051262
Short name T163
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.57 seconds
Started Oct 29 12:30:30 PM PDT 23
Finished Oct 29 12:30:38 PM PDT 23
Peak memory 201028 kb
Host smart-6b5bca6c-c4e4-42ab-ada0-2550800bce67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22905363241987876004564186986358985244418084990598185041398236099475527051262 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.229053632419878760045641869863589852444180849905981850413982
36099475527051262
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.11198516104473280034725156001227842672531175556126165497399612750009765422989
Short name T504
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 29 12:30:32 PM PDT 23
Finished Oct 29 12:30:39 PM PDT 23
Peak memory 200976 kb
Host smart-6bd6ce2b-24ba-4312-b8e3-00980ead4fe4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198516104473280034725156001227842672531175556126165497399612750009765422989 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.1119851610447328003472515600122784267253117555612616549739961275
0009765422989
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.54285032654786136579464041768408492700001263223517401030954209690235758721563
Short name T113
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 29 12:30:26 PM PDT 23
Finished Oct 29 12:30:31 PM PDT 23
Peak memory 201016 kb
Host smart-565af03b-6f06-4ab5-89ab-de76956492a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54285032654786136579464041768408492700001263223517401030954209690235758721563 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.54285032654786136579464041768408492700001263223517401030954209690235758721563
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.109290662874282178968111504854494131641195770145384047893595378385483382039198
Short name T374
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 29 12:30:29 PM PDT 23
Finished Oct 29 12:30:34 PM PDT 23
Peak memory 201020 kb
Host smart-af2253fa-1a00-4067-8ae7-d051f2affd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109290662874282178968111504854494131641195770145384047893595378385483382039198 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.109290662874282178968111504854494131641195770145384047893595378385483382039198
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.101826041770063803764464480509651565706522731429366012019501751900513742634741
Short name T307
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 29 12:30:28 PM PDT 23
Finished Oct 29 12:30:32 PM PDT 23
Peak memory 200988 kb
Host smart-50330ea4-1a20-45a0-88dc-7eccd68517eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101826041770063803764464480509651565706522731429366012019501751900513742634741 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.101826041770063803764464480509651565706522731429366012019501751900513742634741
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.101511277131120949848933723808669651089409026319508357440350049159730288631358
Short name T223
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.73 seconds
Started Oct 29 12:30:28 PM PDT 23
Finished Oct 29 12:30:33 PM PDT 23
Peak memory 201000 kb
Host smart-25c99f65-f2f1-491f-81b9-14964a17ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101511277131120949848933723808669651089409026319508357440350049159730288631358 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.101511277131120949848933723808669651089409026319508357440350049159730288631358
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.68295798630744972183044895262008249702120477895680547569173451207332146757545
Short name T484
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 29 12:30:29 PM PDT 23
Finished Oct 29 12:30:35 PM PDT 23
Peak memory 200732 kb
Host smart-3bae342e-0053-4cc0-8e5f-474cec2d1318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68295798630744972183044895262008249702120477895680547569173451207332146757545 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_smoke.68295798630744972183044895262008249702120477895680547569173451207332146757545
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.78357899998193744087161136646720717832608765125205605758525044042980078913513
Short name T606
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.21 seconds
Started Oct 29 12:30:29 PM PDT 23
Finished Oct 29 12:32:48 PM PDT 23
Peak memory 201280 kb
Host smart-2ea8f301-fbe8-44d4-9306-c3029ee971b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78357899998193744087161136646720717832608765125205605758525044042980078913513 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.78357899998193744087161136646720717832608765125205605758525044042980078913513
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.57494067903475453089696000841858451458277967384304802038713300068072307616249
Short name T303
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Oct 29 12:30:32 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 200972 kb
Host smart-d92ecfdf-0cdc-4fdd-b695-e99df30d47ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57494067903475453089696000841858451458277967384304802038713300068072307616249 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.574940679034754530896960008418584514582779673843048020387133
00068072307616249
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.71417800925269290043973323719569567811730810639696659936800934894806030014106
Short name T395
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 29 12:30:38 PM PDT 23
Finished Oct 29 12:30:42 PM PDT 23
Peak memory 201008 kb
Host smart-2ad6ae6d-cdb4-463e-a93a-3e60987199c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71417800925269290043973323719569567811730810639696659936800934894806030014106 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.71417800925269290043973323719569567811730810639696659936800934894806030014106
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.86748493239403485489020160258740232517620350340865057334509085334867874296504
Short name T127
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 29 12:30:37 PM PDT 23
Finished Oct 29 12:30:43 PM PDT 23
Peak memory 201020 kb
Host smart-920dbbeb-96f3-4cd3-8914-4eca45265d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86748493239403485489020160258740232517620350340865057334509085334867874296504 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.86748493239403485489020160258740232517620350340865057334509085334867874296504
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.69893383312989192917306886338241490841308508034672820253850159449189623007962
Short name T216
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.27 seconds
Started Oct 29 12:30:37 PM PDT 23
Finished Oct 29 12:33:41 PM PDT 23
Peak memory 201208 kb
Host smart-79211f21-b086-4258-9f72-db15e68ca05d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69893383312989192917306886338241490841308508034672820253850159449189623007962 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.69893383312989192917306886338241490841308508034672820253850159
449189623007962
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.19839752087664226411008134289660924887633250327288594036070442853746954909423
Short name T344
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Oct 29 12:30:33 PM PDT 23
Finished Oct 29 12:30:41 PM PDT 23
Peak memory 201048 kb
Host smart-e6c28583-e332-4234-b63f-4248bce7cce7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839752087664226411008134289660924887633250327288594036070442853746954909423 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.198397520876642264110081342896609248876332503272885940360704
42853746954909423
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.98257908753161222964550790395384607919471409134300955136255267020628115946113
Short name T314
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 29 12:30:30 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 201004 kb
Host smart-44f44fa0-935e-405f-9a19-8048db59b2a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98257908753161222964550790395384607919471409134300955136255267020628115946113 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.9825790875316122296455079039538460791947140913430095513625526702
0628115946113
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.32624768998092425167271012608863694954254671250489689153287016152669913644279
Short name T181
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 29 12:30:30 PM PDT 23
Finished Oct 29 12:30:36 PM PDT 23
Peak memory 201012 kb
Host smart-563dd737-4e8a-4e25-87a2-5db099518b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32624768998092425167271012608863694954254671250489689153287016152669913644279 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.32624768998092425167271012608863694954254671250489689153287016152669913644279
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.84250498613309783017606835626705040870398189666316774663188660387850636108340
Short name T630
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Oct 29 12:30:32 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 201000 kb
Host smart-de18f97c-ed9d-4b21-a511-e393a40176db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84250498613309783017606835626705040870398189666316774663188660387850636108340 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.84250498613309783017606835626705040870398189666316774663188660387850636108340
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.111838996408988838102196759181934804422331472107663508944170052651176622085274
Short name T196
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.86 seconds
Started Oct 29 12:30:34 PM PDT 23
Finished Oct 29 12:30:38 PM PDT 23
Peak memory 201068 kb
Host smart-ccc45915-9f30-4dcd-9cbb-8b27462d843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111838996408988838102196759181934804422331472107663508944170052651176622085274 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.111838996408988838102196759181934804422331472107663508944170052651176622085274
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.31598444895070897837484648784018085092633788749114469536115154909798338651507
Short name T458
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Oct 29 12:30:30 PM PDT 23
Finished Oct 29 12:30:36 PM PDT 23
Peak memory 201044 kb
Host smart-f19c99cb-c8ad-4866-adae-b29aecbddd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31598444895070897837484648784018085092633788749114469536115154909798338651507 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.31598444895070897837484648784018085092633788749114469536115154909798338651507
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.74460520469738894708251297834849536788322355550521173342846237468468712352530
Short name T513
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 29 12:30:34 PM PDT 23
Finished Oct 29 12:30:38 PM PDT 23
Peak memory 200924 kb
Host smart-475396e9-37ed-4af7-b0c1-29d70f30d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74460520469738894708251297834849536788322355550521173342846237468468712352530 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_smoke.74460520469738894708251297834849536788322355550521173342846237468468712352530
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.74153980151337522821438590041931080195616546530298127187192556745927851086202
Short name T321
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 29 12:30:29 PM PDT 23
Finished Oct 29 12:30:36 PM PDT 23
Peak memory 200996 kb
Host smart-d3aa885e-8c30-43f9-ad6b-b75037328dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74153980151337522821438590041931080195616546530298127187192556745927851086202 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.741539801513375228214385900419310801956165465302981271871925
56745927851086202
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.74609773174462654987854244657264699399106801032840088106740517875516305421216
Short name T179
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 29 12:30:38 PM PDT 23
Finished Oct 29 12:30:42 PM PDT 23
Peak memory 201020 kb
Host smart-47314944-f3da-4e8f-aaf1-0541721133af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74609773174462654987854244657264699399106801032840088106740517875516305421216 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.74609773174462654987854244657264699399106801032840088106740517875516305421216
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.91847193382868714013904527724514751600075155563600749188503901099288943084508
Short name T645
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Oct 29 12:30:31 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 201088 kb
Host smart-39711463-73a1-4004-8dd8-8dadb446d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91847193382868714013904527724514751600075155563600749188503901099288943084508 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.91847193382868714013904527724514751600075155563600749188503901099288943084508
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.13721090542372917753768638466421716343090724826858795204441443330798151471927
Short name T204
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.78 seconds
Started Oct 29 12:30:33 PM PDT 23
Finished Oct 29 12:33:37 PM PDT 23
Peak memory 201276 kb
Host smart-75e12d89-0cff-4dbd-9d91-4f64f97adf4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13721090542372917753768638466421716343090724826858795204441443330798151471927 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.13721090542372917753768638466421716343090724826858795204441443
330798151471927
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.59535266103700661494377668585199269965639293370430404980182413427621284709559
Short name T294
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 29 12:30:37 PM PDT 23
Finished Oct 29 12:30:45 PM PDT 23
Peak memory 201016 kb
Host smart-c4961662-d2dd-4a2e-bcd5-6118fe0b3c9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59535266103700661494377668585199269965639293370430404980182413427621284709559 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.595352661037006614943776685851992699656392933704304049801824
13427621284709559
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.31434946104300911698410026511372721615951242039202475563852022763604035704634
Short name T580
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 29 12:30:35 PM PDT 23
Finished Oct 29 12:30:42 PM PDT 23
Peak memory 201004 kb
Host smart-9355a806-cdf3-4368-bf51-75869acbed6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31434946104300911698410026511372721615951242039202475563852022763604035704634 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.3143494610430091169841002651137272161595124203920247556385202276
3604035704634
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.112567429429318226189491756773926542795987824958632792695978644023356476120131
Short name T359
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 29 12:30:37 PM PDT 23
Finished Oct 29 12:30:42 PM PDT 23
Peak memory 200976 kb
Host smart-46ca12f1-b4c2-41ce-b3c1-c00196acd1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112567429429318226189491756773926542795987824958632792695978644023356476120131 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.112567429429318226189491756773926542795987824958632792695978644023356476120131
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.34550703833747579591512490013343599021932506118854371655119330408446434336869
Short name T621
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.89 seconds
Started Oct 29 12:30:38 PM PDT 23
Finished Oct 29 12:30:43 PM PDT 23
Peak memory 201012 kb
Host smart-9df4d8f6-64f8-4aaa-9207-d6fa1904dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34550703833747579591512490013343599021932506118854371655119330408446434336869 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.34550703833747579591512490013343599021932506118854371655119330408446434336869
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.72930103602956359867573833297593739288629600565414856603635034436481543867494
Short name T530
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 29 12:30:31 PM PDT 23
Finished Oct 29 12:30:36 PM PDT 23
Peak memory 200992 kb
Host smart-89591e44-a57b-473f-b299-317e61a202f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72930103602956359867573833297593739288629600565414856603635034436481543867494 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.72930103602956359867573833297593739288629600565414856603635034436481543867494
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.18298942322872021734827807110823498774786578992956912640513900055971331052011
Short name T282
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Oct 29 12:30:35 PM PDT 23
Finished Oct 29 12:30:40 PM PDT 23
Peak memory 201008 kb
Host smart-b50e7356-2fd8-437d-82d7-6edf25729c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18298942322872021734827807110823498774786578992956912640513900055971331052011 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.18298942322872021734827807110823498774786578992956912640513900055971331052011
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.27832796498418219383532511270405985987136869770084539795786997604345915869513
Short name T622
Test name
Test status
Simulation time 2116887594 ps
CPU time 4.01 seconds
Started Oct 29 12:30:31 PM PDT 23
Finished Oct 29 12:30:35 PM PDT 23
Peak memory 200888 kb
Host smart-364703ff-2079-4ccf-94fc-61d0dff8addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27832796498418219383532511270405985987136869770084539795786997604345915869513 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sysrst_ctrl_smoke.27832796498418219383532511270405985987136869770084539795786997604345915869513
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.13600806622432354328684582705824861364055913798908259858476271676763793148610
Short name T371
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.48 seconds
Started Oct 29 12:30:42 PM PDT 23
Finished Oct 29 12:32:59 PM PDT 23
Peak memory 199984 kb
Host smart-ccc5e4a0-ee6f-4ba7-8b02-630be0b9f179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600806622432354328684582705824861364055913798908259858476271676763793148610 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.13600806622432354328684582705824861364055913798908259858476271676763793148610
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.47448932639050811582863194415409511045371068899826160626126722634935430254039
Short name T230
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.8 seconds
Started Oct 29 12:30:32 PM PDT 23
Finished Oct 29 12:30:37 PM PDT 23
Peak memory 200996 kb
Host smart-a0be808f-2b6b-4d87-a18b-bb820d22fb1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47448932639050811582863194415409511045371068899826160626126722634935430254039 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.474489326390508115828631944154095110453710688998261606261267
22634935430254039
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.33012264509109981907053781464994936723262619626255910804621996982631979533895
Short name T527
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Oct 29 12:30:39 PM PDT 23
Finished Oct 29 12:30:43 PM PDT 23
Peak memory 201020 kb
Host smart-baac4580-85cf-40b7-a82b-f026bc4eebf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33012264509109981907053781464994936723262619626255910804621996982631979533895 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.33012264509109981907053781464994936723262619626255910804621996982631979533895
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.82676760758207249165721868577876687466987692778344870537685948649843873382363
Short name T97
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Oct 29 12:30:40 PM PDT 23
Finished Oct 29 12:30:45 PM PDT 23
Peak memory 201372 kb
Host smart-c39bca1e-890b-4c0b-9f16-352e6a9bc4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82676760758207249165721868577876687466987692778344870537685948649843873382363 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.82676760758207249165721868577876687466987692778344870537685948649843873382363
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.17498436728504087429629953370153957991229806679557736746019511517298135747570
Short name T288
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.42 seconds
Started Oct 29 12:30:37 PM PDT 23
Finished Oct 29 12:33:42 PM PDT 23
Peak memory 201376 kb
Host smart-3b3b7e39-23d9-401a-8417-679ac3e9e02a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17498436728504087429629953370153957991229806679557736746019511517298135747570 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.17498436728504087429629953370153957991229806679557736746019511
517298135747570
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.58945426265594779514724416968316412895181837368505542926251782137639030068664
Short name T200
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.3 seconds
Started Oct 29 12:30:39 PM PDT 23
Finished Oct 29 12:30:46 PM PDT 23
Peak memory 201028 kb
Host smart-6c59c576-ae7c-4bdb-b733-21ccf2d48afa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58945426265594779514724416968316412895181837368505542926251782137639030068664 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.589454262655947795147244169683164128951818373685055429262517
82137639030068664
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.78474556786221852272226329041715194190350352145885334150257506510880137291106
Short name T507
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:55 PM PDT 23
Peak memory 200964 kb
Host smart-c3fa6470-76cc-4a2e-8ff5-7838cb5ea9af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78474556786221852272226329041715194190350352145885334150257506510880137291106 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.7847455678622185227222632904171519419035035214588533415025750651
0880137291106
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.23389356464586439174240576334047215648364041708145254336943932077687156513843
Short name T254
Test name
Test status
Simulation time 2619740714 ps
CPU time 5.03 seconds
Started Oct 29 12:30:40 PM PDT 23
Finished Oct 29 12:30:45 PM PDT 23
Peak memory 201024 kb
Host smart-6c1532b5-eb82-4b49-8d79-3cfe4457eeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23389356464586439174240576334047215648364041708145254336943932077687156513843 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.23389356464586439174240576334047215648364041708145254336943932077687156513843
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.89385927512359228510055856267856112087883174850485694017346052520077339640140
Short name T198
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201016 kb
Host smart-f71691df-c2c6-4ddf-aa76-d36cf4cdb325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89385927512359228510055856267856112087883174850485694017346052520077339640140 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.89385927512359228510055856267856112087883174850485694017346052520077339640140
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.25395784871848469062115059707296901942823240548004967855101742176970302590196
Short name T263
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 29 12:30:43 PM PDT 23
Finished Oct 29 12:30:47 PM PDT 23
Peak memory 200960 kb
Host smart-6b5dc9a5-a030-47aa-becf-de95082f5079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25395784871848469062115059707296901942823240548004967855101742176970302590196 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.25395784871848469062115059707296901942823240548004967855101742176970302590196
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.9332741085683707531034967532562081852017441088093117389830012826182732883990
Short name T654
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 29 12:30:41 PM PDT 23
Finished Oct 29 12:30:46 PM PDT 23
Peak memory 201052 kb
Host smart-be3121e9-3afa-4e31-9668-6ca8a00bb5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9332741085683707531034967532562081852017441088093117389830012826182732883990 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.9332741085683707531034967532562081852017441088093117389830012826182732883990
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.52561305426891706044908432904362335300869635840585055393465133407510107671594
Short name T433
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 29 12:30:39 PM PDT 23
Finished Oct 29 12:30:43 PM PDT 23
Peak memory 200952 kb
Host smart-eeb2cd40-1437-4024-a259-515e43b63b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52561305426891706044908432904362335300869635840585055393465133407510107671594 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_smoke.52561305426891706044908432904362335300869635840585055393465133407510107671594
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.109256318486571679732322240540814924401038272164074329584043455637587328857652
Short name T326
Test name
Test status
Simulation time 87228974549 ps
CPU time 138.31 seconds
Started Oct 29 12:30:38 PM PDT 23
Finished Oct 29 12:32:57 PM PDT 23
Peak memory 201272 kb
Host smart-ec95a3a3-e342-4926-8ad1-6b87720bc4e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109256318486571679732322240540814924401038272164074329584043455637587328857652 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.109256318486571679732322240540814924401038272164074329584043455637587328857652
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.66273227814350596794789814395042695006692903638332824497559043527752570196814
Short name T624
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 29 12:30:42 PM PDT 23
Finished Oct 29 12:30:47 PM PDT 23
Peak memory 200980 kb
Host smart-a1e87b9c-0f5a-4d39-bdc2-e66fa27576be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66273227814350596794789814395042695006692903638332824497559043527752570196814 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.662732278143505967947898143950426950066929036383328244975590
43527752570196814
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.88760565043273329524787677501767415723137726522842769471904277056908189497517
Short name T533
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 29 12:30:42 PM PDT 23
Finished Oct 29 12:30:46 PM PDT 23
Peak memory 201004 kb
Host smart-5b9515d2-366d-43b8-9586-c576c48d7c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88760565043273329524787677501767415723137726522842769471904277056908189497517 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.88760565043273329524787677501767415723137726522842769471904277056908189497517
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.21080382224344532913258334054266702665563481669314955746208452001127059911299
Short name T443
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Oct 29 12:30:39 PM PDT 23
Finished Oct 29 12:30:45 PM PDT 23
Peak memory 201044 kb
Host smart-44322345-aabc-4003-8fd3-509fb0542f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21080382224344532913258334054266702665563481669314955746208452001127059911299 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.21080382224344532913258334054266702665563481669314955746208452001127059911299
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.104382406589837991631238865417706321686640707030670658057217857069675479746068
Short name T222
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.29 seconds
Started Oct 29 12:30:40 PM PDT 23
Finished Oct 29 12:33:45 PM PDT 23
Peak memory 201264 kb
Host smart-336f3de8-9ee1-47a4-814d-165bd4cd6299
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104382406589837991631238865417706321686640707030670658057217857069675479746068 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.1043824065898379916312388654177063216866407070306706580572178
57069675479746068
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.5057927482212299451340681259011325573046007060381901498939349058739911258287
Short name T465
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Oct 29 12:30:39 PM PDT 23
Finished Oct 29 12:30:47 PM PDT 23
Peak memory 201048 kb
Host smart-f2856325-9608-4b2d-9bc5-60853c9a8ea6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5057927482212299451340681259011325573046007060381901498939349058739911258287 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.5057927482212299451340681259011325573046007060381901498939349
058739911258287
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.90736719523633736038967852928393901706278827982820167181200106617779275777934
Short name T500
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 29 12:30:43 PM PDT 23
Finished Oct 29 12:30:49 PM PDT 23
Peak memory 200980 kb
Host smart-865c4d5f-756b-4f4a-a9e1-ea9e7bba075b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90736719523633736038967852928393901706278827982820167181200106617779275777934 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.9073671952363373603896785292839390170627882798282016718120010661
7779275777934
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.109024627136576268639991867466061685783604451031140524587339917546782741161490
Short name T102
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 29 12:30:45 PM PDT 23
Finished Oct 29 12:30:50 PM PDT 23
Peak memory 201024 kb
Host smart-68bbc70e-6d0d-430c-b0c2-f119879418df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109024627136576268639991867466061685783604451031140524587339917546782741161490 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.109024627136576268639991867466061685783604451031140524587339917546782741161490
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.68538291630922271093234576134699183566819251762471963329422277873294673771534
Short name T284
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201016 kb
Host smart-84d5ddc3-2f5f-4a3e-9102-2859e8ddd02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68538291630922271093234576134699183566819251762471963329422277873294673771534 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.68538291630922271093234576134699183566819251762471963329422277873294673771534
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.41996710450928776623443485843164256115414369692273689575056720577090218856309
Short name T283
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 29 12:30:43 PM PDT 23
Finished Oct 29 12:30:47 PM PDT 23
Peak memory 200980 kb
Host smart-ae65d78c-f1cc-45c5-a9e0-b22158506567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41996710450928776623443485843164256115414369692273689575056720577090218856309 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.41996710450928776623443485843164256115414369692273689575056720577090218856309
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.103335914760683005755299935140056615136397486893436663264838094562384993240435
Short name T271
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.64 seconds
Started Oct 29 12:30:41 PM PDT 23
Finished Oct 29 12:30:46 PM PDT 23
Peak memory 201008 kb
Host smart-45e8139a-8a7e-4ce7-8dd2-0a31a50c7c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103335914760683005755299935140056615136397486893436663264838094562384993240435 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.103335914760683005755299935140056615136397486893436663264838094562384993240435
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.113632799993135176673484646662157088462323464487855808774486461506738078813242
Short name T539
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 29 12:30:42 PM PDT 23
Finished Oct 29 12:30:46 PM PDT 23
Peak memory 199652 kb
Host smart-1fdae0c4-a9be-4037-a85e-4de8c33d95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113632799993135176673484646662157088462323464487855808774486461506738078813242 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.sysrst_ctrl_smoke.113632799993135176673484646662157088462323464487855808774486461506738078813242
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.54660909744830960636436480060222605023755727806705307701506540650019507863439
Short name T131
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.73 seconds
Started Oct 29 12:30:46 PM PDT 23
Finished Oct 29 12:33:03 PM PDT 23
Peak memory 201416 kb
Host smart-cdff0cd7-7177-4ec9-92a3-7fed5493a065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54660909744830960636436480060222605023755727806705307701506540650019507863439 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.54660909744830960636436480060222605023755727806705307701506540650019507863439
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.66416401181205412927227350626639882144993421003138016262985107448375337156783
Short name T47
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.93 seconds
Started Oct 29 12:30:40 PM PDT 23
Finished Oct 29 12:30:45 PM PDT 23
Peak memory 201008 kb
Host smart-19ca3799-8344-42e8-8fcf-b6bdffb4d6dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66416401181205412927227350626639882144993421003138016262985107448375337156783 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.664164011812054129272273506266398821449934210031380162629851
07448375337156783
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.69039111805196352278844761444453125124803129941742166842256139220387300753741
Short name T346
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 29 12:30:48 PM PDT 23
Finished Oct 29 12:30:52 PM PDT 23
Peak memory 201020 kb
Host smart-d5396cdf-f027-438b-8e03-f7b13bc89a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69039111805196352278844761444453125124803129941742166842256139220387300753741 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.69039111805196352278844761444453125124803129941742166842256139220387300753741
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1025601744423837368130350739600292153036777663984749012349423310275133266440
Short name T119
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 29 12:30:43 PM PDT 23
Finished Oct 29 12:30:49 PM PDT 23
Peak memory 201108 kb
Host smart-499ae068-db7b-4070-b13c-cc2668200475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025601744423837368130350739600292153036777663984749012349423310275133266440 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1025601744423837368130350739600292153036777663984749012349423310275133266440
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.96781010066119751850234263947723295568033653066564668308252992802152673241832
Short name T440
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.69 seconds
Started Oct 29 12:30:48 PM PDT 23
Finished Oct 29 12:33:52 PM PDT 23
Peak memory 201240 kb
Host smart-2d46f440-b23b-4b10-8dea-c73267570429
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96781010066119751850234263947723295568033653066564668308252992802152673241832 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.96781010066119751850234263947723295568033653066564668308252992
802152673241832
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.107318347299027694435483432574939560456995430852023670677562280454213171556290
Short name T593
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Oct 29 12:30:50 PM PDT 23
Finished Oct 29 12:30:58 PM PDT 23
Peak memory 201040 kb
Host smart-1a246af9-3ea5-4d84-beb4-863756a66adf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107318347299027694435483432574939560456995430852023670677562280454213171556290 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.10731834729902769443548343257493956045699543085202367067756
2280454213171556290
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.78541473785167403279565319384671604630453568952703927864303810136799383196158
Short name T392
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.43 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 201004 kb
Host smart-b571d832-7634-48b9-a404-1932b880fefc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78541473785167403279565319384671604630453568952703927864303810136799383196158 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.7854147378516740327956531938467160463045356895270392786430381013
6799383196158
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.98024730101096911716962423880783431992798111441451914405874751419174266068903
Short name T327
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 29 12:30:44 PM PDT 23
Finished Oct 29 12:30:49 PM PDT 23
Peak memory 201000 kb
Host smart-0a4004b8-2136-4a62-8ed4-83774530f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98024730101096911716962423880783431992798111441451914405874751419174266068903 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.98024730101096911716962423880783431992798111441451914405874751419174266068903
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.41253079062855141198334076014415328415651561489815782286803086745455751415532
Short name T512
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 29 12:30:48 PM PDT 23
Finished Oct 29 12:30:53 PM PDT 23
Peak memory 201056 kb
Host smart-070de99c-5f2e-41c5-9206-5795c14e3b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41253079062855141198334076014415328415651561489815782286803086745455751415532 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.41253079062855141198334076014415328415651561489815782286803086745455751415532
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2990821170067082721046418000966676986340107744413474454574575595661807103310
Short name T192
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 29 12:30:56 PM PDT 23
Finished Oct 29 12:31:00 PM PDT 23
Peak memory 200940 kb
Host smart-af2adcf8-1984-47e6-bc1d-8c43e153e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990821170067082721046418000966676986340107744413474454574575595661807103310 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2990821170067082721046418000966676986340107744413474454574575595661807103310
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.88319780807526759809426158731806388159470201291315341574996553436619477230171
Short name T610
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.47 seconds
Started Oct 29 12:30:48 PM PDT 23
Finished Oct 29 12:30:53 PM PDT 23
Peak memory 200948 kb
Host smart-a5a57afe-9d9b-4376-a392-ddf55aef4bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88319780807526759809426158731806388159470201291315341574996553436619477230171 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.88319780807526759809426158731806388159470201291315341574996553436619477230171
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.93118597733948217806805493119015109764266627724573393713885182048060682530179
Short name T485
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 29 12:30:44 PM PDT 23
Finished Oct 29 12:30:48 PM PDT 23
Peak memory 200932 kb
Host smart-03436ef4-662d-41de-a11b-30d363aed053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93118597733948217806805493119015109764266627724573393713885182048060682530179 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_smoke.93118597733948217806805493119015109764266627724573393713885182048060682530179
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.111753089238978243914224309726936571337419549859668940944622315542691641998508
Short name T279
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.35 seconds
Started Oct 29 12:30:45 PM PDT 23
Finished Oct 29 12:33:02 PM PDT 23
Peak memory 201304 kb
Host smart-a03497bc-693b-47e2-8821-b4a2eb950066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111753089238978243914224309726936571337419549859668940944622315542691641998508 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.111753089238978243914224309726936571337419549859668940944622315542691641998508
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.82962283391966787673294037730185691868510139467134130341069766734435234296859
Short name T257
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.66 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 200956 kb
Host smart-e64c31c4-8f50-4005-8a45-bb5f9e6597ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82962283391966787673294037730185691868510139467134130341069766734435234296859 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.829622833919667876732940377301856918685101394671341303410697
66734435234296859
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.24933459492022673147200933773998273665198821951760900894650281055080837201010
Short name T473
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:53 PM PDT 23
Peak memory 201020 kb
Host smart-a20b7e04-d65f-4669-ba96-f3a55eab3dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24933459492022673147200933773998273665198821951760900894650281055080837201010 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.24933459492022673147200933773998273665198821951760900894650281055080837201010
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.83495164990409153713189304988491809640879677813156683461491201126260479714164
Short name T554
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 29 12:30:47 PM PDT 23
Finished Oct 29 12:30:53 PM PDT 23
Peak memory 201072 kb
Host smart-c429e372-3220-43d5-93c1-e2d6c74eb903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83495164990409153713189304988491809640879677813156683461491201126260479714164 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.83495164990409153713189304988491809640879677813156683461491201126260479714164
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.59333018036896210917025631465383700891350113253794035055838176200342447854640
Short name T194
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.43 seconds
Started Oct 29 12:30:42 PM PDT 23
Finished Oct 29 12:33:47 PM PDT 23
Peak memory 201272 kb
Host smart-6b2ebb0d-bf85-4d6d-be9d-24e9447c1638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59333018036896210917025631465383700891350113253794035055838176200342447854640 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.59333018036896210917025631465383700891350113253794035055838176
200342447854640
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.22747377182745806971271159769778630838981743804296462660304090401727702036148
Short name T17
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 29 12:30:45 PM PDT 23
Finished Oct 29 12:30:53 PM PDT 23
Peak memory 201016 kb
Host smart-ccd4511a-e0e6-4502-8b32-6769f9358719
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22747377182745806971271159769778630838981743804296462660304090401727702036148 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.227473771827458069712711597697786308389817438042964626603040
90401727702036148
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.76601945506452498842789060317987963591487730466318610675771890029386220132308
Short name T516
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Oct 29 12:30:52 PM PDT 23
Finished Oct 29 12:30:59 PM PDT 23
Peak memory 201144 kb
Host smart-7ac9feea-93d1-461d-af3e-32e3996d413f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76601945506452498842789060317987963591487730466318610675771890029386220132308 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.7660194550645249884278906031798796359148773046631861067577189002
9386220132308
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.65180719361721443468715904814648635905148208109116009265941338126197306564718
Short name T503
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201024 kb
Host smart-4030de9c-9488-490b-957c-2d6bbd3bfc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65180719361721443468715904814648635905148208109116009265941338126197306564718 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.65180719361721443468715904814648635905148208109116009265941338126197306564718
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.104691031524401884835796222650277360390408869280005111111991761032703178674004
Short name T415
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Oct 29 12:30:56 PM PDT 23
Finished Oct 29 12:31:01 PM PDT 23
Peak memory 201012 kb
Host smart-afc3f436-e1c5-4483-b00d-39c782a29ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104691031524401884835796222650277360390408869280005111111991761032703178674004 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.104691031524401884835796222650277360390408869280005111111991761032703178674004
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.37642875504494432164968593642394215571123803468099458899734864661524670987180
Short name T165
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 29 12:30:56 PM PDT 23
Finished Oct 29 12:31:00 PM PDT 23
Peak memory 200940 kb
Host smart-41508e68-f7bc-4cba-8b87-41b3dea3c8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37642875504494432164968593642394215571123803468099458899734864661524670987180 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.37642875504494432164968593642394215571123803468099458899734864661524670987180
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.5258640187671811189656156748958726517642814736128584347660064206005854297710
Short name T570
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 29 12:30:51 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 201048 kb
Host smart-c9180472-c04f-47f8-98dc-f3d10da25e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5258640187671811189656156748958726517642814736128584347660064206005854297710 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.5258640187671811189656156748958726517642814736128584347660064206005854297710
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.62408352123455543151373061878559889521013340105816994611599614831551522413244
Short name T199
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 29 12:30:46 PM PDT 23
Finished Oct 29 12:30:50 PM PDT 23
Peak memory 200908 kb
Host smart-a95bdd92-6dd1-481e-8a9d-13f06f358685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62408352123455543151373061878559889521013340105816994611599614831551522413244 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_smoke.62408352123455543151373061878559889521013340105816994611599614831551522413244
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.76633368585333415428309535550153147092209366547515073271678557734541947746072
Short name T585
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.8 seconds
Started Oct 29 12:30:50 PM PDT 23
Finished Oct 29 12:33:09 PM PDT 23
Peak memory 201284 kb
Host smart-0a18047a-f5a4-4ba8-a79f-904beb6bad54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76633368585333415428309535550153147092209366547515073271678557734541947746072 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.76633368585333415428309535550153147092209366547515073271678557734541947746072
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.73927752527607831252415063465453453260153225000581712101135093744387885005227
Short name T49
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Oct 29 12:30:43 PM PDT 23
Finished Oct 29 12:30:48 PM PDT 23
Peak memory 201040 kb
Host smart-d8b3be75-0104-4c57-9a45-84e81b990f80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73927752527607831252415063465453453260153225000581712101135093744387885005227 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.739277525276078312524150634654534532601532250005817121011350
93744387885005227
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.12482497854106616238523105775207654364684076102053951404743852575434354558060
Short name T587
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 29 12:30:47 PM PDT 23
Finished Oct 29 12:30:51 PM PDT 23
Peak memory 201140 kb
Host smart-fb9d5ff1-e882-4ff8-92ed-dbe1beccab62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482497854106616238523105775207654364684076102053951404743852575434354558060 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.12482497854106616238523105775207654364684076102053951404743852575434354558060
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.24828437741305056138102801953442058958802113835938467191258295552230905548901
Short name T526
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 29 12:30:51 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 201048 kb
Host smart-98998e28-0845-4712-a3f6-ed272736aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24828437741305056138102801953442058958802113835938467191258295552230905548901 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.24828437741305056138102801953442058958802113835938467191258295552230905548901
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.56925822361397202892638676740623553428223953837060083430015397868167827780042
Short name T340
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.23 seconds
Started Oct 29 12:30:45 PM PDT 23
Finished Oct 29 12:33:47 PM PDT 23
Peak memory 201712 kb
Host smart-c665d612-47b0-43ce-8080-b9d6f9f55a68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56925822361397202892638676740623553428223953837060083430015397868167827780042 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.56925822361397202892638676740623553428223953837060083430015397
868167827780042
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.55518839862815007195551573726456529866306493964780894933333999522726056856871
Short name T289
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 201348 kb
Host smart-3904843d-e378-4d10-bee6-e9f9fe735d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55518839862815007195551573726456529866306493964780894933333999522726056856871 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.555188398628150071955515737264565298663064939647808949333339
99522726056856871
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.32437241738352864744732081928301277814405262126123072313832779167413763412934
Short name T609
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 29 12:30:50 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201004 kb
Host smart-9b81353d-6b89-474e-b556-d4b1bdb33819
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32437241738352864744732081928301277814405262126123072313832779167413763412934 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.3243724173835286474473208192830127781440526212612307231383277916
7413763412934
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.105036861748078641455718166866304831125096637109540855556681786800879386240085
Short name T265
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.6 seconds
Started Oct 29 12:30:52 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201140 kb
Host smart-a7070c95-5637-4f3d-b712-f960c926ade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105036861748078641455718166866304831125096637109540855556681786800879386240085 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.105036861748078641455718166866304831125096637109540855556681786800879386240085
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.60889524866792750999509360788415802339195130371932135896909419861147747713763
Short name T177
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 29 12:30:45 PM PDT 23
Finished Oct 29 12:30:50 PM PDT 23
Peak memory 201004 kb
Host smart-7c56db9e-3403-4d3f-b648-64a5482413c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60889524866792750999509360788415802339195130371932135896909419861147747713763 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.60889524866792750999509360788415802339195130371932135896909419861147747713763
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.13610915757326608576614662424360685501113638646544937880477913953051655550950
Short name T155
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 29 12:30:53 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201100 kb
Host smart-50d9b456-373e-4fdf-b99e-14b4d097c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13610915757326608576614662424360685501113638646544937880477913953051655550950 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.13610915757326608576614662424360685501113638646544937880477913953051655550950
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.90352097591031819369052773336186000313603790274011180442057538094948076995809
Short name T652
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Oct 29 12:30:50 PM PDT 23
Finished Oct 29 12:30:55 PM PDT 23
Peak memory 201160 kb
Host smart-085cba8d-7a93-4e7c-9551-a5648af81478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90352097591031819369052773336186000313603790274011180442057538094948076995809 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.90352097591031819369052773336186000313603790274011180442057538094948076995809
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.51523217011039847023202949072941621368935009845291861683705915340114085088361
Short name T225
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 29 12:30:50 PM PDT 23
Finished Oct 29 12:30:54 PM PDT 23
Peak memory 201092 kb
Host smart-9f0d37c0-3411-4937-8b68-179b6e020483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51523217011039847023202949072941621368935009845291861683705915340114085088361 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_smoke.51523217011039847023202949072941621368935009845291861683705915340114085088361
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.42252700622068124769430207304563156840149282745878409666953256917193568649882
Short name T384
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.83 seconds
Started Oct 29 12:30:49 PM PDT 23
Finished Oct 29 12:33:05 PM PDT 23
Peak memory 201296 kb
Host smart-f89c2750-0d53-4130-ab33-edb91fa71f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42252700622068124769430207304563156840149282745878409666953256917193568649882 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.42252700622068124769430207304563156840149282745878409666953256917193568649882
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.108566904035102295242206661044601355184664150819963138966276544425961265643777
Short name T627
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 29 12:30:51 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 200992 kb
Host smart-89980890-8cb2-4562-8472-89949e5fe867
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108566904035102295242206661044601355184664150819963138966276544425961265643777 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.10856690403510229524220666104460135518466415081996313896627
6544425961265643777
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.7070090186912769003283548089338529353828891510636449775111092489280623163847
Short name T308
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 29 12:31:07 PM PDT 23
Finished Oct 29 12:31:11 PM PDT 23
Peak memory 201048 kb
Host smart-af955abb-a966-4dc1-a134-02c076148b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7070090186912769003283548089338529353828891510636449775111092489280623163847 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.7070090186912769003283548089338529353828891510636449775111092489280623163847
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.106906343024125275806912725483277389628903229781469575150175557684476612319431
Short name T434
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 29 12:31:00 PM PDT 23
Finished Oct 29 12:31:06 PM PDT 23
Peak memory 201100 kb
Host smart-20fbe04a-f47e-4626-899d-86060b951ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106906343024125275806912725483277389628903229781469575150175557684476612319431 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.106906343024125275806912725483277389628903229781469575150175557684476612319431
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.39305658591389768661966198453206486276962533558094904209999843087328157428508
Short name T121
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.85 seconds
Started Oct 29 12:30:47 PM PDT 23
Finished Oct 29 12:33:50 PM PDT 23
Peak memory 201244 kb
Host smart-0b4c6172-26a3-4844-a890-1de270394ed8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39305658591389768661966198453206486276962533558094904209999843087328157428508 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.39305658591389768661966198453206486276962533558094904209999843
087328157428508
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.114585487964385449315307419676472873141380766009905469115108845971746687148208
Short name T413
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.46 seconds
Started Oct 29 12:30:52 PM PDT 23
Finished Oct 29 12:30:59 PM PDT 23
Peak memory 201024 kb
Host smart-ece1fdae-5024-475f-bfea-d19c3c316bc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114585487964385449315307419676472873141380766009905469115108845971746687148208 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.11458548796438544931530741967647287314138076600990546911510
8845971746687148208
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.885649534112564987369046070814883955019497730512454402113495389023505076772
Short name T416
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 29 12:31:00 PM PDT 23
Finished Oct 29 12:31:06 PM PDT 23
Peak memory 201052 kb
Host smart-3c8a34f4-c440-41e8-9910-afc3d005dc4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885649534112564987369046070814883955019497730512454402113495389023505076772 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.885649534112564987369046070814883955019497730512454402113495389023505076772
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.60574123995877323221123596063203588369925001137758744958728665275034982052033
Short name T597
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Oct 29 12:30:51 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 200996 kb
Host smart-d7f06564-36e6-446d-9ce8-09b4dd21703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60574123995877323221123596063203588369925001137758744958728665275034982052033 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.60574123995877323221123596063203588369925001137758744958728665275034982052033
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.49883704598992586030407026468377732045744346818082502782359618883017712089555
Short name T502
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.66 seconds
Started Oct 29 12:30:47 PM PDT 23
Finished Oct 29 12:30:52 PM PDT 23
Peak memory 201096 kb
Host smart-bd26dd05-72c2-40ba-98c3-80d24db14263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49883704598992586030407026468377732045744346818082502782359618883017712089555 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.49883704598992586030407026468377732045744346818082502782359618883017712089555
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.54431685966647027899434454254724280446663828613842884151586161205598920054630
Short name T182
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.7 seconds
Started Oct 29 12:30:53 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201100 kb
Host smart-ed9bd3f0-e303-4447-bff9-b42f75a6205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54431685966647027899434454254724280446663828613842884151586161205598920054630 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.54431685966647027899434454254724280446663828613842884151586161205598920054630
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.27539837602373533846097672786174961243300285789618293837451621338973503512029
Short name T669
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Oct 29 12:30:51 PM PDT 23
Finished Oct 29 12:30:56 PM PDT 23
Peak memory 201000 kb
Host smart-3497a55c-9fce-4cab-a27b-5259540e8a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27539837602373533846097672786174961243300285789618293837451621338973503512029 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.27539837602373533846097672786174961243300285789618293837451621338973503512029
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.92648012790872322318065150311672774337642304526384047070977031857738761616231
Short name T664
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Oct 29 12:30:53 PM PDT 23
Finished Oct 29 12:30:57 PM PDT 23
Peak memory 201064 kb
Host smart-e161bf76-e454-4147-8ff8-ba89402d2c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92648012790872322318065150311672774337642304526384047070977031857738761616231 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_smoke.92648012790872322318065150311672774337642304526384047070977031857738761616231
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.56940392736314531319928465814644682171464457579698065303217412196186029437788
Short name T25
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.35 seconds
Started Oct 29 12:30:54 PM PDT 23
Finished Oct 29 12:33:12 PM PDT 23
Peak memory 201284 kb
Host smart-cacb5669-ff34-4446-9167-fdbab1992a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56940392736314531319928465814644682171464457579698065303217412196186029437788 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.56940392736314531319928465814644682171464457579698065303217412196186029437788
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.107351128513137675478975657373516514399247067161852942187630261649074723313581
Short name T18
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 29 12:31:01 PM PDT 23
Finished Oct 29 12:31:06 PM PDT 23
Peak memory 201044 kb
Host smart-841f5187-2f28-4706-9645-4bf86259f23c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107351128513137675478975657373516514399247067161852942187630261649074723313581 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.10735112851313767547897565737351651439924706716185294218763
0261649074723313581
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.60910218254149799911668898055468306091479814542486755024902903499369131229079
Short name T159
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.75 seconds
Started Oct 29 12:31:25 PM PDT 23
Finished Oct 29 12:31:30 PM PDT 23
Peak memory 201320 kb
Host smart-ba370325-cb40-4dd6-84fa-a3ffc8dfa172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60910218254149799911668898055468306091479814542486755024902903499369131229079 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.60910218254149799911668898055468306091479814542486755024902903499369131229079
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.109884619332420869292151012272537943943554696333776678863720355989880975712341
Short name T244
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 29 12:31:06 PM PDT 23
Finished Oct 29 12:31:12 PM PDT 23
Peak memory 201068 kb
Host smart-78e45da3-ae86-444d-95ba-3440236f88f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109884619332420869292151012272537943943554696333776678863720355989880975712341 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.109884619332420869292151012272537943943554696333776678863720355989880975712341
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.64334579569248531807761663492617521625138537004028288313345804262178311206725
Short name T629
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.37 seconds
Started Oct 29 12:31:07 PM PDT 23
Finished Oct 29 12:34:13 PM PDT 23
Peak memory 201244 kb
Host smart-06df0850-db76-4f0e-9225-f88d2eb48438
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64334579569248531807761663492617521625138537004028288313345804262178311206725 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.64334579569248531807761663492617521625138537004028288313345804
262178311206725
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.62207517057087220016168424254780402064661494895310356837045824549461973000740
Short name T575
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.56 seconds
Started Oct 29 12:31:07 PM PDT 23
Finished Oct 29 12:31:15 PM PDT 23
Peak memory 201044 kb
Host smart-ac37b381-157b-41b7-adf8-3463b39b3ec5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62207517057087220016168424254780402064661494895310356837045824549461973000740 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.622075170570872200161684242547804020646614948953103568370458
24549461973000740
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.93818719240760789248849512099277161785377228516611383561285739108177785435357
Short name T474
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Oct 29 12:31:07 PM PDT 23
Finished Oct 29 12:31:13 PM PDT 23
Peak memory 201000 kb
Host smart-0add5ffc-de8a-47d1-8dd0-035616e9edbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93818719240760789248849512099277161785377228516611383561285739108177785435357 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.9381871924076078924884951209927716178537722851661138356128573910
8177785435357
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.13344350516680938254126615491846717412678739259094049823391523170472163935867
Short name T404
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 29 12:31:06 PM PDT 23
Finished Oct 29 12:31:11 PM PDT 23
Peak memory 201016 kb
Host smart-4b019254-0adf-487b-af5e-4ab45dfee6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13344350516680938254126615491846717412678739259094049823391523170472163935867 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.13344350516680938254126615491846717412678739259094049823391523170472163935867
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3138316083255755086147919345145991920597046944519608173104825945911674720440
Short name T478
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 29 12:31:09 PM PDT 23
Finished Oct 29 12:31:14 PM PDT 23
Peak memory 201080 kb
Host smart-acf697c4-a804-4406-a975-14acc3419310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138316083255755086147919345145991920597046944519608173104825945911674720440 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3138316083255755086147919345145991920597046944519608173104825945911674720440
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.24514138450029830283237023566269394209248167256427165656722504513996483106425
Short name T247
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Oct 29 12:31:09 PM PDT 23
Finished Oct 29 12:31:13 PM PDT 23
Peak memory 200952 kb
Host smart-32b93e70-a1b1-4690-8169-ba29e6c2ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24514138450029830283237023566269394209248167256427165656722504513996483106425 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.24514138450029830283237023566269394209248167256427165656722504513996483106425
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.23516110120304989204713233516372423875290162275568310698224266923856106365755
Short name T368
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.5 seconds
Started Oct 29 12:31:08 PM PDT 23
Finished Oct 29 12:31:13 PM PDT 23
Peak memory 200988 kb
Host smart-9c35cad3-733c-42e3-ade9-9cfbf59c2bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23516110120304989204713233516372423875290162275568310698224266923856106365755 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.23516110120304989204713233516372423875290162275568310698224266923856106365755
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.54982031053495978357693361094891031098232197638834217517516103847324457188192
Short name T335
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 29 12:31:07 PM PDT 23
Finished Oct 29 12:31:11 PM PDT 23
Peak memory 200956 kb
Host smart-478f28e1-84d1-4bbe-bd02-b84d23d059d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54982031053495978357693361094891031098232197638834217517516103847324457188192 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_smoke.54982031053495978357693361094891031098232197638834217517516103847324457188192
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.89392323148604352539582474417413576278036082721123772713518609921802305440751
Short name T32
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.89 seconds
Started Oct 29 12:31:19 PM PDT 23
Finished Oct 29 12:33:37 PM PDT 23
Peak memory 201300 kb
Host smart-5b42dd80-778f-4b29-be51-fdd36241eac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89392323148604352539582474417413576278036082721123772713518609921802305440751 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.89392323148604352539582474417413576278036082721123772713518609921802305440751
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.83232245285607522935277305379478138847316236442818331004007479640583824135651
Short name T324
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 29 12:31:08 PM PDT 23
Finished Oct 29 12:31:13 PM PDT 23
Peak memory 200992 kb
Host smart-63b90cfd-5297-48c4-b8e2-a297e016a139
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83232245285607522935277305379478138847316236442818331004007479640583824135651 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.832322452856075229352773053794781388473162364428183310040074
79640583824135651
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.114700805961692914572500986280767072244216089994525680459104013002472092554144
Short name T631
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Oct 29 12:27:56 PM PDT 23
Finished Oct 29 12:28:01 PM PDT 23
Peak memory 201052 kb
Host smart-ac8e18aa-7391-4267-aefc-789773afcafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114700805961692914572500986280767072244216089994525680459104013002472092554144 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.114700805961692914572500986280767072244216089994525680459104013002472092554144
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.79815541268874325808592530853606175011991682064307227615440335056905228152404
Short name T636
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.52 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:16 PM PDT 23
Peak memory 201056 kb
Host smart-a0da618b-4b0e-40d8-b99e-f39ad4a43353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79815541268874325808592530853606175011991682064307227615440335056905228152404 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.79815541268874325808592530853606175011991682064307227615440335056905228152404
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.30454529184490815010756217553662298965439323318816895220974267594209220862947
Short name T566
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.19 seconds
Started Oct 29 12:28:15 PM PDT 23
Finished Oct 29 12:31:19 PM PDT 23
Peak memory 201236 kb
Host smart-44f0f874-38fc-471d-bdcf-e29b8e9ed191
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30454529184490815010756217553662298965439323318816895220974267594209220862947 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.304545291844908150107562175536622989654393233188168952209742675
94209220862947
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.77231866170931123662382028380088700530872742458435446962036830178123465486907
Short name T558
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.47 seconds
Started Oct 29 12:27:53 PM PDT 23
Finished Oct 29 12:28:05 PM PDT 23
Peak memory 201060 kb
Host smart-7fe4afc1-46b6-4e03-931d-d23bcc2f7ad1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77231866170931123662382028380088700530872742458435446962036830178123465486907 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.7723186617093112366238202838008870053087274245843544696203683
0178123465486907
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.98373792079643476173701290827497969267986533393001756450310055803962949534256
Short name T447
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 29 12:28:15 PM PDT 23
Finished Oct 29 12:28:21 PM PDT 23
Peak memory 200992 kb
Host smart-87b931fb-2f2f-4c67-a625-99370ed5d148
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98373792079643476173701290827497969267986533393001756450310055803962949534256 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.98373792079643476173701290827497969267986533393001756450310055803962949534256
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.51363512638945188706680474109539305988231835235442444543523132266898470204413
Short name T361
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.79 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:28:09 PM PDT 23
Peak memory 201032 kb
Host smart-ab60105b-fed2-47ce-a6fa-b60925c40449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51363512638945188706680474109539305988231835235442444543523132266898470204413 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.51363512638945188706680474109539305988231835235442444543523132266898470204413
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.5154019093916902879930933881986631008489140480397855386541312398028564415056
Short name T300
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:28:09 PM PDT 23
Peak memory 201064 kb
Host smart-03aa1d5c-1a84-4824-9222-16d404c406d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5154019093916902879930933881986631008489140480397855386541312398028564415056 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.5154019093916902879930933881986631008489140480397855386541312398028564415056
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.51157739636151017954769556648101076216352043954863411089395249686051898047944
Short name T537
Test name
Test status
Simulation time 2074566504 ps
CPU time 4.01 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:15 PM PDT 23
Peak memory 200972 kb
Host smart-7cbee1c3-b948-47c8-ba11-48cb8c7e871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51157739636151017954769556648101076216352043954863411089395249686051898047944 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.51157739636151017954769556648101076216352043954863411089395249686051898047944
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.83922544212832884997265907395530805282677521070584473735258117734540438420660
Short name T258
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:28:09 PM PDT 23
Peak memory 201012 kb
Host smart-4d6552ea-d24c-43ca-b276-2100a142df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83922544212832884997265907395530805282677521070584473735258117734540438420660 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.83922544212832884997265907395530805282677521070584473735258117734540438420660
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.93496493071820176487056525438586695159874542334527367174075080807396074168277
Short name T183
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Oct 29 12:27:49 PM PDT 23
Finished Oct 29 12:27:53 PM PDT 23
Peak memory 200928 kb
Host smart-5c18b1e7-5fde-4a2e-a1e2-5c10c0571efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93496493071820176487056525438586695159874542334527367174075080807396074168277 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_smoke.93496493071820176487056525438586695159874542334527367174075080807396074168277
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.91669293245533317764364983677553823224701731160052104861568939085874627720730
Short name T385
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.3 seconds
Started Oct 29 12:28:08 PM PDT 23
Finished Oct 29 12:30:28 PM PDT 23
Peak memory 201280 kb
Host smart-0449e4b9-0abc-4e9e-9e6a-c35228b83652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91669293245533317764364983677553823224701731160052104861568939085874627720730 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.91669293245533317764364983677553823224701731160052104861568939085874627720730
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.76304785451185432569890245612118104456623355242001792951141833123546181364168
Short name T291
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:12 PM PDT 23
Peak memory 201044 kb
Host smart-029fe47e-9122-427a-b1fc-502be093f161
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76304785451185432569890245612118104456623355242001792951141833123546181364168 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.7630478545118543256989024561211810445662335524200179295114183
3123546181364168
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.67845246806892581845339173856378207321417837156487891575087776922430499269669
Short name T207
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 29 12:28:32 PM PDT 23
Finished Oct 29 12:28:37 PM PDT 23
Peak memory 201056 kb
Host smart-805c3285-3b75-4b35-9c21-edd8263511c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67845246806892581845339173856378207321417837156487891575087776922430499269669 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.67845246806892581845339173856378207321417837156487891575087776922430499269669
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.10106125484658433070765599900088754909235135774912411498466559581336908572386
Short name T98
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 29 12:28:00 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 201084 kb
Host smart-1875f5b6-fc79-4451-a6aa-958dac6d0c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10106125484658433070765599900088754909235135774912411498466559581336908572386 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.10106125484658433070765599900088754909235135774912411498466559581336908572386
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.58174025564235542187539760038387761948598959176479937986429704865932084030940
Short name T422
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.32 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:32:18 PM PDT 23
Peak memory 200872 kb
Host smart-480c457b-6dec-43dd-9b89-4cbf1d6631bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58174025564235542187539760038387761948598959176479937986429704865932084030940 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.581740255642355421875397600383877619485989591764799379864297048
65932084030940
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.85734939223605025155478085922088910100435733275147510017447944885672992161314
Short name T635
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.61 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:15 PM PDT 23
Peak memory 201028 kb
Host smart-0487f76b-879b-4b95-a779-50b37452c62d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85734939223605025155478085922088910100435733275147510017447944885672992161314 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.8573493922360502515547808592208891010043573327514751001744794
4885672992161314
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.73526960204954703070822523352782996851857750407344380747378864368550795523597
Short name T482
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 201008 kb
Host smart-72d7cb04-357b-4c4c-9562-e67197f18171
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73526960204954703070822523352782996851857750407344380747378864368550795523597 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.73526960204954703070822523352782996851857750407344380747378864368550795523597
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.109180457331100685044918459466463769930292732966146212534192314684888584101431
Short name T449
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 29 12:28:03 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 201028 kb
Host smart-c78d8d07-f287-4e9e-b590-5ab8b4a5eea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109180457331100685044918459466463769930292732966146212534192314684888584101431 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.109180457331100685044918459466463769930292732966146212534192314684888584101431
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.45423904576114641503804505039015433554104646095702940408612925183076347864731
Short name T63
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 29 12:29:04 PM PDT 23
Finished Oct 29 12:29:09 PM PDT 23
Peak memory 200824 kb
Host smart-bf3ad04b-b03c-4a5c-8650-df26972c1bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45423904576114641503804505039015433554104646095702940408612925183076347864731 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.45423904576114641503804505039015433554104646095702940408612925183076347864731
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.65876608871714372577349558623437722622045360299334775711920535172625622420837
Short name T350
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.87 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:11 PM PDT 23
Peak memory 200972 kb
Host smart-0456ad3a-4a65-483f-aaf7-d8e185272755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65876608871714372577349558623437722622045360299334775711920535172625622420837 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.65876608871714372577349558623437722622045360299334775711920535172625622420837
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.91432196109845035710084276257617082193774388389494638209259219454453492839679
Short name T376
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.76 seconds
Started Oct 29 12:28:00 PM PDT 23
Finished Oct 29 12:28:05 PM PDT 23
Peak memory 201024 kb
Host smart-1a304752-cafb-459b-bdc4-c909dd34b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91432196109845035710084276257617082193774388389494638209259219454453492839679 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.91432196109845035710084276257617082193774388389494638209259219454453492839679
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.9016221744129500240455603157332479694036178008589730960052413736228661420262
Short name T104
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:11 PM PDT 23
Peak memory 200936 kb
Host smart-3f473b3c-0f49-40ba-b731-7dd255df3627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9016221744129500240455603157332479694036178008589730960052413736228661420262 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sysrst_ctrl_smoke.9016221744129500240455603157332479694036178008589730960052413736228661420262
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.94539463300340619652939107568030527499056744308370811653134611914619395221997
Short name T132
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.74 seconds
Started Oct 29 12:28:13 PM PDT 23
Finished Oct 29 12:30:32 PM PDT 23
Peak memory 200244 kb
Host smart-ff49e44d-26c3-404f-a49e-707cc981b53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94539463300340619652939107568030527499056744308370811653134611914619395221997 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.94539463300340619652939107568030527499056744308370811653134611914619395221997
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.98683186274532672614836935131953490513112128406128180493460612087717773204347
Short name T662
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.87 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:16 PM PDT 23
Peak memory 200996 kb
Host smart-3985dbde-ad61-482f-8aab-23bef5668a1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98683186274532672614836935131953490513112128406128180493460612087717773204347 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.9868318627453267261483693513195349051311212840612818049346061
2087717773204347
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.798856984499308475842542169383314351524932659731205273974147937097063513219
Short name T203
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.79 seconds
Started Oct 29 12:29:07 PM PDT 23
Finished Oct 29 12:29:11 PM PDT 23
Peak memory 200876 kb
Host smart-fa648ad5-6670-4242-937f-dfbe1efd112b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798856984499308475842542169383314351524932659731205273974147937097063513219 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.798856984499308475842542169383314351524932659731205273974147937097063513219
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.80102739228970647730344277380535083236378651104853571367028700738028858726999
Short name T579
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.52 seconds
Started Oct 29 12:27:59 PM PDT 23
Finished Oct 29 12:28:06 PM PDT 23
Peak memory 201108 kb
Host smart-c7c4c13b-01ed-43cc-a7fe-4acfc8f4f4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80102739228970647730344277380535083236378651104853571367028700738028858726999 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.80102739228970647730344277380535083236378651104853571367028700738028858726999
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.37868092856904778427502339873702528727491478588876303661011004342260299946661
Short name T128
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.54 seconds
Started Oct 29 12:29:02 PM PDT 23
Finished Oct 29 12:32:07 PM PDT 23
Peak memory 200448 kb
Host smart-6ad67140-0762-459f-9e1f-5675b8819111
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868092856904778427502339873702528727491478588876303661011004342260299946661 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.378680928569047784275023398737025287274914785888763036610110043
42260299946661
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.67487155170818495749940208291818534179039764548128797366650494594486428272036
Short name T147
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.53 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:14 PM PDT 23
Peak memory 201040 kb
Host smart-2d509444-c751-4209-a601-7c510e02f1c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67487155170818495749940208291818534179039764548128797366650494594486428272036 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.6748715517081849574994020829181853417903976454812879736665049
4594486428272036
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.89852119731304192817436524255371763601571907528289197662488595928833401902625
Short name T220
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Oct 29 12:28:02 PM PDT 23
Finished Oct 29 12:28:09 PM PDT 23
Peak memory 200984 kb
Host smart-f9505bee-c90b-4db6-9a42-8c67b63cb3e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89852119731304192817436524255371763601571907528289197662488595928833401902625 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.89852119731304192817436524255371763601571907528289197662488595928833401902625
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.40982570245253383399705281400254760518091675790262314717912889827754618191612
Short name T427
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.75 seconds
Started Oct 29 12:28:06 PM PDT 23
Finished Oct 29 12:28:11 PM PDT 23
Peak memory 201008 kb
Host smart-f2728b52-b814-4a8b-b6fd-2f3b5cd57233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40982570245253383399705281400254760518091675790262314717912889827754618191612 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.40982570245253383399705281400254760518091675790262314717912889827754618191612
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.36603110670340082018190007126430597552551917335613935554194265731935326943246
Short name T393
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 29 12:29:03 PM PDT 23
Finished Oct 29 12:29:08 PM PDT 23
Peak memory 200824 kb
Host smart-304b4c34-7b2c-4952-b7ed-f62ccf83c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36603110670340082018190007126430597552551917335613935554194265731935326943246 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.36603110670340082018190007126430597552551917335613935554194265731935326943246
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.12040732544849007977547029741618859693001694301238136427631078897238054984679
Short name T290
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 29 12:29:03 PM PDT 23
Finished Oct 29 12:29:07 PM PDT 23
Peak memory 200640 kb
Host smart-80223d8d-28de-491d-9d78-3469a593ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12040732544849007977547029741618859693001694301238136427631078897238054984679 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.12040732544849007977547029741618859693001694301238136427631078897238054984679
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.20183665688741477261657593816655295711670148946094754098425005908150781315983
Short name T336
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Oct 29 12:28:03 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 201148 kb
Host smart-58f80812-1ab3-4473-ae3a-4b289bce2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20183665688741477261657593816655295711670148946094754098425005908150781315983 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.20183665688741477261657593816655295711670148946094754098425005908150781315983
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.67144409784112042411777012686262172950014270599318033310587715021964159570126
Short name T158
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:05 PM PDT 23
Peak memory 200908 kb
Host smart-8cd47462-1127-43a5-a4a9-a074789f9010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67144409784112042411777012686262172950014270599318033310587715021964159570126 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_smoke.67144409784112042411777012686262172950014270599318033310587715021964159570126
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.17082903589553251156743532288693278494614621441048728994542198221224091026562
Short name T270
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.35 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:30:28 PM PDT 23
Peak memory 201164 kb
Host smart-8cedba28-98d2-46bd-9b1e-b726ddb93fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17082903589553251156743532288693278494614621441048728994542198221224091026562 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.17082903589553251156743532288693278494614621441048728994542198221224091026562
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.82743940916269877449232777708822000377322989803572847867476542460278763216763
Short name T342
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.85 seconds
Started Oct 29 12:28:03 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 200992 kb
Host smart-01cce034-27a0-4b12-a96b-371993ae1927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82743940916269877449232777708822000377322989803572847867476542460278763216763 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.8274394091626987744923277770882200037732298980357284786747654
2460278763216763
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.110044248009771355750036800956274148537627270370809544418880574778899046582589
Short name T171
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 200164 kb
Host smart-22a97073-0f66-47ca-a622-4bfcf1472205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110044248009771355750036800956274148537627270370809544418880574778899046582589 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.110044248009771355750036800956274148537627270370809544418880574778899046582589
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.111809972107623202341577615367945062839194121501792449478259504317293021031977
Short name T62
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:20 PM PDT 23
Peak memory 200780 kb
Host smart-fee00b55-3279-4f6b-8696-aebc7a57a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111809972107623202341577615367945062839194121501792449478259504317293021031977 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.111809972107623202341577615367945062839194121501792449478259504317293021031977
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.93779799328094054253523086562776342343841272791829546192253788783926234525182
Short name T446
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.21 seconds
Started Oct 29 12:28:14 PM PDT 23
Finished Oct 29 12:31:18 PM PDT 23
Peak memory 201272 kb
Host smart-9fcc7adf-4c22-48cb-a44c-97cbc6363d66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93779799328094054253523086562776342343841272791829546192253788783926234525182 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.937797993280940542535230865627763423438412727918295461922537887
83926234525182
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.62313584832915792514275386754867729625673225829316642897363798721322698652844
Short name T161
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:18 PM PDT 23
Peak memory 201044 kb
Host smart-02d1e997-ab12-4e72-b2b7-a4943eb7097f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62313584832915792514275386754867729625673225829316642897363798721322698652844 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.6231358483291579251427538675486772962567322582931664289736379
8721322698652844
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2212284593842123132173143090227199171010676097485216612325565205920708990798
Short name T136
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Oct 29 12:28:05 PM PDT 23
Finished Oct 29 12:28:13 PM PDT 23
Peak memory 201044 kb
Host smart-b989a92d-2ecc-45a5-ae00-b4f944f80bd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212284593842123132173143090227199171010676097485216612325565205920708990798 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.2212284593842123132173143090227199171010676097485216612325565205920708990798
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.109114556143325136088900405079049342288336000478077906320958673083074702900926
Short name T602
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.77 seconds
Started Oct 29 12:28:01 PM PDT 23
Finished Oct 29 12:28:07 PM PDT 23
Peak memory 201016 kb
Host smart-9a7f357c-cd88-42a1-8214-5d2133cb49d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109114556143325136088900405079049342288336000478077906320958673083074702900926 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.109114556143325136088900405079049342288336000478077906320958673083074702900926
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.15351167947842817820907885608142475163414944040826171855798277763455401221316
Short name T586
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.92 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:28:10 PM PDT 23
Peak memory 201080 kb
Host smart-177e2183-8370-4fb0-b62c-6ef5bf3b1f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15351167947842817820907885608142475163414944040826171855798277763455401221316 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.15351167947842817820907885608142475163414944040826171855798277763455401221316
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.46417381009305509069823450669854187976967576579778886505934064729971819078822
Short name T338
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 29 12:28:05 PM PDT 23
Finished Oct 29 12:28:10 PM PDT 23
Peak memory 200972 kb
Host smart-30ba4e3d-ac56-44a7-b30c-4ac025eb921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46417381009305509069823450669854187976967576579778886505934064729971819078822 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.46417381009305509069823450669854187976967576579778886505934064729971819078822
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.76138229003209116883314844637849331575328864280666166451464536347346828480667
Short name T521
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 29 12:28:21 PM PDT 23
Finished Oct 29 12:28:26 PM PDT 23
Peak memory 200980 kb
Host smart-e179dd7c-a235-4c47-8cd6-b9123ce79d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76138229003209116883314844637849331575328864280666166451464536347346828480667 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.76138229003209116883314844637849331575328864280666166451464536347346828480667
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.3447941183454619604402122015116217163737214775091767669568235853027640652775
Short name T408
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 29 12:28:14 PM PDT 23
Finished Oct 29 12:28:18 PM PDT 23
Peak memory 200808 kb
Host smart-390c5b8f-6220-4a84-8dee-84cd99f178e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447941183454619604402122015116217163737214775091767669568235853027640652775 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sysrst_ctrl_smoke.3447941183454619604402122015116217163737214775091767669568235853027640652775
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.10456868650883560735793713018389329057700689890266196791742564566446805713998
Short name T466
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.21 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:31:30 PM PDT 23
Peak memory 200712 kb
Host smart-93c74301-2385-41b5-865e-8d8fddb20df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10456868650883560735793713018389329057700689890266196791742564566446805713998 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.10456868650883560735793713018389329057700689890266196791742564566446805713998
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.41861382347703892410874538929528984783293007457923987440712486918369587107495
Short name T39
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 29 12:28:23 PM PDT 23
Finished Oct 29 12:28:27 PM PDT 23
Peak memory 201000 kb
Host smart-f2c82565-37f0-46bd-bf58-ebf92a7411ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41861382347703892410874538929528984783293007457923987440712486918369587107495 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.41861382347703892410874538929528984783293007457923987440712486918369587107495
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.26945809639160117061121654092001089445906392182241189990886433959506867982238
Short name T475
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:20 PM PDT 23
Peak memory 200780 kb
Host smart-f1ef2062-df7a-4a87-94b5-28877d2b76fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26945809639160117061121654092001089445906392182241189990886433959506867982238 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.26945809639160117061121654092001089445906392182241189990886433959506867982238
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.57893134658652798959458336083566093362092784088490967529962337685655159687217
Short name T476
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.77 seconds
Started Oct 29 12:28:28 PM PDT 23
Finished Oct 29 12:31:32 PM PDT 23
Peak memory 201284 kb
Host smart-5bd26be6-ec9e-4e67-a269-b9d569e87e9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57893134658652798959458336083566093362092784088490967529962337685655159687217 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.578931346586527989594583360835660933620927840884909675299623376
85655159687217
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.92022633484203599129457382661175108945803725179383927627281226308690607462959
Short name T517
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Oct 29 12:28:07 PM PDT 23
Finished Oct 29 12:28:19 PM PDT 23
Peak memory 201024 kb
Host smart-0a6bcd25-8878-4331-93a5-e0c4a1ddc4e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92022633484203599129457382661175108945803725179383927627281226308690607462959 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.9202263348420359912945738266117510894580372517938392762728122
6308690607462959
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2123638000840093034751698332061179732820143403407787918053115841550362834729
Short name T235
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 29 12:28:31 PM PDT 23
Finished Oct 29 12:28:37 PM PDT 23
Peak memory 200980 kb
Host smart-daede1ce-9a2b-44b5-92c8-3a7e49a80271
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123638000840093034751698332061179732820143403407787918053115841550362834729 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.2123638000840093034751698332061179732820143403407787918053115841550362834729
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.27264430616139828540726254954060457852011675692277641642425202001656924935286
Short name T162
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.77 seconds
Started Oct 29 12:28:09 PM PDT 23
Finished Oct 29 12:28:16 PM PDT 23
Peak memory 200988 kb
Host smart-2aa8a3d0-5ae0-486a-b412-354f6317396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27264430616139828540726254954060457852011675692277641642425202001656924935286 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.27264430616139828540726254954060457852011675692277641642425202001656924935286
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.18100360941822250094020682643925821675301056996441457593316356552843847184678
Short name T206
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 29 12:28:15 PM PDT 23
Finished Oct 29 12:28:20 PM PDT 23
Peak memory 201004 kb
Host smart-3ac63b55-a583-4190-a209-08943b3c8fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18100360941822250094020682643925821675301056996441457593316356552843847184678 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.18100360941822250094020682643925821675301056996441457593316356552843847184678
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.21800422565255174387578305878323506131917303495621671771961014252211341439143
Short name T154
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Oct 29 12:28:04 PM PDT 23
Finished Oct 29 12:28:08 PM PDT 23
Peak memory 200988 kb
Host smart-8c3ab2ca-a2a8-49c1-a575-aa99fddfc42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21800422565255174387578305878323506131917303495621671771961014252211341439143 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.21800422565255174387578305878323506131917303495621671771961014252211341439143
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.59372801265243582410968501005396671255774162101038156379324072726166022817366
Short name T578
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.75 seconds
Started Oct 29 12:28:13 PM PDT 23
Finished Oct 29 12:28:19 PM PDT 23
Peak memory 200144 kb
Host smart-8c32262d-0864-48eb-9999-b6c8ec6a8951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59372801265243582410968501005396671255774162101038156379324072726166022817366 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.59372801265243582410968501005396671255774162101038156379324072726166022817366
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.71570774501400169636690598560684188648476059324058212361151410064375888724553
Short name T248
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 29 12:29:14 PM PDT 23
Finished Oct 29 12:29:18 PM PDT 23
Peak memory 200592 kb
Host smart-c608bac3-5eb1-4178-8a95-c03b591e2678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71570774501400169636690598560684188648476059324058212361151410064375888724553 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_smoke.71570774501400169636690598560684188648476059324058212361151410064375888724553
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.23698838167063327789162531033722096534774839687308452738893365350082423265495
Short name T214
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.78 seconds
Started Oct 29 12:28:29 PM PDT 23
Finished Oct 29 12:30:45 PM PDT 23
Peak memory 201320 kb
Host smart-27ce4725-7912-44ad-9735-fd05ce372dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23698838167063327789162531033722096534774839687308452738893365350082423265495 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.23698838167063327789162531033722096534774839687308452738893365350082423265495
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.86466535397668596144200531963015072793120024215570314134567357115664660714948
Short name T626
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 29 12:28:26 PM PDT 23
Finished Oct 29 12:28:31 PM PDT 23
Peak memory 200992 kb
Host smart-e243b2e8-9919-475a-bbef-b8726af83d99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86466535397668596144200531963015072793120024215570314134567357115664660714948 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.8646653539766859614420053196301507279312002421557031413456735
7115664660714948
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest
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