Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T19
1	0	Covered	T17,T22,T19
1	1	Covered	T19,T20,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T19
1	0	Covered	T19,T20,T28
1	1	Covered	T17,T22,T19

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	125837	0	0
SrcPulseCheck_M	2147483647	127146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	125837
T19	1054608	0
T22	5488664	27
T23	5488664	27
T24	1078472	2
T25	5488664	27
T26	1632376	0
T27	0	27
T28	0	15
T29	0	27
T31	0	27
T33	0	15
T35	1372166	27
T36	1011862	5
T41	1130928	0
T42	1110688	0
T43	1110688	0
T44	951752	0
T45	263652	0
T97	352820	16
T98	352820	16
T99	0	16
T100	141936	0
T105	0	16
T106	0	16
T107	0	16
T108	0	16
T109	0	16
T110	0	16
T111	0	16
T112	226534	0
T113	233180	0
T114	233180	0
T115	497384	0
T116	294458	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	127146
T19	1054608	0
T22	5488664	27
T23	5488664	27
T24	1078472	2
T25	5488664	27
T26	1632376	0
T27	0	27
T28	0	15
T29	0	27
T31	0	27
T33	0	15
T35	1372166	27
T36	1011862	5
T41	1130928	0
T42	1110688	0
T43	1110688	0
T44	951752	0
T45	263652	0
T97	352820	16
T98	352820	16
T99	0	16
T100	506	0
T105	0	16
T106	0	16
T107	0	16
T108	0	16
T109	0	16
T110	0	16
T111	0	16
T112	226534	0
T113	233180	0
T114	233180	0
T115	497384	0
T116	294458	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T17,T22,T23
1	1	Covered	T95,T73,T74

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T95,T73,T74
1	1	Covered	T17,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1932	0	0
SrcPulseCheck_M	754515696	1962	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1932
T17	884	1
T18	817	0
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T39	403	0
T40	414	0
T41	503	0
T72	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1962
T17	247808	1
T18	203230	0
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T39	112864	0
T40	116176	0
T41	140863	0
T72	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T17,T22,T23
1	1	Covered	T95,T73,T74

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T95,T73,T74
1	1	Covered	T17,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1932	0	0
SrcPulseCheck_M	2727417	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1932
T17	247808	1
T18	203230	0
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T39	112864	0
T40	116176	0
T41	140863	0
T72	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1932
T17	884	1
T18	817	0
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T39	403	0
T40	414	0
T41	503	0
T72	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1197
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1238	0	0
SrcPulseCheck_M	754515696	1268	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1238
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1268
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1238	0	0
SrcPulseCheck_M	2727417	1238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1238
T19	130789	2
T20	130789	2
T21	0	2
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1238
T19	1037	2
T20	1037	2
T21	0	2
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	2
T46	0	2
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T95,T73,T74

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T95,T73,T74
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	800	0	0
SrcPulseCheck_M	754515696	830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	800
T19	1037	1
T20	1037	1
T21	0	1
T23	23657	0
T24	479	0
T25	23657	0
T26	817	0
T41	503	0
T42	494	0
T43	494	0
T44	423	0
T45	0	1
T46	0	1
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	830
T19	130789	1
T20	130789	1
T21	0	1
T23	662426	0
T24	134330	0
T25	662426	0
T26	203230	0
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0
T45	0	1
T46	0	1
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T19,T23
1	0	Covered	T22,T19,T23
1	1	Covered	T28,T33,T36

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T19,T23
1	0	Covered	T28,T33,T36
1	1	Covered	T22,T19,T23

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1510	0	0
SrcPulseCheck_M	754515696	1552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1510
T19	1037	1
T20	0	1
T22	23657	8
T23	23657	8
T24	479	0
T25	23657	8
T26	817	0
T27	0	8
T28	0	7
T29	0	8
T31	0	8
T33	0	7
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1552
T19	130789	1
T20	0	1
T22	662426	8
T23	662426	8
T24	134330	1
T25	662426	8
T26	203230	0
T27	0	8
T28	0	7
T29	0	8
T31	0	8
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T42,T43,T28
1	0	Covered	T42,T43,T28
1	1	Covered	T42,T43,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T42,T43,T28
1	0	Covered	T42,T43,T28
1	1	Covered	T42,T43,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	3105	0	0
SrcPulseCheck_M	754515696	3135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	3105
T20	1037	0
T26	817	0
T27	23657	0
T28	17445	20
T29	23657	0
T33	17445	20
T36	0	20
T37	0	20
T42	494	20
T43	494	20
T44	423	0
T118	0	20
T119	0	20
T120	0	20
T121	0	20
T122	403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	3135
T20	130789	0
T26	203230	0
T27	662426	0
T28	488486	20
T29	662426	0
T33	488486	20
T36	0	20
T37	0	20
T42	138342	20
T43	138342	20
T44	118546	0
T118	0	20
T119	0	20
T120	0	20
T121	0	20
T122	112864	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T42,T43,T28
1	0	Covered	T42,T43,T28
1	1	Covered	T42,T43,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T42,T43,T28
1	0	Covered	T42,T43,T28
1	1	Covered	T42,T43,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	3105	0	0
SrcPulseCheck_M	2727417	3105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	3105
T20	130789	0
T26	203230	0
T27	662426	0
T28	488486	20
T29	662426	0
T33	488486	20
T36	0	20
T37	0	20
T42	138342	20
T43	138342	20
T44	118546	0
T118	0	20
T119	0	20
T120	0	20
T121	0	20
T122	112864	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	3105
T20	1037	0
T26	817	0
T27	23657	0
T28	17445	20
T29	23657	0
T33	17445	20
T36	0	20
T37	0	20
T42	494	20
T43	494	20
T44	423	0
T118	0	20
T119	0	20
T120	0	20
T121	0	20
T122	403	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T28,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T28,T33
1	1	Covered	T41,T42,T43

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5170	0	0
SrcPulseCheck_M	754515696	5200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5170
T20	1037	0
T24	479	0
T25	23657	0
T26	817	0
T27	23657	0
T28	17445	41
T33	0	41
T41	503	20
T42	494	1
T43	494	1
T44	423	0
T118	0	1
T123	0	20
T124	0	20
T125	0	20
T126	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5200
T20	130789	0
T24	134330	0
T25	662426	0
T26	203230	0
T27	662426	0
T28	488486	41
T33	0	41
T41	140863	20
T42	138342	1
T43	138342	1
T44	118546	0
T118	0	1
T123	0	20
T124	0	20
T125	0	20
T126	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T28,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T28,T33
1	1	Covered	T41,T42,T43

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5170	0	0
SrcPulseCheck_M	2727417	5170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5170
T20	130789	0
T24	134330	0
T25	662426	0
T26	203230	0
T27	662426	0
T28	488486	41
T33	0	41
T41	140863	20
T42	138342	1
T43	138342	1
T44	118546	0
T118	0	1
T123	0	20
T124	0	20
T125	0	20
T126	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5170
T20	1037	0
T24	479	0
T25	23657	0
T26	817	0
T27	23657	0
T28	17445	41
T33	0	41
T41	503	20
T42	494	1
T43	494	1
T44	423	0
T118	0	1
T123	0	20
T124	0	20
T125	0	20
T126	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T17,T22,T23
1	1	Covered	T41,T28,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T41,T28,T33
1	1	Covered	T17,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5967	0	0
SrcPulseCheck_M	754515696	5997	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5967
T17	884	1
T18	817	0
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T27	0	9
T28	0	46
T39	403	0
T40	414	0
T41	503	20
T42	0	1
T43	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5997
T17	247808	1
T18	203230	0
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T27	0	9
T28	0	46
T39	112864	0
T40	116176	0
T41	140863	20
T42	0	1
T43	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T17,T22,T23
1	1	Covered	T41,T28,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T22,T23
1	0	Covered	T41,T28,T33
1	1	Covered	T17,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5967	0	0
SrcPulseCheck_M	2727417	5967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5967
T17	247808	1
T18	203230	0
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T27	0	9
T28	0	46
T39	112864	0
T40	116176	0
T41	140863	20
T42	0	1
T43	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5967
T17	884	1
T18	817	0
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T27	0	9
T28	0	46
T39	403	0
T40	414	0
T41	503	20
T42	0	1
T43	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T28,T33
1	0	Covered	T41,T28,T33
1	1	Covered	T41,T28,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T28,T33
1	0	Covered	T41,T28,T33
1	1	Covered	T41,T28,T33

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	4925	0	0
SrcPulseCheck_M	754515696	4955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	4925
T20	1037	0
T24	479	0
T25	23657	0
T26	817	0
T27	23657	0
T28	17445	40
T33	0	40
T36	0	40
T41	503	20
T42	494	0
T43	494	0
T44	423	0
T116	0	20
T123	0	20
T124	0	20
T125	0	20
T126	0	20
T127	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	4955
T20	130789	0
T24	134330	0
T25	662426	0
T26	203230	0
T27	662426	0
T28	488486	40
T33	0	40
T36	0	40
T41	140863	20
T42	138342	0
T43	138342	0
T44	118546	0
T116	0	20
T123	0	20
T124	0	20
T125	0	20
T126	0	20
T127	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T28,T33
1	0	Covered	T41,T28,T33
1	1	Covered	T41,T28,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T41,T28,T33
1	0	Covered	T41,T28,T33
1	1	Covered	T41,T28,T33

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	4925	0	0
SrcPulseCheck_M	2727417	4925	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	4925
T20	130789	0
T24	134330	0
T25	662426	0
T26	203230	0
T27	662426	0
T28	488486	40
T33	0	40
T36	0	40
T41	140863	20
T42	138342	0
T43	138342	0
T44	118546	0
T116	0	20
T123	0	20
T124	0	20
T125	0	20
T126	0	20
T127	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	4925
T20	1037	0
T24	479	0
T25	23657	0
T26	817	0
T27	23657	0
T28	17445	40
T33	0	40
T36	0	40
T41	503	20
T42	494	0
T43	494	0
T44	423	0
T116	0	20
T123	0	20
T124	0	20
T125	0	20
T126	0	20
T127	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T26,T28
1	0	Covered	T18,T26,T28
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T26,T28
1	0	Covered	T103,T104,T95
1	1	Covered	T18,T26,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1246	0	0
SrcPulseCheck_M	754515696	1276	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1246
T18	817	1
T19	1037	0
T22	23657	0
T23	23657	0
T24	479	0
T25	23657	0
T26	0	1
T28	0	1
T30	0	1
T32	0	1
T33	0	1
T34	0	1
T36	0	1
T37	0	1
T38	0	1
T39	403	0
T40	414	0
T41	503	0
T42	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1276
T18	203230	1
T19	130789	0
T22	662426	0
T23	662426	0
T24	134330	0
T25	662426	0
T26	0	1
T28	0	1
T30	0	1
T32	0	1
T33	0	1
T34	0	1
T36	0	1
T37	0	1
T38	0	1
T39	112864	0
T40	116176	0
T41	140863	0
T42	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T26,T28
1	0	Covered	T18,T26,T28
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T26,T28
1	0	Covered	T103,T104,T95
1	1	Covered	T18,T26,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1246	0	0
SrcPulseCheck_M	2727417	1246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1246
T18	203230	1
T19	130789	0
T22	662426	0
T23	662426	0
T24	134330	0
T25	662426	0
T26	0	1
T28	0	1
T30	0	1
T32	0	1
T33	0	1
T34	0	1
T36	0	1
T37	0	1
T38	0	1
T39	112864	0
T40	116176	0
T41	140863	0
T42	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1246
T18	817	1
T19	1037	0
T22	23657	0
T23	23657	0
T24	479	0
T25	23657	0
T26	0	1
T28	0	1
T30	0	1
T32	0	1
T33	0	1
T34	0	1
T36	0	1
T37	0	1
T38	0	1
T39	403	0
T40	414	0
T41	503	0
T42	494	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T22,T23
1	0	Covered	T18,T22,T23
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T22,T23
1	0	Covered	T103,T104,T95
1	1	Covered	T18,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1924	0	0
SrcPulseCheck_M	754515696	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1924
T18	817	1
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	0	1
T27	0	9
T28	0	6
T29	0	9
T30	0	1
T39	403	0
T40	414	0
T41	503	0
T42	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1974
T18	203230	1
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	0	1
T27	0	9
T28	0	6
T29	0	9
T30	0	1
T39	112864	0
T40	116176	0
T41	140863	0
T42	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T22,T23
1	0	Covered	T18,T22,T23
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T22,T23
1	0	Covered	T103,T104,T95
1	1	Covered	T18,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1924	0	0
SrcPulseCheck_M	2727417	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1924
T18	203230	1
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	0	1
T27	0	9
T28	0	6
T29	0	9
T30	0	1
T39	112864	0
T40	116176	0
T41	140863	0
T42	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1924
T18	817	1
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	0	1
T27	0	9
T28	0	6
T29	0	9
T30	0	1
T39	403	0
T40	414	0
T41	503	0
T42	494	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1254	0	0
SrcPulseCheck_M	754515696	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1254
T35	23657	0
T36	17445	0
T45	1037	0
T97	627	5
T98	627	5
T99	0	5
T105	0	5
T106	0	5
T107	0	5
T108	0	5
T109	0	5
T110	0	5
T111	0	5
T112	403	0
T113	414	0
T114	414	0
T115	884	0
T116	523	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1289
T35	662426	0
T36	488486	0
T45	130789	0
T97	175783	5
T98	175783	5
T99	0	5
T105	0	5
T106	0	5
T107	0	5
T108	0	5
T109	0	5
T110	0	5
T111	0	5
T112	112864	0
T113	116176	0
T114	116176	0
T115	247808	0
T116	146706	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1259	0	0
SrcPulseCheck_M	2727417	1259	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1259
T35	662426	0
T36	488486	0
T45	130789	0
T97	175783	5
T98	175783	5
T99	0	5
T105	0	5
T106	0	5
T107	0	5
T108	0	5
T109	0	5
T110	0	5
T111	0	5
T112	112864	0
T113	116176	0
T114	116176	0
T115	247808	0
T116	146706	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1259
T35	23657	0
T36	17445	0
T45	1037	0
T97	627	5
T98	627	5
T99	0	5
T105	0	5
T106	0	5
T107	0	5
T108	0	5
T109	0	5
T110	0	5
T111	0	5
T112	403	0
T113	414	0
T114	414	0
T115	884	0
T116	523	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1192	0	0
SrcPulseCheck_M	754515696	1222	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1192
T35	23657	0
T36	17445	0
T45	1037	0
T97	627	3
T98	627	3
T99	0	3
T105	0	3
T106	0	3
T107	0	3
T108	0	3
T109	0	3
T110	0	3
T111	0	3
T112	403	0
T113	414	0
T114	414	0
T115	884	0
T116	523	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1222
T35	662426	0
T36	488486	0
T45	130789	0
T97	175783	3
T98	175783	3
T99	0	3
T105	0	3
T106	0	3
T107	0	3
T108	0	3
T109	0	3
T110	0	3
T111	0	3
T112	112864	0
T113	116176	0
T114	116176	0
T115	247808	0
T116	146706	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T97,T98,T99
1	0	Covered	T97,T98,T99
1	1	Covered	T97,T98,T99

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1192	0	0
SrcPulseCheck_M	2727417	1192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1192
T35	662426	0
T36	488486	0
T45	130789	0
T97	175783	3
T98	175783	3
T99	0	3
T105	0	3
T106	0	3
T107	0	3
T108	0	3
T109	0	3
T110	0	3
T111	0	3
T112	112864	0
T113	116176	0
T114	116176	0
T115	247808	0
T116	146706	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1192
T35	23657	0
T36	17445	0
T45	1037	0
T97	627	3
T98	627	3
T99	0	3
T105	0	3
T106	0	3
T107	0	3
T108	0	3
T109	0	3
T110	0	3
T111	0	3
T112	403	0
T113	414	0
T114	414	0
T115	884	0
T116	523	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T100,T101,T102
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T103,T104,T95
1	1	Covered	T100,T101,T102

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1052	0	0
SrcPulseCheck_M	754515696	1102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1052
T73	0	2
T74	0	2
T95	0	13
T100	506	1
T101	0	1
T102	0	1
T103	0	11
T104	0	11
T128	0	1
T129	0	1
T130	1037	0
T131	1037	0
T132	494	0
T133	884	0
T134	494	0
T135	403	0
T136	423	0
T137	503	0
T138	1037	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1102
T1	0	2
T73	0	2
T95	0	13
T100	141936	1
T101	0	1
T102	0	1
T103	0	11
T104	0	11
T128	0	1
T129	0	1
T130	130789	0
T131	130789	0
T132	138342	0
T133	247808	0
T134	138342	0
T135	112864	0
T136	118546	0
T137	140863	0
T138	130789	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T100,T101,T102
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T103,T104,T95
1	1	Covered	T100,T101,T102

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1052	0	0
SrcPulseCheck_M	2727417	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1052
T73	0	2
T74	0	2
T95	0	13
T100	141936	1
T101	0	1
T102	0	1
T103	0	11
T104	0	11
T128	0	1
T129	0	1
T130	130789	0
T131	130789	0
T132	138342	0
T133	247808	0
T134	138342	0
T135	112864	0
T136	118546	0
T137	140863	0
T138	130789	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1052
T73	0	2
T74	0	2
T95	0	13
T100	506	1
T101	0	1
T102	0	1
T103	0	11
T104	0	11
T128	0	1
T129	0	1
T130	1037	0
T131	1037	0
T132	494	0
T133	884	0
T134	494	0
T135	403	0
T136	423	0
T137	503	0
T138	1037	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T1
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	982	0	0
SrcPulseCheck_M	754515696	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	982
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	9
T82	0	2
T95	0	9
T96	0	9
T103	7721	11
T104	0	11
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	1
T2	0	20
T73	0	2
T74	0	2
T80	0	9
T82	0	2
T95	0	9
T96	0	9
T103	215076	11
T104	0	11
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	982	0	0
SrcPulseCheck_M	2727417	982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	982
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	9
T82	0	2
T95	0	9
T96	0	9
T103	215076	11
T104	0	11
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	982
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	9
T82	0	2
T95	0	9
T96	0	9
T103	7721	11
T104	0	11
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T1
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1127	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1127
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	7721	11
T104	0	11
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T1	0	2
T2	0	20
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	215076	11
T104	0	11
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1127	0	0
SrcPulseCheck_M	2727417	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1127
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	215076	11
T104	0	11
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1127
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	7721	11
T104	0	11
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T1
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	10
T82	0	2
T95	0	10
T96	0	10
T103	7721	11
T104	0	11
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T1	0	1
T2	0	20
T73	0	2
T74	0	2
T80	0	10
T82	0	2
T95	0	10
T96	0	10
T103	215076	11
T104	0	11
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	10
T82	0	2
T95	0	10
T96	0	10
T103	215076	11
T104	0	11
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	10
T82	0	2
T95	0	10
T96	0	10
T103	7721	11
T104	0	11
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T100,T101,T102
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T103,T104,T95
1	1	Covered	T100,T101,T102

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1023	0	0
SrcPulseCheck_M	754515696	1053	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1023
T73	0	2
T74	0	2
T95	0	11
T100	506	1
T101	0	1
T102	0	1
T103	0	9
T104	0	9
T128	0	1
T129	0	1
T130	1037	0
T131	1037	0
T132	494	0
T133	884	0
T134	494	0
T135	403	0
T136	423	0
T137	503	0
T138	1037	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1053
T1	0	1
T73	0	2
T95	0	11
T100	141936	1
T101	0	1
T102	0	1
T103	0	9
T104	0	9
T128	0	1
T129	0	1
T130	130789	0
T131	130789	0
T132	138342	0
T133	247808	0
T134	138342	0
T135	112864	0
T136	118546	0
T137	140863	0
T138	130789	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T100,T101,T102
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T100,T101,T102
1	0	Covered	T103,T104,T95
1	1	Covered	T100,T101,T102

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1023	0	0
SrcPulseCheck_M	2727417	1023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1023
T73	0	2
T74	0	2
T95	0	11
T100	141936	1
T101	0	1
T102	0	1
T103	0	9
T104	0	9
T128	0	1
T129	0	1
T130	130789	0
T131	130789	0
T132	138342	0
T133	247808	0
T134	138342	0
T135	112864	0
T136	118546	0
T137	140863	0
T138	130789	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1023
T73	0	2
T74	0	2
T95	0	11
T100	506	1
T101	0	1
T102	0	1
T103	0	9
T104	0	9
T128	0	1
T129	0	1
T130	1037	0
T131	1037	0
T132	494	0
T133	884	0
T134	494	0
T135	403	0
T136	423	0
T137	503	0
T138	1037	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T1
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1123	0	0
SrcPulseCheck_M	754515696	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1123
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	7721	9
T104	0	9
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1173
T1	0	2
T2	0	20
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	215076	9
T104	0	9
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1123	0	0
SrcPulseCheck_M	2727417	1123	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1123
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	215076	9
T104	0	9
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1123
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	7721	9
T104	0	9
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T1
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1118	0	0
SrcPulseCheck_M	754515696	1168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1118
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	7721	9
T104	0	9
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1168
T1	0	2
T2	0	20
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	215076	9
T104	0	9
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1118	0	0
SrcPulseCheck_M	2727417	1118	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1118
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	215076	9
T104	0	9
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1118
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	16
T82	0	2
T95	0	16
T96	0	16
T103	7721	9
T104	0	9
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T1
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T1
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1048	0	0
SrcPulseCheck_M	754515696	1078	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1048
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	12
T82	0	2
T95	0	12
T96	0	12
T103	7721	9
T104	0	9
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1078
T1	0	1
T2	0	20
T73	0	2
T74	0	2
T80	0	12
T82	0	2
T95	0	12
T96	0	12
T103	215076	9
T104	0	9
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T103,T104,T95
1	0	Covered	T103,T104,T95
1	1	Covered	T103,T104,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1048	0	0
SrcPulseCheck_M	2727417	1048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1048
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	12
T82	0	2
T95	0	12
T96	0	12
T103	215076	9
T104	0	9
T139	134330	0
T140	235306	0
T141	488486	0
T142	488486	0
T143	140863	0
T144	116176	0
T145	130789	0
T146	112864	0
T147	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1048
T2	0	20
T11	0	2
T73	0	2
T74	0	2
T80	0	12
T82	0	2
T95	0	12
T96	0	12
T103	7721	9
T104	0	9
T139	479	0
T140	8403	0
T141	17445	0
T142	17445	0
T143	503	0
T144	414	0
T145	1037	0
T146	403	0
T147	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1777	0	0
SrcPulseCheck_M	754515696	1827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1777
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1827
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1777	0	0
SrcPulseCheck_M	2727417	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1777
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1777
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1597	0	0
SrcPulseCheck_M	754515696	1627	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1597
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1627
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1597	0	0
SrcPulseCheck_M	2727417	1597	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1597
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1597
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1747	0	0
SrcPulseCheck_M	754515696	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1747
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1777
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1747	0	0
SrcPulseCheck_M	2727417	1747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1747
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1747
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1692	0	0
SrcPulseCheck_M	754515696	1722	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1692
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1722
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1692	0	0
SrcPulseCheck_M	2727417	1692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1692
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1692
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1968	0	0
SrcPulseCheck_M	754515696	1998	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1968
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1998
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1968	0	0
SrcPulseCheck_M	2727417	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1968
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1968
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1763	0	0
SrcPulseCheck_M	754515696	1793	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1763
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1793
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1763	0	0
SrcPulseCheck_M	2727417	1763	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1763
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1763
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1738	0	0
SrcPulseCheck_M	754515696	1768	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1738
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1768
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1738	0	0
SrcPulseCheck_M	2727417	1738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1738
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1738
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1813	0	0
SrcPulseCheck_M	754515696	1863	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1813
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1863
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1813	0	0
SrcPulseCheck_M	2727417	1813	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1813
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1813
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1773	0	0
SrcPulseCheck_M	754515696	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1773
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1803
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1773	0	0
SrcPulseCheck_M	2727417	1773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1773
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	1
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1773
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	1
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1663	0	0
SrcPulseCheck_M	754515696	1693	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1663
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1693
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1663	0	0
SrcPulseCheck_M	2727417	1663	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1663
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1663
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1603	0	0
SrcPulseCheck_M	754515696	1633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1603
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1633
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1603	0	0
SrcPulseCheck_M	2727417	1603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1603
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1603
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1683	0	0
SrcPulseCheck_M	754515696	1733	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1683
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1733
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T22,T23,T25
1	1	Covered	T103,T104,T95

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T25
1	0	Covered	T103,T104,T95
1	1	Covered	T22,T23,T25

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1683	0	0
SrcPulseCheck_M	2727417	1683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1683
T19	130789	0
T22	662426	9
T23	662426	9
T24	134330	0
T25	662426	9
T26	203230	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1683
T19	1037	0
T22	23657	9
T23	23657	9
T24	479	0
T25	23657	9
T26	817	0
T27	0	9
T28	0	5
T29	0	9
T31	0	9
T33	0	5
T35	0	9
T36	0	5
T41	503	0
T42	494	0
T43	494	0
T44	423	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T33,T36

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T33,T36
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1410	0	0
SrcPulseCheck_M	754515696	1440	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1410
T19	1037	0
T22	23657	8
T23	23657	8
T24	479	1
T25	23657	8
T26	817	0
T27	0	8
T28	0	7
T29	0	8
T31	0	8
T33	0	7
T35	0	8
T41	503	0
T42	494	0
T43	494	0
T44	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1440
T19	130789	0
T22	662426	8
T23	662426	8
T24	134330	1
T25	662426	8
T26	203230	0
T27	0	8
T28	0	7
T29	0	8
T31	0	8
T33	0	7
T35	0	8
T41	140863	0
T42	138342	0
T43	138342	0
T44	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T26,T28
1	0	Covered	T18,T26,T28
1	1	Covered	T18,T26,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T18,T26,T28
1	0	Covered	T18,T26,T30
1	1	Covered	T18,T26,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	990	0	0
SrcPulseCheck_M	754515696	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	990
T18	817	3
T19	1037	0
T22	23657	0
T23	23657	0
T24	479	0
T25	23657	0
T26	0	3
T28	0	1
T30	0	3
T32	0	3
T33	0	1
T34	0	3
T36	0	1
T37	0	1
T38	0	3
T39	403	0
T40	414	0
T41	503	0
T42	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1022
T18	203230	3
T19	130789	0
T22	662426	0
T23	662426	0
T24	134330	0
T25	662426	0
T26	0	3
T28	0	1
T30	0	3
T32	0	3
T33	0	1
T34	0	3
T36	0	1
T37	0	1
T38	0	3
T39	112864	0
T40	116176	0
T41	140863	0
T42	138342	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc