Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	64.58	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	54.17	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	58.33	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	58.33	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	62.50	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	66.67	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	66.67	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	70.83	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	79.17	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
54.17	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	11	5	31.25

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	11	5	31.25	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
58.33	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	10	6	37.50

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	10	6	37.50	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
58.33	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	10	6	37.50

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	10	6	37.50	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	9	7	43.75

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	9	7	43.75	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	8	8	50.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	8	8	50.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	8	8	50.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	8	8	50.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
70.83	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	7	9	56.25

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	7	9	56.25	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.17	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	5	11	68.75

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	5	11	68.75	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T17

7

T21

7

T22

7

auto[1]

1300

1

T17

13

T21

13

T22

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

400

1

T17

4

T21

4

T22

4

from_0to1

300

1

T17

3

T21

3

T22

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T17

9

T21

9

T22

9

auto[1]

1100

1

T17

11

T21

11

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T17

10

T21

10

T22

10

auto[1]

1000

1

T17

10

T21

10

T22

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	11	5	31.25	11

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[1]]	*	--	--	2
[auto[0]]	[from_0to1]	*	*	--	--	4
[auto[1]]	[from_1to0]	[auto[0]]	*	--	--	2
[auto[1]]	[from_0to1]	[auto[0]]	*	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[from_1to0]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[0]

from_1to0

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[1]

from_0to1

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T17

11

T21

11

T22

11

auto[1]

900

1

T17

9

T21

9

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

400

1

T17

4

T21

4

T22

4

from_0to1

400

1

T17

4

T21

4

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T17

7

T21

7

T22

7

auto[1]

1300

1

T17

13

T21

13

T22

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T17

11

T21

11

T22

11

auto[1]

900

1

T17

9

T21

9

T22

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	10	6	37.50	10

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[1]]	*	--	--	2
[auto[0]]	[from_0to1]	[auto[0]]	*	--	--	2
[auto[1]]	[from_1to0]	[auto[0]]	*	--	--	2
[auto[1]]	[from_0to1]	*	[auto[0]]	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[from_0to1]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[1]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[1]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1300

1

T17

13

T21

13

T22

13

auto[1]

700

1

T17

7

T21

7

T22

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

400

1

T17

4

T21

4

T22

4

from_0to1

400

1

T17

4

T21

4

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T17

9

T21

9

T22

9

auto[1]

1100

1

T17

11

T21

11

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T17

12

T21

12

T22

12

auto[1]

800

1

T17

8

T21

8

T22

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	10	6	37.50	10

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[0]]	*	--	--	2
[auto[0]]	[from_0to1]	[auto[1]]	*	--	--	2
[auto[1]]	[from_0to1]	[auto[1]]	*	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[from_1to0]	[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[from_1to0]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[from_0to1]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[1]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[0]

from_0to1

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T17

12

T21

12

T22

12

auto[1]

800

1

T17

8

T21

8

T22

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

400

1

T17

4

T21

4

T22

4

from_0to1

300

1

T17

3

T21

3

T22

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800

1

T17

8

T21

8

T22

8

auto[1]

1200

1

T17

12

T21

12

T22

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T17

9

T21

9

T22

9

auto[1]

1100

1

T17

11

T21

11

T22

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	9	7	43.75	9

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_0to1]	[auto[0]]	*	--	--	2
[auto[1]]	[from_1to0]	[auto[0]]	*	--	--	2
[auto[1]]	[from_0to1]	[auto[0]]	*	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[from_0to1]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[from_1to0]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T17

7

T21

7

T22

7

auto[1]

1300

1

T17

13

T21

13

T22

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T17

5

T21

5

T22

5

from_0to1

500

1

T17

5

T21

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1300

1

T17

13

T21

13

T22

13

auto[1]

700

1

T17

7

T21

7

T22

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T17

11

T21

11

T22

11

auto[1]

900

1

T17

9

T21

9

T22

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	8	8	50.00	8

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	*	*	--	--	4
[auto[0]]	[from_0to1]	[auto[1]]	*	--	--	2
[auto[1]]	[from_0to1]	*	[auto[0]]	--	--	2

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_0to1

auto[0]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[0]

from_0to1

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800

1

T17

8

T21

8

T22

8

auto[1]

1200

1

T17

12

T21

12

T22

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

600

1

T17

6

T21

6

T22

6

from_0to1

500

1

T17

5

T21

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T17

9

T21

9

T22

9

auto[1]

1100

1

T17

11

T21

11

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T17

7

T21

7

T22

7

auto[1]

1300

1

T17

13

T21

13

T22

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	8	8	50.00	8

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_0to1]	[auto[1]]	*	--	--	2
[auto[1]]	[from_1to0]	[auto[0]]	*	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[from_0to1]	[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[from_1to0]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[from_0to1]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

300

1

T17

3

T21

3

T22

3

auto[1]

from_0to1

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T17

10

T21

10

T22

10

auto[1]

1000

1

T17

10

T21

10

T22

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

600

1

T17

6

T21

6

T22

6

from_0to1

600

1

T17

6

T21

6

T22

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T17

10

T21

10

T22

10

auto[1]

1000

1

T17

10

T21

10

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T17

9

T21

9

T22

9

auto[1]

1100

1

T17

11

T21

11

T22

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	7	9	56.25	7

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	*	[auto[0]]	--	--	2
[auto[1]]	[from_1to0]	*	[auto[0]]	--	--	2
[auto[1]]	[from_0to1]	*	[auto[1]]	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_0to1]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[0]

from_0to1

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[0]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1300

1

T17

13

T21

13

T22

13

auto[1]

700

1

T17

7

T21

7

T22

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

800

1

T17

8

T21

8

T22

8

from_0to1

800

1

T17

8

T21

8

T22

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T17

10

T21

10

T22

10

auto[1]

1000

1

T17

10

T21

10

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1300

1

T17

13

T21

13

T22

13

auto[1]

700

1

T17

7

T21

7

T22

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	5	11	68.75	5

Automatically Generated Cross Bins for cp_pin_cross

Element holes

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[from_0to1]	*	[auto[1]]	--	--	2

Uncovered bins

cp_en_override	cp_override_value	cp_pin_allowed_0	cp_pin_allowed_1	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[from_1to0]	[auto[0]]	[auto[0]]	0	1	1
[auto[0]]	[from_0to1]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[from_1to0]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[1]

200

1

T17

2

T21

2

T22

2

auto[0]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

300

1

T17

3

T21

3

T22

3

auto[0]

from_0to1

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[0]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[1]

from_1to0

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

100

1

T17

1

T21

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

200

1

T17

2

T21

2

T22

2

auto[1]

from_0to1

auto[1]

auto[0]

100

1

T17

1

T21

1

T22

1