Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 93.88 97.93 94.86 100.00 79.49 97.01 94.01
dut 93.88 97.93 94.86 100.00 79.49 97.01 94.01
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 2.78 2.78
tlul_assert_device 95.24 100.00 85.71 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_intr_hw 93.75 100.00 75.00 100.00 100.00
u_prim_sync_reqack 87.50 100.00 50.00 100.00 100.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 98.83 99.31 96.13 100.00 98.71 100.00
subtree...
u_sysrst_ctrl_autoblock 86.66 90.00 94.44 66.67 88.46 93.75
u_sysrst_ctrl_detect 85.00 89.13 90.48 66.67 85.00 93.75
u_sysrst_ctrl_combo 97.18 98.76 92.55 100.00 97.00 97.58
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 95.37 97.83 90.48 100.00 95.24 93.33
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[1].u_combo_act 92.34 91.67 85.37 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 97.71 100.00 95.24 100.00 100.00 93.33
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[2].u_combo_act 93.16 91.67 87.80 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 95.37 97.83 90.48 100.00 95.24 93.33
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[3].u_combo_act 98.37 100.00 95.12 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
u_sysrst_ctrl_keyintr 83.53 89.38 85.19 67.86 85.36 89.86
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 81.68 89.13 80.95 66.67 85.00 86.67
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 85.00 89.13 90.48 66.67 85.00 93.75
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 81.68 89.13 80.95 66.67 85.00 86.67
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 85.00 89.13 90.48 66.67 85.00 93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 81.68 89.13 80.95 66.67 85.00 86.67
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 86.62 91.30 80.95 83.33 90.00 87.50
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 89.30 93.48 86.44 83.33 89.66 93.62
u_sysrst_ctrl_detect_ac_present 89.13 93.02 86.67 83.33 88.89 93.75
u_sysrst_ctrl_detect_lid_open 89.81 93.48 88.89 83.33 90.00 93.33
u_sysrst_ctrl_detect_pwrb 89.89 93.48 88.89 83.33 90.00 93.75
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