Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
2.78 2.78

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 2.78 2.78



Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
2.78 2.78


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
2.78 2.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.34 100.00 96.72 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 1 2.78
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 1 2.78




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 754515696 10220 0 0
auto_block_debounce_ctl_rd_A 754515696 0 0 0
auto_block_out_ctl_rd_A 754515696 0 0 0
com_det_ctl_0_rd_A 754515696 0 0 0
com_det_ctl_1_rd_A 754515696 0 0 0
com_det_ctl_2_rd_A 754515696 0 0 0
com_det_ctl_3_rd_A 754515696 0 0 0
com_out_ctl_0_rd_A 754515696 0 0 0
com_out_ctl_1_rd_A 754515696 0 0 0
com_out_ctl_2_rd_A 754515696 0 0 0
com_out_ctl_3_rd_A 754515696 0 0 0
com_pre_det_ctl_0_rd_A 754515696 0 0 0
com_pre_det_ctl_1_rd_A 754515696 0 0 0
com_pre_det_ctl_2_rd_A 754515696 0 0 0
com_pre_det_ctl_3_rd_A 754515696 0 0 0
com_pre_sel_ctl_0_rd_A 754515696 0 0 0
com_pre_sel_ctl_1_rd_A 754515696 0 0 0
com_pre_sel_ctl_2_rd_A 754515696 0 0 0
com_pre_sel_ctl_3_rd_A 754515696 0 0 0
com_sel_ctl_0_rd_A 754515696 0 0 0
com_sel_ctl_1_rd_A 754515696 0 0 0
com_sel_ctl_2_rd_A 754515696 0 0 0
com_sel_ctl_3_rd_A 754515696 0 0 0
ec_rst_ctl_rd_A 754515696 0 0 0
intr_enable_rd_A 754515696 0 0 0
key_intr_ctl_rd_A 754515696 0 0 0
key_intr_debounce_ctl_rd_A 754515696 0 0 0
key_invert_ctl_rd_A 754515696 0 0 0
pin_allowed_ctl_rd_A 754515696 0 0 0
pin_out_ctl_rd_A 754515696 0 0 0
pin_out_value_rd_A 754515696 0 0 0
regwen_rd_A 754515696 0 0 0
ulp_ac_debounce_ctl_rd_A 754515696 0 0 0
ulp_ctl_rd_A 754515696 0 0 0
ulp_lid_debounce_ctl_rd_A 754515696 0 0 0
ulp_pwrb_debounce_ctl_rd_A 754515696 0 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 10220 0 0
T1 238063 4 0 0
T2 122452 503 0 0
T3 122452 503 0 0
T4 122452 503 0 0
T5 122452 503 0 0
T6 0 503 0 0
T7 0 4 0 0
T8 0 4 0 0
T9 0 503 0 0
T10 0 503 0 0
T11 113301 0 0 0
T12 113301 0 0 0
T13 116199 0 0 0
T14 116199 0 0 0
T15 113301 0 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 0 0 0

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