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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
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T555 /workspace/coverage/default/29.sysrst_ctrl_smoke.65983355520790378859216748840268299127745269975927042638470327782955003079649 Nov 22 01:25:41 PM PST 23 Nov 22 01:25:52 PM PST 23 2116887594 ps
T556 /workspace/coverage/default/22.sysrst_ctrl_stress_all.108331661138554954338835204893230225684516431125714737834313449309264699933025 Nov 22 01:25:26 PM PST 23 Nov 22 01:27:50 PM PST 23 87228974549 ps
T557 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.27015118173486019630729247545646580237071398053914591180970410924129202337481 Nov 22 01:24:27 PM PST 23 Nov 22 01:24:36 PM PST 23 4425119128 ps
T558 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.39250587267840971615992898726815307195787310012958605496391698048999784488151 Nov 22 01:24:56 PM PST 23 Nov 22 01:28:05 PM PST 23 118289458206 ps
T559 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.21033166551177345525061310445756942733117120366857932058619068491302781512781 Nov 22 01:25:08 PM PST 23 Nov 22 01:25:15 PM PST 23 2619740714 ps
T560 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.76776779881486093023204213712159818470651630803572497035868584903366994293651 Nov 22 01:24:35 PM PST 23 Nov 22 01:27:40 PM PST 23 118289458206 ps
T561 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.68800997702401997880911963613497730252096779299454728449706437535158794388952 Nov 22 01:24:31 PM PST 23 Nov 22 01:24:39 PM PST 23 4089103959 ps
T562 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.106486725783708311368283559119551258663442081668711745633698956743231864346812 Nov 22 01:23:38 PM PST 23 Nov 22 01:23:54 PM PST 23 3138968703 ps
T563 /workspace/coverage/default/10.sysrst_ctrl_smoke.12760229252148077733808605356377242778015412078966103889955160244633861220688 Nov 22 01:23:39 PM PST 23 Nov 22 01:23:53 PM PST 23 2116887594 ps
T564 /workspace/coverage/default/34.sysrst_ctrl_alert_test.17079280503660989388091704851224804534781577715133481649374055648708301686719 Nov 22 01:24:54 PM PST 23 Nov 22 01:25:01 PM PST 23 2015424120 ps
T565 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.99640390287858753749177023283498802788292053308242239505791026191624525653358 Nov 22 01:24:30 PM PST 23 Nov 22 01:24:37 PM PST 23 2619740714 ps
T566 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.30311117740679271321667018544534348334678083266761905705409673074266339729900 Nov 22 01:23:39 PM PST 23 Nov 22 01:23:54 PM PST 23 2470384766 ps
T567 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.40457934808977295740007913430194810989563571376719117816853799937565884853904 Nov 22 01:25:58 PM PST 23 Nov 22 01:26:10 PM PST 23 4425119128 ps
T568 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.63134713207439773724648899514400613693317431926512816571981406921965434350957 Nov 22 01:24:56 PM PST 23 Nov 22 01:25:05 PM PST 23 5189470156 ps
T569 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.52216971420726938687045126709240383199057432823605631629595655261918658244228 Nov 22 01:26:12 PM PST 23 Nov 22 01:26:23 PM PST 23 5189470156 ps
T570 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.18302970764974169422457502573421905418764675977962616453279163320704648810390 Nov 22 01:24:30 PM PST 23 Nov 22 01:24:37 PM PST 23 5189470156 ps
T571 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.68351310851436229398899630820737770936782389273413160353600178752838944891368 Nov 22 01:24:27 PM PST 23 Nov 22 01:24:33 PM PST 23 2619740714 ps
T572 /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.104258815316201893653911667597654465389621287530146435576841790264164188175393 Nov 22 01:24:49 PM PST 23 Nov 22 01:24:56 PM PST 23 5189470156 ps
T573 /workspace/coverage/default/36.sysrst_ctrl_smoke.57560109903076675505748792510955858458147985135763014573002140169150597146535 Nov 22 01:25:46 PM PST 23 Nov 22 01:25:56 PM PST 23 2116887594 ps
T574 /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.95039584573170879470962965095787013259056068177458819725398212568226809062711 Nov 22 01:23:50 PM PST 23 Nov 22 01:24:04 PM PST 23 5189470156 ps
T575 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.75378483182894952076622828731100817830450943145193490482557485010149461471403 Nov 22 01:25:22 PM PST 23 Nov 22 01:25:29 PM PST 23 5189470156 ps
T576 /workspace/coverage/default/6.sysrst_ctrl_smoke.5741046261789485177711293772482683177261951690072648476005597554590708985930 Nov 22 01:23:33 PM PST 23 Nov 22 01:23:50 PM PST 23 2116887594 ps
T577 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.17219752893485652128096525043527071256253334414497085852386009809733387907196 Nov 22 01:23:55 PM PST 23 Nov 22 01:24:10 PM PST 23 4425119128 ps
T578 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.63885889929873992578582667985628031670908083342624866565683458045512613651654 Nov 22 01:23:25 PM PST 23 Nov 22 01:23:44 PM PST 23 2074566504 ps
T579 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.34109623011426281590029179412845977778908738234055217213961584224992072312339 Nov 22 01:24:35 PM PST 23 Nov 22 01:24:42 PM PST 23 2515402263 ps
T580 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.45608772567008491103906167901794490690552298409443750295206735773243677334338 Nov 22 01:25:04 PM PST 23 Nov 22 01:25:12 PM PST 23 2515402263 ps
T581 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.101960092246829892688682077970616336913833432581424080444086352095853733388669 Nov 22 01:25:37 PM PST 23 Nov 22 01:25:54 PM PST 23 4425119128 ps
T582 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.108191435303026855431106002398471484218941332291923690713957102379424631056522 Nov 22 01:25:27 PM PST 23 Nov 22 01:25:41 PM PST 23 4089103959 ps
T583 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.99245967478007705124953463306565092562557033373755391878178206261302355487391 Nov 22 01:25:27 PM PST 23 Nov 22 01:25:41 PM PST 23 2515402263 ps
T584 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.115036033434082140972906904280882060471720398288088856447165208995023684646885 Nov 22 01:24:49 PM PST 23 Nov 22 01:24:56 PM PST 23 2515402263 ps
T585 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.25205936827048907398726122316472214740796580472284540224476728298396170808052 Nov 22 01:24:56 PM PST 23 Nov 22 01:25:05 PM PST 23 2470384766 ps
T586 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.71740257312438460217981196939431703836900950361368322132429977807732308986340 Nov 22 01:24:16 PM PST 23 Nov 22 01:24:25 PM PST 23 5189470156 ps
T587 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.14174220006465001163523852875000534068091771325741819133119925937877679069423 Nov 22 01:24:57 PM PST 23 Nov 22 01:25:05 PM PST 23 2515402263 ps
T588 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.22550628325816879770111340901679231924307671747561152498777223868767860079298 Nov 22 01:25:45 PM PST 23 Nov 22 01:28:53 PM PST 23 118289458206 ps
T589 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.84015038571514510156256249025921235461093527544634656905935082578709978971744 Nov 22 01:24:53 PM PST 23 Nov 22 01:25:02 PM PST 23 4089103959 ps
T590 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4791090851744489771194404929604190545574944284515932740079745931205021728289 Nov 22 01:25:29 PM PST 23 Nov 22 01:25:43 PM PST 23 5189470156 ps
T591 /workspace/coverage/default/40.sysrst_ctrl_smoke.34673048375740181781902011295439763158590921174410497604327496411916189523324 Nov 22 01:25:43 PM PST 23 Nov 22 01:25:53 PM PST 23 2116887594 ps
T592 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.59643256220474733798764258496150292224350569029669226799207870777191734275890 Nov 22 01:24:50 PM PST 23 Nov 22 01:24:57 PM PST 23 2515402263 ps
T593 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.114761684780798564050258356470716330826002394876750064320213909533051067536735 Nov 22 01:23:57 PM PST 23 Nov 22 01:24:09 PM PST 23 3138968703 ps
T594 /workspace/coverage/default/43.sysrst_ctrl_alert_test.2558186610316392103630794125120392415512885234851795253724553356690708708513 Nov 22 01:25:24 PM PST 23 Nov 22 01:25:30 PM PST 23 2015424120 ps
T595 /workspace/coverage/default/5.sysrst_ctrl_alert_test.103473641078987097989953392042753005001891502069095280464440785950325305892270 Nov 22 01:23:38 PM PST 23 Nov 22 01:23:52 PM PST 23 2015424120 ps
T596 /workspace/coverage/default/19.sysrst_ctrl_alert_test.8565158820170598219020551726768713608674188390710074896143421166409945911962 Nov 22 01:24:45 PM PST 23 Nov 22 01:24:50 PM PST 23 2015424120 ps
T597 /workspace/coverage/default/13.sysrst_ctrl_stress_all.56111279399023024449020735615185204682137796370039292005582063401477941221720 Nov 22 01:23:55 PM PST 23 Nov 22 01:26:19 PM PST 23 87228974549 ps
T598 /workspace/coverage/default/7.sysrst_ctrl_stress_all.20404767518250641067530821703473839967273061179725092483087668549081890236432 Nov 22 01:24:02 PM PST 23 Nov 22 01:26:27 PM PST 23 87228974549 ps
T599 /workspace/coverage/default/40.sysrst_ctrl_alert_test.76810604859875613187269625838467350550191720990288163397694947377873734522799 Nov 22 01:24:54 PM PST 23 Nov 22 01:25:02 PM PST 23 2015424120 ps
T600 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.32052074123705641962292982826965288998010828757682797012613812480667009508114 Nov 22 01:24:36 PM PST 23 Nov 22 01:24:41 PM PST 23 2074566504 ps
T601 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.20933367620942886457336890315525152762951474056022513409356695692584239836436 Nov 22 01:24:12 PM PST 23 Nov 22 01:24:21 PM PST 23 2515402263 ps
T602 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.114340830834386233497141665735981272978776085811438833775617377583277868590221 Nov 22 01:24:43 PM PST 23 Nov 22 01:27:46 PM PST 23 118289458206 ps
T603 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.49212472684853761167473809519981528471356302060202383779655281257523109362656 Nov 22 01:25:40 PM PST 23 Nov 22 01:25:55 PM PST 23 4089103959 ps
T604 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.35787599126330448893955219386230443571654579293054408049435174678330745877019 Nov 22 01:24:28 PM PST 23 Nov 22 01:24:35 PM PST 23 3138968703 ps
T605 /workspace/coverage/default/6.sysrst_ctrl_stress_all.44764666826593974675597510934512948640599785901052713218123313994320682385959 Nov 22 01:23:40 PM PST 23 Nov 22 01:26:06 PM PST 23 87228974549 ps
T606 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.5305048095494081747999402057142623446125688019660187659286545411204647831056 Nov 22 01:23:37 PM PST 23 Nov 22 01:23:53 PM PST 23 2619740714 ps
T607 /workspace/coverage/default/6.sysrst_ctrl_alert_test.53279968516591870724152309693670205096096862396961775291200927657036608472826 Nov 22 01:23:35 PM PST 23 Nov 22 01:23:51 PM PST 23 2015424120 ps
T608 /workspace/coverage/default/17.sysrst_ctrl_alert_test.98759883859043693386680753146154975252511235922461741446264562888327508622727 Nov 22 01:24:03 PM PST 23 Nov 22 01:24:15 PM PST 23 2015424120 ps
T609 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.19099998612721818806159593473634103766990601132533883756408911310364303700786 Nov 22 01:24:51 PM PST 23 Nov 22 01:25:00 PM PST 23 4089103959 ps
T610 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.63632283801516925810612599282571160042773427720473605057557786789507526292472 Nov 22 01:23:48 PM PST 23 Nov 22 01:24:03 PM PST 23 4425119128 ps
T611 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.110003783824927370848036768315217122771230168663686001836375504667803572133266 Nov 22 01:24:49 PM PST 23 Nov 22 01:24:57 PM PST 23 3138968703 ps
T612 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.74133183634266708341120670603358561812023048971766906077425391449344038470565 Nov 22 01:25:29 PM PST 23 Nov 22 01:25:44 PM PST 23 2470384766 ps
T613 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.36955568271229063668695457473226328994234847817522963372739664995639685728375 Nov 22 01:23:38 PM PST 23 Nov 22 01:26:50 PM PST 23 118289458206 ps
T614 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.105773390299687035768154616039783855140987555403164022074039913801345919418061 Nov 22 01:24:59 PM PST 23 Nov 22 01:25:08 PM PST 23 3138968703 ps
T108 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.69603252768203435730644559922526168049061372132272364875443999731646841537782 Nov 22 01:23:42 PM PST 23 Nov 22 01:23:56 PM PST 23 2534562824 ps
T615 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.56198471915480006691419388340550673481097824495672606999223332015177091373046 Nov 22 01:23:51 PM PST 23 Nov 22 01:24:05 PM PST 23 5189470156 ps
T616 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.27179639143705069090607293938845951170667251632425030780930020893597115368262 Nov 22 01:25:34 PM PST 23 Nov 22 01:25:47 PM PST 23 5189470156 ps
T617 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.56252931509846683125957896159114223032403350998553632904419351439904556449358 Nov 22 01:24:30 PM PST 23 Nov 22 01:24:36 PM PST 23 2074566504 ps
T618 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.46969741454043616441068892618119196963451222222868134314126838549850714440573 Nov 22 01:23:50 PM PST 23 Nov 22 01:24:06 PM PST 23 4089103959 ps
T619 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.33894354596660509460203005441667465017691902686676386016501880339852162633717 Nov 22 01:24:11 PM PST 23 Nov 22 01:24:21 PM PST 23 4089103959 ps
T620 /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.21405290836318314118699883895349196969396754348030730989163369363917457633388 Nov 22 01:24:37 PM PST 23 Nov 22 01:24:44 PM PST 23 3138968703 ps
T621 /workspace/coverage/default/9.sysrst_ctrl_smoke.72396052455785099426090533291921243414938468932009059851025025803467364361223 Nov 22 01:23:58 PM PST 23 Nov 22 01:24:07 PM PST 23 2116887594 ps
T622 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.75970421143534420933269689967088651234539234306225743850377158038883096040340 Nov 22 01:24:28 PM PST 23 Nov 22 01:24:36 PM PST 23 4089103959 ps
T623 /workspace/coverage/default/23.sysrst_ctrl_alert_test.33273229471640818955942632610620172590996495340295123063757667419365162550633 Nov 22 01:24:27 PM PST 23 Nov 22 01:24:32 PM PST 23 2015424120 ps
T624 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.67051196008859536020159463347506228338979468728924338791766558728368150608821 Nov 22 01:25:44 PM PST 23 Nov 22 01:25:55 PM PST 23 2470384766 ps
T625 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.32947027115834003012752650201453595230315843837239647093627170026259429694164 Nov 22 01:25:44 PM PST 23 Nov 22 01:25:54 PM PST 23 2074566504 ps
T626 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.112307150095990101046812156016746359340468002228832523900868011660870614494515 Nov 22 01:24:56 PM PST 23 Nov 22 01:25:06 PM PST 23 4089103959 ps
T627 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.21577850048408641404125830680519324535842819376970834576889432813375681525140 Nov 22 01:24:57 PM PST 23 Nov 22 01:25:05 PM PST 23 5189470156 ps
T628 /workspace/coverage/default/21.sysrst_ctrl_smoke.55566671381557749481841411043005186550574658526519061090124889635704143012491 Nov 22 01:24:46 PM PST 23 Nov 22 01:24:51 PM PST 23 2116887594 ps
T629 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.61815615419210570397833542400139501911447389951416262383712406786541617862293 Nov 22 01:24:11 PM PST 23 Nov 22 01:27:17 PM PST 23 118289458206 ps
T630 /workspace/coverage/default/1.sysrst_ctrl_stress_all.107944321028982985442286396202332396025685034251893633280937127422537275097281 Nov 22 01:23:44 PM PST 23 Nov 22 01:26:08 PM PST 23 87228974549 ps
T631 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.41716120452500012707327660446913076348994783829510764085392823291564241892845 Nov 22 01:24:49 PM PST 23 Nov 22 01:24:55 PM PST 23 2074566504 ps
T632 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.68943314476808629165549704273950920249286899423121909932348874676465313543188 Nov 22 01:24:13 PM PST 23 Nov 22 01:24:21 PM PST 23 2074566504 ps
T633 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.99733194538354597224545127578953711356528316978258664434537747013658217087448 Nov 22 01:25:00 PM PST 23 Nov 22 01:25:08 PM PST 23 2515402263 ps
T634 /workspace/coverage/default/3.sysrst_ctrl_alert_test.114902283145285734000584264546713324277299648050139857246612770996806771678308 Nov 22 01:23:48 PM PST 23 Nov 22 01:24:00 PM PST 23 2015424120 ps
T635 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.27974840985348334810068583832126118922643031779764700602097051981199533452301 Nov 22 01:24:36 PM PST 23 Nov 22 01:27:42 PM PST 23 118289458206 ps
T636 /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.89447373415464393717686808719768943404973242113500487243649843744501123797354 Nov 22 01:25:42 PM PST 23 Nov 22 01:25:53 PM PST 23 5189470156 ps
T637 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.78466916069391510127045355799783210250195432933077102389870140198591421189719 Nov 22 01:24:44 PM PST 23 Nov 22 01:24:52 PM PST 23 4089103959 ps
T638 /workspace/coverage/default/18.sysrst_ctrl_smoke.36373039397876700899446775608099872346331187230271778757454199856552421989078 Nov 22 01:24:12 PM PST 23 Nov 22 01:24:20 PM PST 23 2116887594 ps
T639 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.99594740898805387292168966182566869008657081394478564927407186974935366986785 Nov 22 01:24:49 PM PST 23 Nov 22 01:25:00 PM PST 23 4425119128 ps
T640 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.45895844404351487114558530728783385154437656215877268049280371211024455627263 Nov 22 01:24:25 PM PST 23 Nov 22 01:27:29 PM PST 23 118289458206 ps
T641 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.58604739635374791051987698718765723040409992758926793059986523327282428302454 Nov 22 01:25:50 PM PST 23 Nov 22 01:25:58 PM PST 23 2515402263 ps
T642 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.88540332294397491061604139956647443161558778819077674520444576584241091505661 Nov 22 01:25:00 PM PST 23 Nov 22 01:25:08 PM PST 23 5189470156 ps
T643 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.58724183610156716214980046480640249677400517532447851178721423355310049897234 Nov 22 01:23:26 PM PST 23 Nov 22 01:26:43 PM PST 23 118289458206 ps
T644 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.69531217009592915088340980914470236494299149080917295067620662239888997243884 Nov 22 01:25:07 PM PST 23 Nov 22 01:25:14 PM PST 23 2074566504 ps
T645 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.102732099614596792899399121382542077490021101104456773790696136430738836447016 Nov 22 01:23:55 PM PST 23 Nov 22 01:24:06 PM PST 23 2074566504 ps
T646 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.53539108813908954624031131142822058503147167050227645167049990011018069347753 Nov 22 01:24:46 PM PST 23 Nov 22 01:24:54 PM PST 23 4089103959 ps
T647 /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.12870597842633736519039797687228793273332571931993407524639926134787240141044 Nov 22 01:23:58 PM PST 23 Nov 22 01:24:09 PM PST 23 2470384766 ps
T648 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.113894220549360642665387342867984817416170768441539360342793551214307127178054 Nov 22 01:23:52 PM PST 23 Nov 22 01:24:05 PM PST 23 2470384766 ps
T649 /workspace/coverage/default/49.sysrst_ctrl_smoke.3834333743940824159530310208371342255987755475834527838799202352507082598471 Nov 22 01:25:35 PM PST 23 Nov 22 01:25:50 PM PST 23 2116887594 ps
T650 /workspace/coverage/default/34.sysrst_ctrl_smoke.112946174505393080220489529347454246812010372902459585745084421788751929524799 Nov 22 01:25:05 PM PST 23 Nov 22 01:25:12 PM PST 23 2116887594 ps
T651 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.16709329046275112461545079285316545456525084464165662130929096204017257080517 Nov 22 01:25:08 PM PST 23 Nov 22 01:25:14 PM PST 23 2074566504 ps
T652 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.20735110362009199588455257233907210823538242440171338345037520905272605851675 Nov 22 01:24:35 PM PST 23 Nov 22 01:24:42 PM PST 23 5189470156 ps
T653 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.68533471703118624750280090093613919970493187156643697302706296596301038780906 Nov 22 01:25:43 PM PST 23 Nov 22 01:25:54 PM PST 23 2515402263 ps
T654 /workspace/coverage/default/17.sysrst_ctrl_smoke.48878296354135780025145102861993113771572775134369661285429928916363869738689 Nov 22 01:23:55 PM PST 23 Nov 22 01:24:06 PM PST 23 2116887594 ps
T655 /workspace/coverage/default/16.sysrst_ctrl_smoke.14354972353944604163516453759491102648039876793957935150118232670325262960724 Nov 22 01:23:51 PM PST 23 Nov 22 01:24:04 PM PST 23 2116887594 ps
T656 /workspace/coverage/default/45.sysrst_ctrl_stress_all.80146127439534164773639867380854047216853547988228200386446065138536279189678 Nov 22 01:25:23 PM PST 23 Nov 22 01:27:40 PM PST 23 87228974549 ps
T657 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.111782254153664953548352724364258294376221297455918857679537949358889293574173 Nov 22 01:25:43 PM PST 23 Nov 22 01:28:52 PM PST 23 118289458206 ps
T658 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.47102996792667211097485917826060731177688943025386039154555339602747830565178 Nov 22 01:23:55 PM PST 23 Nov 22 01:24:08 PM PST 23 3138968703 ps
T659 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.63644011871186396511623736557327050003613012797126283206979987745224407582610 Nov 22 01:25:05 PM PST 23 Nov 22 01:25:13 PM PST 23 2515402263 ps
T660 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.27500663892686361979138891732132382139038381238423146154157077291413329363337 Nov 22 01:23:54 PM PST 23 Nov 22 01:24:06 PM PST 23 5189470156 ps
T661 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.49991351467805827450738490607802793273950749526369523667632623891728571281888 Nov 22 01:25:31 PM PST 23 Nov 22 01:25:45 PM PST 23 4089103959 ps
T662 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.56579222742053200241681946421446323613427465273935911556892407558188591829379 Nov 22 01:23:39 PM PST 23 Nov 22 01:26:54 PM PST 23 118289458206 ps
T109 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.29235042980823532365233161353978502543162568367854595288153777297346367769685 Nov 22 01:23:48 PM PST 23 Nov 22 01:24:01 PM PST 23 2534562824 ps
T663 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.74948043472328970558283123546453635572451982123473951676476972551617269689942 Nov 22 01:25:44 PM PST 23 Nov 22 01:25:55 PM PST 23 2470384766 ps
T664 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.5375299457662361060775959324420570799975642162999979169266921680544272995287 Nov 22 01:23:49 PM PST 23 Nov 22 01:24:05 PM PST 23 4089103959 ps
T665 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.91106026207683993753975115174409264617219784648129158394993849162127371603809 Nov 22 01:24:33 PM PST 23 Nov 22 01:24:40 PM PST 23 2470384766 ps
T666 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.51722721797317282443535137994089320149597207798951099589028964785368532450833 Nov 22 01:24:59 PM PST 23 Nov 22 01:25:07 PM PST 23 2515402263 ps
T667 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.65015399222494735269634237434388907976241982361133008629704405280318507436252 Nov 22 01:24:57 PM PST 23 Nov 22 01:25:05 PM PST 23 2074566504 ps
T668 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.112857186701106421690241266063839650909574042619909924769580405642122593924997 Nov 22 01:23:37 PM PST 23 Nov 22 01:23:53 PM PST 23 2470384766 ps
T669 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.39624500203953752066033394568454656438585383271332327233116494369669789312270 Nov 22 01:24:42 PM PST 23 Nov 22 01:24:48 PM PST 23 2074566504 ps
T54 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.15045062331641842660019214959123638622488809932475000640415723541544715374207 Nov 22 01:59:48 PM PST 23 Nov 22 01:59:54 PM PST 23 2074977215 ps
T1 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.76613344947148257527948372201324836226500765129883973194727513557112098663349 Nov 22 02:00:01 PM PST 23 Nov 22 02:01:11 PM PST 23 42510939439 ps
T55 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.33421121224783141098633870359372530548072570933145829474536683480997770550609 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2074977215 ps
T125 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.98891975033880751075193575726481154371786245744152469689695705561679102123405 Nov 22 02:00:10 PM PST 23 Nov 22 02:00:15 PM PST 23 2023227629 ps
T126 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.20975126787073993344960546264767464942017485392714737833267431441680113588810 Nov 22 02:00:16 PM PST 23 Nov 22 02:00:21 PM PST 23 2023227629 ps
T127 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.40912100270108002426118123621501965144172797901252415709915827832203568843151 Nov 22 02:00:09 PM PST 23 Nov 22 02:00:14 PM PST 23 2023227629 ps
T2 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.89402621360163982936895305965167542217852073056378255781021665753704586717265 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:50 PM PST 23 2186637036 ps
T11 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.87865561937215246857753777209301413007283806359388486338035506749915360967420 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:08 PM PST 23 2023227629 ps
T3 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.39568446163237412494304220174953781156120132395622890585309281282271320568185 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:53 PM PST 23 2186637036 ps
T12 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.77771832661760373843313970720223036015248835935375176933618953944693534183960 Nov 22 01:59:53 PM PST 23 Nov 22 01:59:59 PM PST 23 2023227629 ps
T13 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.7711041742590292228892743637464302600834020525334912397472701304637858744362 Nov 22 01:59:49 PM PST 23 Nov 22 01:59:54 PM PST 23 2074977215 ps
T4 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.11528409178246421945174215936945878513714844878981988654547711265061678924537 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:10 PM PST 23 2186637036 ps
T14 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.92849341070029711189817659338773825657917217228856367431992280345386825706052 Nov 22 01:59:51 PM PST 23 Nov 22 01:59:56 PM PST 23 2074977215 ps
T15 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.96365626082838518244669226586428850852615290297545098454381573270963875239397 Nov 22 01:59:50 PM PST 23 Nov 22 01:59:54 PM PST 23 2023227629 ps
T5 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.64417082359289775293783404959105731974945176347660402511250147287147561570842 Nov 22 01:59:47 PM PST 23 Nov 22 01:59:54 PM PST 23 2186637036 ps
T52 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.13201490696276360275529794068825016718342584597846456468955948889242009174888 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2074977215 ps
T6 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.101216492033242740853534701874735581546687716601834924025953484913907191450947 Nov 22 01:59:32 PM PST 23 Nov 22 01:59:39 PM PST 23 2186637036 ps
T56 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.96663295569600755109953617200752786429879401641598864860878149145560034656307 Nov 22 01:59:41 PM PST 23 Nov 22 01:59:52 PM PST 23 6030981281 ps
T7 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.93629444931877587792038271596981773196251072868362355589347638578037533494303 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:06 PM PST 23 2142012393 ps
T77 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.76114796114352540883623851559118801807510466078822049584956442857120805915498 Nov 22 02:00:07 PM PST 23 Nov 22 02:00:12 PM PST 23 2023227629 ps
T8 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.83868418391162035348017618905652858921938236621962455037489293897427984317350 Nov 22 01:59:30 PM PST 23 Nov 22 02:00:39 PM PST 23 42510939439 ps
T78 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.62594583370723609584849973678114389483119256262347241642125017412230166698185 Nov 22 02:00:14 PM PST 23 Nov 22 02:00:19 PM PST 23 2023227629 ps
T9 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.45565201354709826753779787597237820642296346477944647312357882832563963301549 Nov 22 01:59:50 PM PST 23 Nov 22 01:59:56 PM PST 23 2186637036 ps
T10 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.61622534363334782384502108825322471162127433884703836973628409178329995638245 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:08 PM PST 23 2186637036 ps
T57 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.88545983923204175053521290596987372683494657648450383219342411894902952309144 Nov 22 01:59:30 PM PST 23 Nov 22 01:59:35 PM PST 23 2074977215 ps
T81 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.14575037751741014874237078357030835096178352911034308876787009369915567077070 Nov 22 01:59:34 PM PST 23 Nov 22 02:00:00 PM PST 23 9477310853 ps
T48 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.55349993436834045736909197340800778528240656697398755062288374810120647002208 Nov 22 01:59:45 PM PST 23 Nov 22 02:00:55 PM PST 23 42510939439 ps
T49 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2637418192611674421405876952140363997525878649658394074242067524176361055810 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:11 PM PST 23 2186637036 ps
T50 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.110685050519844443590978692248254734761923924985507775950029179173929919557175 Nov 22 01:59:47 PM PST 23 Nov 22 01:59:54 PM PST 23 2186637036 ps
T670 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.47113510787474635800401936214643243239255806801047546423765975250482506686160 Nov 22 01:59:54 PM PST 23 Nov 22 01:59:59 PM PST 23 2023227629 ps
T82 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.32446415075110045701249370611413204706414661255658410600161099813252472864493 Nov 22 01:59:54 PM PST 23 Nov 22 02:00:20 PM PST 23 9477310853 ps
T58 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.15578048520097713755481725134765154063082262795799962668976488499790399785091 Nov 22 01:59:54 PM PST 23 Nov 22 02:00:03 PM PST 23 2890827831 ps
T61 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.29903050874724050788367950233225244925621525049654435427178518642056773866614 Nov 22 01:59:55 PM PST 23 Nov 22 02:00:20 PM PST 23 9477310853 ps
T51 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2029453525812582260581696208457700411651693547956110060307141695448896231904 Nov 22 01:59:51 PM PST 23 Nov 22 01:59:58 PM PST 23 2186637036 ps
T62 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.46919039441837701903685030543849320627762095621496391701090976876150234782746 Nov 22 02:00:12 PM PST 23 Nov 22 02:00:17 PM PST 23 2023227629 ps
T59 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.40722734214117451710520631843647897828121237864449354593818767041881565301731 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:50 PM PST 23 2074977215 ps
T63 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.49272319417268046055826042292542279607873753876473460363904265623132512691589 Nov 22 01:59:55 PM PST 23 Nov 22 01:59:59 PM PST 23 2023227629 ps
T64 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.103308149455344190255262122046024582394129273708870501999030899747643023888125 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:48 PM PST 23 2142012393 ps
T65 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.31244971254050592891260325932395169196689927723870125322167673143661961710723 Nov 22 01:59:47 PM PST 23 Nov 22 01:59:52 PM PST 23 2142012393 ps
T66 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.34659353847703090683140335618128312021337759380788670811351808172959163656864 Nov 22 02:00:09 PM PST 23 Nov 22 02:00:14 PM PST 23 2023227629 ps
T67 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.27104788414013300699556920234863912917978016417892951110436089912220517051638 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:08 PM PST 23 2023227629 ps
T60 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.44013208227461055756815082792050710981424348557165267736935971246502368859751 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:57 PM PST 23 6030981281 ps
T671 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.39508805517111209565705365931323525443001517579809995299717926768910466401782 Nov 22 01:59:56 PM PST 23 Nov 22 02:01:05 PM PST 23 42510939439 ps
T672 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.115719468044813235912271178997442223737835008264453544559971898906128469801286 Nov 22 01:59:47 PM PST 23 Nov 22 02:00:14 PM PST 23 9477310853 ps
T673 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.15430554998455166072707619750735618900866761317507500283317423172420634506267 Nov 22 01:59:44 PM PST 23 Nov 22 02:00:09 PM PST 23 9477310853 ps
T674 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.60344205584357885401043382684136588544070621798508997051983379580829614294495 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:52 PM PST 23 2074977215 ps
T79 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.44770599388560695716496167409636914743046659371221649431717450775971305984998 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:56 PM PST 23 6030981281 ps
T675 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.66101777594181342317542039353504892007653232746536776046709185736069556864291 Nov 22 01:59:37 PM PST 23 Nov 22 01:59:42 PM PST 23 2023227629 ps
T676 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.111839889127917421934919047269708440067322320160213560308713999884008888273180 Nov 22 01:59:48 PM PST 23 Nov 22 01:59:55 PM PST 23 2186637036 ps
T677 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.47702346009634622472478379966723943537394695791116700411349767210377594505685 Nov 22 01:59:51 PM PST 23 Nov 22 02:01:01 PM PST 23 42510939439 ps
T68 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.28539750770612306990918227747239861328922965452627270394584118156154410348132 Nov 22 01:59:51 PM PST 23 Nov 22 02:01:41 PM PST 23 41047879715 ps
T678 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.25142999932309456852835504531980410836527885699403311536738109667684342679632 Nov 22 01:59:53 PM PST 23 Nov 22 02:01:02 PM PST 23 42510939439 ps
T679 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.88432128869334907458937760993967006477604836646875086755766236904307500295283 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:50 PM PST 23 2023227629 ps
T680 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.62830380762140623978304095378874019077273322329865222222736940645417612065911 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:48 PM PST 23 2142012393 ps
T681 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.30241467378962572743099931001700690461900029546395326310550427328483685053129 Nov 22 02:00:11 PM PST 23 Nov 22 02:00:16 PM PST 23 2023227629 ps
T682 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.28242587379055825799256478488469025566929442788023792357327541399897188071007 Nov 22 01:59:59 PM PST 23 Nov 22 02:00:04 PM PST 23 2074977215 ps
T683 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.60518551795498200295059245077803014717426446268845886231221158821306893818906 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2142012393 ps
T69 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.36145951106097256868140019141588641839053315966551636556932781957613634419405 Nov 22 01:59:37 PM PST 23 Nov 22 02:01:29 PM PST 23 41047879715 ps
T684 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.51179200521724965161382570283629806552270962124055913571106180533427337164812 Nov 22 01:59:53 PM PST 23 Nov 22 02:00:19 PM PST 23 9477310853 ps
T685 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.111178779938024232647600797302499413492031155206134045452141121381626625998203 Nov 22 01:59:46 PM PST 23 Nov 22 02:00:12 PM PST 23 9477310853 ps
T686 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.84250043496047969828230322947556103814142342536213671593859613916780477215991 Nov 22 02:00:16 PM PST 23 Nov 22 02:00:21 PM PST 23 2023227629 ps
T687 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.72162194986582701533281540400394755788047020960052489732543580150704699273847 Nov 22 01:59:44 PM PST 23 Nov 22 02:00:10 PM PST 23 9477310853 ps
T688 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.104313953939277646824249465877884199137131891808151540832111495575003071000985 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:50 PM PST 23 2186637036 ps
T689 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.97640326853259302586881494353678114881141736571183311279720301008703135944470 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:50 PM PST 23 2023227629 ps
T690 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.74015826971439263110380947856440307268199252155205445052371059433131782653763 Nov 22 02:00:11 PM PST 23 Nov 22 02:00:15 PM PST 23 2023227629 ps
T691 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.9912869984659248068105298439658347273519799226373411673363901965806641391021 Nov 22 01:59:54 PM PST 23 Nov 22 02:01:05 PM PST 23 42510939439 ps
T692 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.80974903675931392754028321404332380406005223274711524822091920789073101032430 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:09 PM PST 23 2074977215 ps
T693 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.48489943286474056113309454139827556075866233459009033866177294557566300175528 Nov 22 01:59:56 PM PST 23 Nov 22 02:00:00 PM PST 23 2023227629 ps
T694 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.66688495113112803266568563007477461035544709016181833760716975236948175411036 Nov 22 01:59:46 PM PST 23 Nov 22 02:00:56 PM PST 23 42510939439 ps
T695 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.7742223016851301164392955233435497730775750435524649764106880250388681580744 Nov 22 01:59:56 PM PST 23 Nov 22 02:00:01 PM PST 23 2142012393 ps
T696 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.31704031733207203305342826095010249790689812175576053161602542678718552911838 Nov 22 01:59:32 PM PST 23 Nov 22 01:59:38 PM PST 23 2142012393 ps
T70 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.73722499466168528458520575107394517474040356826980234349055209535764537132631 Nov 22 01:59:54 PM PST 23 Nov 22 02:01:48 PM PST 23 41047879715 ps
T697 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.94596243657214341331437742600654243802875002141390469832073186026362272237108 Nov 22 01:59:54 PM PST 23 Nov 22 02:00:20 PM PST 23 9477310853 ps
T698 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4669094983161490145803698126251942838818587227550463884102691914729065172028 Nov 22 01:59:32 PM PST 23 Nov 22 01:59:39 PM PST 23 2186637036 ps
T699 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.41824406476754677732323960697979255505476524555044498994124855625993464402771 Nov 22 01:59:42 PM PST 23 Nov 22 01:59:48 PM PST 23 2142012393 ps
T700 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.36801331216706816316673716825629053026251744397903473907723023725798645244744 Nov 22 01:59:50 PM PST 23 Nov 22 02:00:15 PM PST 23 9477310853 ps
T701 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.40387396853026572381260004690676097483204321775264475184303987743246138426496 Nov 22 01:59:52 PM PST 23 Nov 22 02:01:01 PM PST 23 42510939439 ps
T702 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.5556319017276153580706380692145562043370625644486870184842872862799769460927 Nov 22 01:59:42 PM PST 23 Nov 22 02:00:08 PM PST 23 9477310853 ps
T703 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.16234518128179067002607299033765908970325472111479956908152507114870103460811 Nov 22 01:59:57 PM PST 23 Nov 22 02:00:02 PM PST 23 2142012393 ps
T704 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.66899655464917302644917542098202949494877611061080391406342760666316115094957 Nov 22 01:59:50 PM PST 23 Nov 22 02:01:01 PM PST 23 42510939439 ps
T705 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.107751379630814716819064915436239301149415242489343478054051875987600734280247 Nov 22 01:59:33 PM PST 23 Nov 22 01:59:39 PM PST 23 2074977215 ps
T706 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.51293233219460973819275675900259536044284451708202968364403912286628507973047 Nov 22 02:00:10 PM PST 23 Nov 22 02:00:15 PM PST 23 2023227629 ps
T71 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.956337567459376386108090460373221334543670486804885907190819188126901252916 Nov 22 01:59:32 PM PST 23 Nov 22 01:59:42 PM PST 23 2890827831 ps
T72 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.53909813656961474735690363747409495756821225776085174733161403313119025267442 Nov 22 01:59:31 PM PST 23 Nov 22 02:01:25 PM PST 23 41047879715 ps
T80 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.78477973136909586805429113926337651861123680813208759615012213126945689522547 Nov 22 01:59:37 PM PST 23 Nov 22 01:59:48 PM PST 23 6030981281 ps
T707 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.100814651162490790865234976471484323436595824943974793537128568865999357640944 Nov 22 02:00:13 PM PST 23 Nov 22 02:00:18 PM PST 23 2023227629 ps
T708 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.69677495927172204460454307214115538243897197794442510385758723445679230737768 Nov 22 01:59:37 PM PST 23 Nov 22 02:00:03 PM PST 23 9477310853 ps
T709 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.47701247139331815005032955890444861684690414636843636157920458732506387927796 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:06 PM PST 23 2023227629 ps
T710 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.87430152517727242087183646770919625280160543890373255439779385283898014186502 Nov 22 01:59:48 PM PST 23 Nov 22 02:00:59 PM PST 23 42510939439 ps
T711 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.68632143673881927472908945252778306666158667800620750278381867002277222080051 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2142012393 ps
T712 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.68526259581387937314634913953838721559698516829462729142130401677195219809116 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:09 PM PST 23 2186637036 ps
T713 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.73786838207904336614238062362058731507776357280272192860738668374170441153747 Nov 22 01:59:55 PM PST 23 Nov 22 01:59:59 PM PST 23 2023227629 ps
T714 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.91448851815740744128704751060568918600928303877305478865029228207803124342081 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:47 PM PST 23 2023227629 ps
T715 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.84259423004071580078071833224497123150046063403755757608476317191609903392557 Nov 22 01:59:53 PM PST 23 Nov 22 01:59:58 PM PST 23 2023227629 ps
T716 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.13325802638815547811350732093605664180942033664195402148219321301054923768564 Nov 22 01:59:48 PM PST 23 Nov 22 01:59:53 PM PST 23 2023227629 ps
T717 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.30516430341693987444917426430458337713790548805806143776828726703759213558084 Nov 22 01:59:56 PM PST 23 Nov 22 02:00:01 PM PST 23 2023227629 ps
T718 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.36964148873696633572439643468834710441752308463238460073234856637313932757445 Nov 22 01:59:48 PM PST 23 Nov 22 01:59:53 PM PST 23 2142012393 ps
T719 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.101243634141421624353518175037839868235540165592769622526680723149099323470762 Nov 22 01:59:52 PM PST 23 Nov 22 01:59:57 PM PST 23 2023227629 ps
T720 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.99291210301995388358075410188162940848185087831679235938617353539001769047631 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2142012393 ps
T721 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.112550972746133786919314622675438806606299190058849067831975937198733398332961 Nov 22 01:59:47 PM PST 23 Nov 22 01:59:53 PM PST 23 2074977215 ps
T722 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.72082951848993311596592254070882417161966886004939270717771907901550756075836 Nov 22 01:59:41 PM PST 23 Nov 22 01:59:46 PM PST 23 2142012393 ps
T723 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.114004067616442616455721983391068507733587726596208525248400054623783673054181 Nov 22 01:59:46 PM PST 23 Nov 22 02:00:55 PM PST 23 42510939439 ps
T724 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.103770893862974691176257255175107390332678054190193096427755904865469472628489 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:50 PM PST 23 2186637036 ps
T725 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.54017042287348132941277431708751529336423953964742396486722894063746693982771 Nov 22 01:59:37 PM PST 23 Nov 22 02:00:47 PM PST 23 42510939439 ps
T726 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.19182923084651250029108671460494243368931621118711065087544396421641881411720 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:52 PM PST 23 2186637036 ps
T727 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.81619054031093331649902623888026056139880157295279839660120893750298523119233 Nov 22 01:59:45 PM PST 23 Nov 22 01:59:56 PM PST 23 6030981281 ps
T728 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.86582981349407543719275668099221415336258853932534645995360671812510447957894 Nov 22 02:00:12 PM PST 23 Nov 22 02:00:17 PM PST 23 2023227629 ps
T729 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.62214541639724831017218591667862531173432501721201740754215210226890548376684 Nov 22 01:59:47 PM PST 23 Nov 22 01:59:52 PM PST 23 2142012393 ps
T730 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.45395546548993456967421341063979133608949775070903090113891008194718142025453 Nov 22 02:00:11 PM PST 23 Nov 22 02:00:15 PM PST 23 2023227629 ps
T73 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.39782437058407450775069024408515702390538024898324821650723097076463239970562 Nov 22 01:59:48 PM PST 23 Nov 22 01:59:58 PM PST 23 2890827831 ps
T731 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.21934342152926725805670880401017778178248409146483455690543720907398586186103 Nov 22 01:59:57 PM PST 23 Nov 22 02:00:02 PM PST 23 2023227629 ps
T732 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.77935057114328085197822832391154323292296231749875755921399657229150078213042 Nov 22 01:59:32 PM PST 23 Nov 22 02:00:42 PM PST 23 42510939439 ps
T733 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.69347151946414998935586909667982005158737309856559959717340135508725994410722 Nov 22 01:59:55 PM PST 23 Nov 22 02:00:01 PM PST 23 2186637036 ps
T734 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3785328837900859128564353767959010807382309259400931453649901984439683469975 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:07 PM PST 23 2023227629 ps
T735 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.74787765266952815717189751525450531812032314038059940025779035113671639937576 Nov 22 02:00:14 PM PST 23 Nov 22 02:00:20 PM PST 23 2023227629 ps
T736 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.103660597453663064822946982879689345907374259228061909353242447265332420532246 Nov 22 01:59:32 PM PST 23 Nov 22 01:59:37 PM PST 23 2023227629 ps
T737 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.10677610076380757320087969037258918239786231361625652274005161201699230104042 Nov 22 01:59:54 PM PST 23 Nov 22 01:59:59 PM PST 23 2142012393 ps
T738 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.85935711364439060153154222892417462361675544592527126220565295075071373589513 Nov 22 01:59:41 PM PST 23 Nov 22 01:59:47 PM PST 23 2074977215 ps
T74 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.11728817438553267977521361538802166650274105526741509239687558504347610789564 Nov 22 01:59:42 PM PST 23 Nov 22 01:59:51 PM PST 23 2890827831 ps
T739 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.45920196375362976949643633231597382451995731848316860700140745676652555098625 Nov 22 01:59:37 PM PST 23 Nov 22 01:59:42 PM PST 23 2142012393 ps
T740 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.71883723760335803263941803480152258083822636510680239249890611273769368256122 Nov 22 01:59:52 PM PST 23 Nov 22 02:00:19 PM PST 23 9477310853 ps
T741 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.107467341526922103261334626575105477518202488917126998587880902287816379985622 Nov 22 01:59:51 PM PST 23 Nov 22 01:59:56 PM PST 23 2142012393 ps
T75 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.37893965303503552116542068165909298518313412327400974700609578032870793052339 Nov 22 01:59:42 PM PST 23 Nov 22 01:59:52 PM PST 23 2890827831 ps
T742 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.46946507866377026458835409722460876755932235597545199676179415621923153680126 Nov 22 01:59:43 PM PST 23 Nov 22 02:00:09 PM PST 23 9477310853 ps
T743 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.22668571478862167842331135947457314447037021307721957940382488184794116760010 Nov 22 01:59:47 PM PST 23 Nov 22 01:59:54 PM PST 23 2186637036 ps
T744 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.69017285838569738830769396631857938566507511822390528050894335319887248663770 Nov 22 01:59:42 PM PST 23 Nov 22 01:59:47 PM PST 23 2142012393 ps
T745 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.65883912910868704817266480695560453909326063339588395722369884652388925745282 Nov 22 01:59:53 PM PST 23 Nov 22 01:59:57 PM PST 23 2023227629 ps
T746 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.21365314994637464260213428555319397863306573606661387266322459463533082122892 Nov 22 01:59:55 PM PST 23 Nov 22 02:00:00 PM PST 23 2074977215 ps
T747 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.74142220456430494130406285527757370638913493378204292291464485115287316450142 Nov 22 01:59:44 PM PST 23 Nov 22 01:59:49 PM PST 23 2074977215 ps
T748 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.15960448085253981915162556264399862393753484621648284770579415324960601582271 Nov 22 01:59:46 PM PST 23 Nov 22 02:00:56 PM PST 23 42510939439 ps
T749 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.73351079380146027845196221414317205679726392067575917390016996888606914971587 Nov 22 01:59:53 PM PST 23 Nov 22 01:59:57 PM PST 23 2023227629 ps
T750 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.37856157601351511625275858916403918846315428960527262983503751694315978641325 Nov 22 01:59:36 PM PST 23 Nov 22 01:59:41 PM PST 23 2023227629 ps
T751 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.956306008654628333948996444915865488069515793846064728592446581378483618624 Nov 22 01:59:43 PM PST 23 Nov 22 02:00:09 PM PST 23 9477310853 ps
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