Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T752 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.26464957395146006919345302981641832162757344622706158067189861845409030636611 Nov 22 01:59:43 PM PST 23 Nov 22 02:00:09 PM PST 23 9477310853 ps
T753 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.53072631154035804797802368361573734377790152180413609067712344850429524394374 Nov 22 01:59:43 PM PST 23 Nov 22 02:00:10 PM PST 23 9477310853 ps
T754 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.91303132649361255641870240113727768290857662952074987976456693452709033286046 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:07 PM PST 23 2074977215 ps
T755 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.51524910691068517540989917878891177632452836370973539843246452830599504183368 Nov 22 02:00:13 PM PST 23 Nov 22 02:00:19 PM PST 23 2023227629 ps
T756 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.46160643237577970650452711366317020494829409292244239160921152681339356758230 Nov 22 01:59:49 PM PST 23 Nov 22 01:59:54 PM PST 23 2023227629 ps
T757 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.89054976711565942737632069520020485362434332690750781456847656890089136640155 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:06 PM PST 23 2023227629 ps
T758 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.66549912984140664212302648094395837063057576259991300152200353628946232653684 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:07 PM PST 23 2023227629 ps
T759 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.38974712017032126458734530943545077055987531190369125612414188575006786113568 Nov 22 02:00:01 PM PST 23 Nov 22 02:00:06 PM PST 23 2023227629 ps
T760 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.41272491369695682892591573729262127396284119348632232172237238351336901295011 Nov 22 02:00:02 PM PST 23 Nov 22 02:00:07 PM PST 23 2023227629 ps
T761 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.24986328332262689066479035983948052392759816243533062362422403865786744008486 Nov 22 01:59:47 PM PST 23 Nov 22 02:00:57 PM PST 23 42510939439 ps
T762 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.4770772585657335543949803968322577119105618058825219181901819712939747146301 Nov 22 02:00:12 PM PST 23 Nov 22 02:00:17 PM PST 23 2023227629 ps
T763 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.51940009274683980779597308764325745697420127847067522029933693481961254486522 Nov 22 01:59:42 PM PST 23 Nov 22 02:00:07 PM PST 23 9477310853 ps
T764 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.78040977000847590549023155723892623584679941364773224531860104529510565807350 Nov 22 01:59:55 PM PST 23 Nov 22 02:00:21 PM PST 23 9477310853 ps
T765 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.37021857235211104617006321908583022142695566599971678410884001552361635191334 Nov 22 02:00:00 PM PST 23 Nov 22 02:00:05 PM PST 23 2023227629 ps
T766 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.49969543464788220145658063218098322265915387125235815927652140903223645682320 Nov 22 01:59:44 PM PST 23 Nov 22 02:00:55 PM PST 23 42510939439 ps
T767 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.85863667765613895552334769973181079335557632926818369495750829597955654681130 Nov 22 01:59:44 PM PST 23 Nov 22 01:59:49 PM PST 23 2142012393 ps
T768 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.16635724686910351350543530386156998878645751846505653202616422850611410908389 Nov 22 01:59:47 PM PST 23 Nov 22 02:00:57 PM PST 23 42510939439 ps
T769 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.112683119506732451563541608528239144503874124270633121047071841855939801863451 Nov 22 01:59:43 PM PST 23 Nov 22 01:59:48 PM PST 23 2023227629 ps
T770 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.71702001983363181351332949188790318744858838743719938639398079402357807580284 Nov 22 01:59:51 PM PST 23 Nov 22 01:59:58 PM PST 23 2186637036 ps
T771 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.98428424107612868489861085191614008120968577276635662072295985619263670457169 Nov 22 01:59:53 PM PST 23 Nov 22 01:59:58 PM PST 23 2074977215 ps
T76 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.95408508709552472305991500624547734846087434090645355468424508637375254730891 Nov 22 01:59:37 PM PST 23 Nov 22 02:01:30 PM PST 23 41047879715 ps
T772 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.111825858044261487464509511837836837167926476937177377897237005565234813453954 Nov 22 01:59:44 PM PST 23 Nov 22 01:59:49 PM PST 23 2074977215 ps
T773 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.87744771026983132984732333536269614856653272048942105527138525691485930645936 Nov 22 01:59:56 PM PST 23 Nov 22 02:00:03 PM PST 23 2186637036 ps
T774 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.47076813332371469038518684358052632884753123215309334294674643741942344249257 Nov 22 01:59:48 PM PST 23 Nov 22 01:59:53 PM PST 23 2023227629 ps
T775 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.104749794119925680051768821803341235132274838274986112396284718006130611662650 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2023227629 ps
T776 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.29262085462782530466770904920819404133503965102891098153031527004553679065131 Nov 22 01:59:47 PM PST 23 Nov 22 02:00:58 PM PST 23 42510939439 ps
T777 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.32313760745808230675668292032850551454309779109332146524500026672194978324458 Nov 22 02:00:11 PM PST 23 Nov 22 02:00:15 PM PST 23 2023227629 ps
T778 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.86173304029252121504946591236772258527862155651004643350684244654201853190512 Nov 22 01:59:55 PM PST 23 Nov 22 02:00:00 PM PST 23 2142012393 ps
T779 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.57568727542931280202592668714231456301033775134063972603870168860970582044669 Nov 22 01:59:57 PM PST 23 Nov 22 02:00:23 PM PST 23 9477310853 ps
T780 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.739509534266036659146039421370603614470192630786590670652135322239313706883 Nov 22 01:59:46 PM PST 23 Nov 22 01:59:51 PM PST 23 2074977215 ps
T781 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.92818638945404510019888315062542346962092283219684516220389172032971275401286 Nov 22 01:59:43 PM PST 23 Nov 22 02:00:53 PM PST 23 42510939439 ps
T782 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.5558622955757463489004235215312559198391033492752405786796822280944075766491 Nov 22 01:59:57 PM PST 23 Nov 22 02:00:02 PM PST 23 2074977215 ps

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.12934256646772931310499220431026537748995762527320788716355900099479005825194
Short name T22
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.27 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 201436 kb
Host smart-6c1acafb-fd79-43d6-a538-6cef9f6aa554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934256646772931310499220431026537748995762527320788716355900099479005825194 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.12934256646772931310499220431026537748995762527320788716355900099479005825194
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.43072072716394688349426244558646073394160009535902372924620895554744364709231
Short name T84
Test name
Test status
Simulation time 38606274248 ps
CPU time 59.88 seconds
Started Nov 22 01:23:24 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201204 kb
Host smart-e072ed3c-b09d-4d15-92c4-668908136cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43072072716394688349426244558646073394160009535902372924620895554744364709231 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.43072072716394688349426244558646073394160009535902372924620895554744364709231
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.76613344947148257527948372201324836226500765129883973194727513557112098663349
Short name T1
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.24 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:01:11 PM PST 23
Peak memory 201216 kb
Host smart-f6d41ab4-ef73-4b29-9c27-18b4e48cc987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76613344947148257527948372201324836226500765129883973194727513557112098663349 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.76613344947148257527948372201324836226500765129883973194727513
557112098663349
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.48493962606939249483598531406236598265587654290113982750323063454809547796602
Short name T16
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 22 01:24:46 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 201172 kb
Host smart-759f91a8-d1a4-411a-8ad8-b93c0355af0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48493962606939249483598531406236598265587654290113982750323063454809547796602 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.484939626069392494835985314062365982655876542901139827503230
63454809547796602
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.51267985052205319599850113896676270009553272576873084532968207724688708215449
Short name T27
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.83 seconds
Started Nov 22 01:24:02 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 201444 kb
Host smart-546a4aff-1fe6-453c-998f-f336621b5d71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51267985052205319599850113896676270009553272576873084532968207724688708215449 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.51267985052205319599850113896676270009553272576873084532968207
724688708215449
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.64417082359289775293783404959105731974945176347660402511250147287147561570842
Short name T5
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.83 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201228 kb
Host smart-5ad11239-a316-4a9a-a589-aff217d99bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64417082359289775293783404959105731974945176347660402511250147287147561570842 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.64417082359289775293783404959105731974945176347660402511250147287147561570842
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.21482136972964818410098480506066965175249643707899428959144224157651511411884
Short name T38
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.06 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 221548 kb
Host smart-a4d8d558-f583-4404-9ad4-49bb71c6cc11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482136972964818410098480506066965175249643707899428959144224157651511411884 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.21482136972964818410098480506066965175249643707899428959144224157651511411884
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.11570050201637319033761418642852806086135340766939756303590888401885911908409
Short name T90
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.58 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201232 kb
Host smart-eae9cebe-35e6-4dd8-87c0-9d3d315b08ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11570050201637319033761418642852806086135340766939756303590888401885911908409 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.11570050201637319033761418642852806086135340766939756303590888401885911908409
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.14575037751741014874237078357030835096178352911034308876787009369915567077070
Short name T81
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.65 seconds
Started Nov 22 01:59:34 PM PST 23
Finished Nov 22 02:00:00 PM PST 23
Peak memory 201216 kb
Host smart-26c850dd-4d84-498b-9b81-0b25276583b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14575037751741014874237078357030835096178352911034308876787009369915567077070
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.145750377517410148742370783570308350961783529
11034308876787009369915567077070
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.81284665138354430559454508170960259395662335880403078784843850997542374045884
Short name T119
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 201200 kb
Host smart-77f81b22-949e-4d71-add7-ed14b3406475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81284665138354430559454508170960259395662335880403078784843850997542374045884 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.81284665138354430559454508170960259395662335880403078784843850997542374045884
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.73127072256862930533710834903982559167612283665769364231444869665627279112025
Short name T40
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201148 kb
Host smart-4d9e0798-b8b3-4410-bc38-25df2f1b8866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73127072256862930533710834903982559167612283665769364231444869665627279112025 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.73127072256862930533710834903982559167612283665769364231444869665627279112025
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.96365626082838518244669226586428850852615290297545098454381573270963875239397
Short name T15
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Nov 22 01:59:50 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201008 kb
Host smart-f9062d05-1687-41c9-a444-1e297fb1f9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96365626082838518244669226586428850852615290297545098454381573270963875239397 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.96365626082838518244669226586428850852615290297545098454381573270963875239397
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.15578048520097713755481725134765154063082262795799962668976488499790399785091
Short name T58
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.42 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 201052 kb
Host smart-15711c72-845a-4d54-b2a9-e38d384b67b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578048520097713755481725134765154063082262795799962668976488499790399785091 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.15578048520097713755481725134765154063082262795799962668976488499790399785091
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.51329652852069125153801108283426688131955180534227982973174495200784467961732
Short name T171
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 22 01:24:07 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 201132 kb
Host smart-08f1cdd2-00ea-4e54-92e3-755cbf10799b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51329652852069125153801108283426688131955180534227982973174495200784467961732 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.51329652852069125153801108283426688131955180534227982973174495200784467961732
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.109556358840783881044778376049728316687267492773500888037206091380229011890630
Short name T369
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.31 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201236 kb
Host smart-e3b3c300-1182-456b-8ae8-51ca64dd61fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109556358840783881044778376049728316687267492773500888037206091380229011890630 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.109556358840783881044778376049728316687267492773500888037206091380229011890630
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.90149135399196270834780145737244970208463550991167653819819882121718175714918
Short name T100
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Nov 22 01:23:53 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201208 kb
Host smart-de4f6450-4801-4fe5-9ec4-0554d8890094
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90149135399196270834780145737244970208463550991167653819819882121718175714918 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.901491353991962708347801457372449702084635509911676538198198
82121718175714918
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.37893965303503552116542068165909298518313412327400974700609578032870793052339
Short name T75
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.91 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 201280 kb
Host smart-88941060-6b7e-40e7-b3bc-acd9eea063e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37893965303503552116542068165909298518313412327400974700609578032870793052339 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.37893965303503552116542068165909298518313412327400974700609578032870793052339
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.53909813656961474735690363747409495756821225776085174733161403313119025267442
Short name T72
Test name
Test status
Simulation time 41047879715 ps
CPU time 112.78 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:01:25 PM PST 23
Peak memory 201232 kb
Host smart-06d06171-1c0f-4229-8ff6-976945c629d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53909813656961474735690363747409495756821225776085174733161403313119025267442 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.53909813656961474735690363747409495756821225776085174733161403313119025267442
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.96663295569600755109953617200752786429879401641598864860878149145560034656307
Short name T56
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.07 seconds
Started Nov 22 01:59:41 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 201076 kb
Host smart-05e299e1-5280-4880-a434-99ca7fb9c8e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96663295569600755109953617200752786429879401641598864860878149145560034656307 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.96663295569600755109953617200752786429879401641598864860878149145560034656307
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.31704031733207203305342826095010249790689812175576053161602542678718552911838
Short name T696
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.2 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 01:59:38 PM PST 23
Peak memory 201124 kb
Host smart-63fe11cb-646c-4864-a3ad-60b30444aa88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170403173320720330534282609501024979068981
2175576053161602542678718552911838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3170
4031733207203305342826095010249790689812175576053161602542678718552911838
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.85935711364439060153154222892417462361675544592527126220565295075071373589513
Short name T738
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Nov 22 01:59:41 PM PST 23
Finished Nov 22 01:59:47 PM PST 23
Peak memory 200992 kb
Host smart-53abe28e-2d2c-4510-896c-fed9bfc56c52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85935711364439060153154222892417462361675544592527126220565295075071373589513 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.85935711364439060153154222892417462361675544592527126220565295075071373589513
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.103660597453663064822946982879689345907374259228061909353242447265332420532246
Short name T736
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 01:59:37 PM PST 23
Peak memory 201000 kb
Host smart-96f3cb75-103b-4107-b320-93ee50f1118f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103660597453663064822946982879689345907374259228061909353242447265332420532246 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.103660597453663064822946982879689345907374259228061909353242447265332420532246
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4669094983161490145803698126251942838818587227550463884102691914729065172028
Short name T698
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 01:59:39 PM PST 23
Peak memory 201288 kb
Host smart-f5ac161d-e1f5-48ef-a0da-33851c588a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4669094983161490145803698126251942838818587227550463884102691914729065172028 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.4669094983161490145803698126251942838818587227550463884102691914729065172028
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.77935057114328085197822832391154323292296231749875755921399657229150078213042
Short name T732
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.69 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:00:42 PM PST 23
Peak memory 201240 kb
Host smart-6bb48c51-3de3-4b3a-b671-4482fa14c6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77935057114328085197822832391154323292296231749875755921399657229150078213042 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.779350571143280851978228323911543232922962317498757559213996572
29150078213042
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.39782437058407450775069024408515702390538024898324821650723097076463239970562
Short name T73
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.56 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 01:59:58 PM PST 23
Peak memory 201224 kb
Host smart-63645018-8680-49b5-befb-c26c27d7095a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782437058407450775069024408515702390538024898324821650723097076463239970562 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.39782437058407450775069024408515702390538024898324821650723097076463239970562
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.28539750770612306990918227747239861328922965452627270394584118156154410348132
Short name T68
Test name
Test status
Simulation time 41047879715 ps
CPU time 108.68 seconds
Started Nov 22 01:59:51 PM PST 23
Finished Nov 22 02:01:41 PM PST 23
Peak memory 201216 kb
Host smart-11227574-98b6-4823-a653-c8bc3ad09435
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539750770612306990918227747239861328922965452627270394584118156154410348132 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.28539750770612306990918227747239861328922965452627270394584118156154410348132
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.78477973136909586805429113926337651861123680813208759615012213126945689522547
Short name T80
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.94 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 201048 kb
Host smart-113e8f42-dafc-4868-98e9-adb0e762fd17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78477973136909586805429113926337651861123680813208759615012213126945689522547 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.78477973136909586805429113926337651861123680813208759615012213126945689522547
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.31244971254050592891260325932395169196689927723870125322167673143661961710723
Short name T65
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.14 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 201184 kb
Host smart-ff8f5513-7976-4f27-b175-b7ad49af170a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124497125405059289126032593239516919668992
7723870125322167673143661961710723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3124
4971254050592891260325932395169196689927723870125322167673143661961710723
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.107751379630814716819064915436239301149415242489343478054051875987600734280247
Short name T705
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Nov 22 01:59:33 PM PST 23
Finished Nov 22 01:59:39 PM PST 23
Peak memory 201044 kb
Host smart-53f57abc-9b07-494b-9ef2-d90b60d13cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107751379630814716819064915436239301149415242489343478054051875987600734280247 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.107751379630814716819064915436239301149415242489343478054051875987600734280247
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.97640326853259302586881494353678114881141736571183311279720301008703135944470
Short name T689
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 200980 kb
Host smart-a53f477e-301a-4e52-998f-8d566fc2b054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97640326853259302586881494353678114881141736571183311279720301008703135944470 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.97640326853259302586881494353678114881141736571183311279720301008703135944470
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.26464957395146006919345302981641832162757344622706158067189861845409030636611
Short name T752
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.69 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 201204 kb
Host smart-e1c5514d-e094-4e64-ab2c-c24421ccefa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26464957395146006919345302981641832162757344622706158067189861845409030636611
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.264649573951460069193453029816418321627573446
22706158067189861845409030636611
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.71702001983363181351332949188790318744858838743719938639398079402357807580284
Short name T770
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.74 seconds
Started Nov 22 01:59:51 PM PST 23
Finished Nov 22 01:59:58 PM PST 23
Peak memory 200640 kb
Host smart-b86e5cbd-936c-48b7-bae6-61b62c8f2722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71702001983363181351332949188790318744858838743719938639398079402357807580284 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.71702001983363181351332949188790318744858838743719938639398079402357807580284
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.83868418391162035348017618905652858921938236621962455037489293897427984317350
Short name T8
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.52 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 02:00:39 PM PST 23
Peak memory 201312 kb
Host smart-afcfce3c-5718-49bf-8df8-4c9017e0aa95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83868418391162035348017618905652858921938236621962455037489293897427984317350 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.838684183911620353480176189056528589219382366219624550374892938
97427984317350
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.41824406476754677732323960697979255505476524555044498994124855625993464402771
Short name T699
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.25 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 201000 kb
Host smart-0d67e2b7-d29d-4995-8134-589a7e219248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182440647675467773232396069797925550547652
4555044498994124855625993464402771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.418
24406476754677732323960697979255505476524555044498994124855625993464402771
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.74142220456430494130406285527757370638913493378204292291464485115287316450142
Short name T747
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Nov 22 01:59:44 PM PST 23
Finished Nov 22 01:59:49 PM PST 23
Peak memory 201000 kb
Host smart-e59fed0a-1832-49cc-bf98-074c0809e812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74142220456430494130406285527757370638913493378204292291464485115287316450142 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.74142220456430494130406285527757370638913493378204292291464485115287316450142
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.88432128869334907458937760993967006477604836646875086755766236904307500295283
Short name T679
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 200980 kb
Host smart-6ae1a80b-4b81-4bba-ab5c-7555b143156b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88432128869334907458937760993967006477604836646875086755766236904307500295283 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.88432128869334907458937760993967006477604836646875086755766236904307500295283
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.72162194986582701533281540400394755788047020960052489732543580150704699273847
Short name T687
Test name
Test status
Simulation time 9477310853 ps
CPU time 25 seconds
Started Nov 22 01:59:44 PM PST 23
Finished Nov 22 02:00:10 PM PST 23
Peak memory 201272 kb
Host smart-3764dcd4-a09c-4f0b-917e-7171b9670954
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72162194986582701533281540400394755788047020960052489732543580150704699273847
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.72162194986582701533281540400394755788047020
960052489732543580150704699273847
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.15960448085253981915162556264399862393753484621648284770579415324960601582271
Short name T748
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.6 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 02:00:56 PM PST 23
Peak memory 201352 kb
Host smart-9e2ea509-817d-42bd-b60a-441f47e8ea5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15960448085253981915162556264399862393753484621648284770579415324960601582271 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.15960448085253981915162556264399862393753484621648284770579415
324960601582271
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.60518551795498200295059245077803014717426446268845886231221158821306893818906
Short name T683
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201108 kb
Host smart-b1dab063-ebec-4e5f-900e-5084028c3b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6051855179549820029505924507780301471742644
6268845886231221158821306893818906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.605
18551795498200295059245077803014717426446268845886231221158821306893818906
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.5558622955757463489004235215312559198391033492752405786796822280944075766491
Short name T782
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Nov 22 01:59:57 PM PST 23
Finished Nov 22 02:00:02 PM PST 23
Peak memory 201072 kb
Host smart-a95f654b-31e7-4e9f-887f-8d14f9d17669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5558622955757463489004235215312559198391033492752405786796822280944075766491 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.5558622955757463489004235215312559198391033492752405786796822280944075766491
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.13325802638815547811350732093605664180942033664195402148219321301054923768564
Short name T716
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 01:59:53 PM PST 23
Peak memory 201016 kb
Host smart-7e17a208-a7a8-49e3-b786-b78835a15fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13325802638815547811350732093605664180942033664195402148219321301054923768564 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.13325802638815547811350732093605664180942033664195402148219321301054923768564
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.57568727542931280202592668714231456301033775134063972603870168860970582044669
Short name T779
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.73 seconds
Started Nov 22 01:59:57 PM PST 23
Finished Nov 22 02:00:23 PM PST 23
Peak memory 201284 kb
Host smart-d78dd70f-1cd3-400b-b660-69463187c262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57568727542931280202592668714231456301033775134063972603870168860970582044669
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.57568727542931280202592668714231456301033775
134063972603870168860970582044669
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.22668571478862167842331135947457314447037021307721957940382488184794116760010
Short name T743
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.65 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201268 kb
Host smart-f07d367c-1ef4-4826-816c-53c5e04ece92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22668571478862167842331135947457314447037021307721957940382488184794116760010 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.22668571478862167842331135947457314447037021307721957940382488184794116760010
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.47702346009634622472478379966723943537394695791116700411349767210377594505685
Short name T677
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.44 seconds
Started Nov 22 01:59:51 PM PST 23
Finished Nov 22 02:01:01 PM PST 23
Peak memory 201300 kb
Host smart-01416334-dd3a-44f8-9180-31404651ce94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47702346009634622472478379966723943537394695791116700411349767210377594505685 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.47702346009634622472478379966723943537394695791116700411349767
210377594505685
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.36964148873696633572439643468834710441752308463238460073234856637313932757445
Short name T718
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 01:59:53 PM PST 23
Peak memory 201056 kb
Host smart-48d1ac92-4804-42bc-9910-73affc9a7784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696414887369663357243964346883471044175230
8463238460073234856637313932757445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.369
64148873696633572439643468834710441752308463238460073234856637313932757445
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.33421121224783141098633870359372530548072570933145829474536683480997770550609
Short name T55
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201060 kb
Host smart-4cd2d275-9696-4139-ae37-00d2cea7c224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33421121224783141098633870359372530548072570933145829474536683480997770550609 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.33421121224783141098633870359372530548072570933145829474536683480997770550609
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.78040977000847590549023155723892623584679941364773224531860104529510565807350
Short name T764
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.83 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 201332 kb
Host smart-ba13aae3-f96f-4510-93a9-e7d34fb7bd22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78040977000847590549023155723892623584679941364773224531860104529510565807350
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.78040977000847590549023155723892623584679941
364773224531860104529510565807350
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.11528409178246421945174215936945878513714844878981988654547711265061678924537
Short name T4
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.86 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:10 PM PST 23
Peak memory 201212 kb
Host smart-ccbe5a1a-dd60-4bc9-8b8a-7beccd012fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528409178246421945174215936945878513714844878981988654547711265061678924537 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.11528409178246421945174215936945878513714844878981988654547711265061678924537
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.24986328332262689066479035983948052392759816243533062362422403865786744008486
Short name T761
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.8 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 02:00:57 PM PST 23
Peak memory 201312 kb
Host smart-1650c824-00da-4ae9-8830-eb75c5586f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24986328332262689066479035983948052392759816243533062362422403865786744008486 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.24986328332262689066479035983948052392759816243533062362422403
865786744008486
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.86173304029252121504946591236772258527862155651004643350684244654201853190512
Short name T778
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.2 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 02:00:00 PM PST 23
Peak memory 201180 kb
Host smart-243d1a62-89f3-4f5f-9b40-d7f498153dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8617330402925212150494659123677225852786215
5651004643350684244654201853190512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.861
73304029252121504946591236772258527862155651004643350684244654201853190512
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.80974903675931392754028321404332380406005223274711524822091920789073101032430
Short name T692
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.09 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 200364 kb
Host smart-f521c545-32d6-46e3-919a-b67811e8aba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80974903675931392754028321404332380406005223274711524822091920789073101032430 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.80974903675931392754028321404332380406005223274711524822091920789073101032430
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.21934342152926725805670880401017778178248409146483455690543720907398586186103
Short name T731
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 01:59:57 PM PST 23
Finished Nov 22 02:00:02 PM PST 23
Peak memory 201044 kb
Host smart-ee01fb31-1788-4978-a531-360eaf427be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21934342152926725805670880401017778178248409146483455690543720907398586186103 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.21934342152926725805670880401017778178248409146483455690543720907398586186103
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.36801331216706816316673716825629053026251744397903473907723023725798645244744
Short name T700
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.2 seconds
Started Nov 22 01:59:50 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 201276 kb
Host smart-2f0363b5-8cda-4611-aedd-6352b136fe68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801331216706816316673716825629053026251744397903473907723023725798645244744
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.36801331216706816316673716825629053026251744
397903473907723023725798645244744
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2637418192611674421405876952140363997525878649658394074242067524176361055810
Short name T49
Test name
Test status
Simulation time 2186637036 ps
CPU time 6.02 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:11 PM PST 23
Peak memory 201220 kb
Host smart-dd25b5c4-2640-48ee-acc4-08b70b4598d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637418192611674421405876952140363997525878649658394074242067524176361055810 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.2637418192611674421405876952140363997525878649658394074242067524176361055810
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.66688495113112803266568563007477461035544709016181833760716975236948175411036
Short name T694
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.49 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 02:00:56 PM PST 23
Peak memory 201412 kb
Host smart-53a65218-35cf-46e7-9d06-3b631587de7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66688495113112803266568563007477461035544709016181833760716975236948175411036 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.66688495113112803266568563007477461035544709016181833760716975
236948175411036
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.99291210301995388358075410188162940848185087831679235938617353539001769047631
Short name T720
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.26 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201120 kb
Host smart-76ae6f96-512f-4f10-a48a-1c430902a51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9929121030199538835807541018816294084818508
7831679235938617353539001769047631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.992
91210301995388358075410188162940848185087831679235938617353539001769047631
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.13201490696276360275529794068825016718342584597846456468955948889242009174888
Short name T52
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201060 kb
Host smart-e5083490-90bb-43e4-96c7-2a18858e4541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201490696276360275529794068825016718342584597846456468955948889242009174888 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.13201490696276360275529794068825016718342584597846456468955948889242009174888
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.38974712017032126458734530943545077055987531190369125612414188575006786113568
Short name T759
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:06 PM PST 23
Peak memory 200936 kb
Host smart-075cc6d0-455e-4c35-b4cc-ee0a3b3ee3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38974712017032126458734530943545077055987531190369125612414188575006786113568 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.38974712017032126458734530943545077055987531190369125612414188575006786113568
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.111178779938024232647600797302499413492031155206134045452141121381626625998203
Short name T685
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.48 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 02:00:12 PM PST 23
Peak memory 201080 kb
Host smart-7f92db0e-7b8d-4fe3-a208-36e6a1188af7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111178779938024232647600797302499413492031155206134045452141121381626625998203
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.1111787799380242326476007973024994134920311
55206134045452141121381626625998203
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.45565201354709826753779787597237820642296346477944647312357882832563963301549
Short name T9
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.72 seconds
Started Nov 22 01:59:50 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 201276 kb
Host smart-ce8b95ce-1b5c-4a24-bdf5-6717c781e49f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45565201354709826753779787597237820642296346477944647312357882832563963301549 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.45565201354709826753779787597237820642296346477944647312357882832563963301549
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.39508805517111209565705365931323525443001517579809995299717926768910466401782
Short name T671
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.52 seconds
Started Nov 22 01:59:56 PM PST 23
Finished Nov 22 02:01:05 PM PST 23
Peak memory 201380 kb
Host smart-44540756-2798-4110-9682-c458127b5fc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39508805517111209565705365931323525443001517579809995299717926768910466401782 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.39508805517111209565705365931323525443001517579809995299717926
768910466401782
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.16234518128179067002607299033765908970325472111479956908152507114870103460811
Short name T703
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Nov 22 01:59:57 PM PST 23
Finished Nov 22 02:00:02 PM PST 23
Peak memory 201140 kb
Host smart-97b28e3b-892d-4508-b885-47045053f0e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623451812817906700260729903376590897032547
2111479956908152507114870103460811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.162
34518128179067002607299033765908970325472111479956908152507114870103460811
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.92849341070029711189817659338773825657917217228856367431992280345386825706052
Short name T14
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Nov 22 01:59:51 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 201052 kb
Host smart-0e748cf5-116c-41df-a28f-93a154b823f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92849341070029711189817659338773825657917217228856367431992280345386825706052 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.92849341070029711189817659338773825657917217228856367431992280345386825706052
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.30516430341693987444917426430458337713790548805806143776828726703759213558084
Short name T717
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 22 01:59:56 PM PST 23
Finished Nov 22 02:00:01 PM PST 23
Peak memory 201044 kb
Host smart-6d4fbf1a-3f88-4f80-b6ad-42efb42fedad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30516430341693987444917426430458337713790548805806143776828726703759213558084 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.30516430341693987444917426430458337713790548805806143776828726703759213558084
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.115719468044813235912271178997442223737835008264453544559971898906128469801286
Short name T672
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.1 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 02:00:14 PM PST 23
Peak memory 201272 kb
Host smart-ebbfae27-f371-4c64-ab96-db86d73e32f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115719468044813235912271178997442223737835008264453544559971898906128469801286
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.1157194680448132359122711789974422237378350
08264453544559971898906128469801286
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.111839889127917421934919047269708440067322320160213560308713999884008888273180
Short name T676
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.76 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 01:59:55 PM PST 23
Peak memory 201300 kb
Host smart-efb4a5db-8331-47ae-ad06-ef9da89797ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111839889127917421934919047269708440067322320160213560308713999884008888273180 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.111839889127917421934919047269708440067322320160213560308713999884008888273180
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.66899655464917302644917542098202949494877611061080391406342760666316115094957
Short name T704
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.33 seconds
Started Nov 22 01:59:50 PM PST 23
Finished Nov 22 02:01:01 PM PST 23
Peak memory 201332 kb
Host smart-32d105e8-c0f4-45a5-b7f7-1464af3d86b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66899655464917302644917542098202949494877611061080391406342760666316115094957 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.66899655464917302644917542098202949494877611061080391406342760
666316115094957
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.93629444931877587792038271596981773196251072868362355589347638578037533494303
Short name T7
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:06 PM PST 23
Peak memory 201060 kb
Host smart-b6139939-8cd0-4aa0-8ea3-9c6e84cce4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9362944493187758779203827159698177319625107
2868362355589347638578037533494303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.936
29444931877587792038271596981773196251072868362355589347638578037533494303
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.15045062331641842660019214959123638622488809932475000640415723541544715374207
Short name T54
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.1 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201068 kb
Host smart-01c424e7-5ea3-49af-9106-db23ca60ba03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15045062331641842660019214959123638622488809932475000640415723541544715374207 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.15045062331641842660019214959123638622488809932475000640415723541544715374207
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3785328837900859128564353767959010807382309259400931453649901984439683469975
Short name T734
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 200944 kb
Host smart-e8b48103-a058-4580-a71d-c1b7ca2bc6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785328837900859128564353767959010807382309259400931453649901984439683469975 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.3785328837900859128564353767959010807382309259400931453649901984439683469975
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.29903050874724050788367950233225244925621525049654435427178518642056773866614
Short name T61
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.7 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 02:00:20 PM PST 23
Peak memory 201332 kb
Host smart-59992f82-363d-42d7-9a7d-ac0135a4f385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29903050874724050788367950233225244925621525049654435427178518642056773866614
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.29903050874724050788367950233225244925621525
049654435427178518642056773866614
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.39568446163237412494304220174953781156120132395622890585309281282271320568185
Short name T3
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.8 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:53 PM PST 23
Peak memory 201296 kb
Host smart-c35ddf69-7fa6-4511-9b1a-b4fd3198e2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568446163237412494304220174953781156120132395622890585309281282271320568185 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.39568446163237412494304220174953781156120132395622890585309281282271320568185
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.16635724686910351350543530386156998878645751846505653202616422850611410908389
Short name T768
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.26 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 02:00:57 PM PST 23
Peak memory 201296 kb
Host smart-271afc9a-dcce-46aa-95c0-23f0fdc60d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16635724686910351350543530386156998878645751846505653202616422850611410908389 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.16635724686910351350543530386156998878645751846505653202616422
850611410908389
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.10677610076380757320087969037258918239786231361625652274005161201699230104042
Short name T737
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 201088 kb
Host smart-70bcb73f-35a7-4332-860f-3f86e49f1466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067761007638075732008796903725891823978623
1361625652274005161201699230104042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.106
77610076380757320087969037258918239786231361625652274005161201699230104042
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.91303132649361255641870240113727768290857662952074987976456693452709033286046
Short name T754
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.1 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 200876 kb
Host smart-1cbcf71d-ced8-4964-9de6-b5c78a29d388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91303132649361255641870240113727768290857662952074987976456693452709033286046 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.91303132649361255641870240113727768290857662952074987976456693452709033286046
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.27104788414013300699556920234863912917978016417892951110436089912220517051638
Short name T67
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 200480 kb
Host smart-9600247e-e62d-47f3-840b-ace84c574996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104788414013300699556920234863912917978016417892951110436089912220517051638 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.27104788414013300699556920234863912917978016417892951110436089912220517051638
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.51179200521724965161382570283629806552270962124055913571106180533427337164812
Short name T684
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.09 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 02:00:19 PM PST 23
Peak memory 201244 kb
Host smart-dff09c10-5d04-4ff1-975f-5d910688e66e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51179200521724965161382570283629806552270962124055913571106180533427337164812
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.51179200521724965161382570283629806552270962
124055913571106180533427337164812
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.68526259581387937314634913953838721559698516829462729142130401677195219809116
Short name T712
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.76 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 201164 kb
Host smart-1acfff19-d4fc-4f7d-a18b-6e209e7e9541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68526259581387937314634913953838721559698516829462729142130401677195219809116 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.68526259581387937314634913953838721559698516829462729142130401677195219809116
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.107467341526922103261334626575105477518202488917126998587880902287816379985622
Short name T741
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.17 seconds
Started Nov 22 01:59:51 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 201036 kb
Host smart-2eafbe0f-f65a-4aaf-856a-dcd601ca95ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074673415269221032613346265751054775182024
88917126998587880902287816379985622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.10
7467341526922103261334626575105477518202488917126998587880902287816379985622
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.21365314994637464260213428555319397863306573606661387266322459463533082122892
Short name T746
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 02:00:00 PM PST 23
Peak memory 201044 kb
Host smart-9f2dc9f2-10ca-4e2d-8fc0-205e6df40d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21365314994637464260213428555319397863306573606661387266322459463533082122892 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.21365314994637464260213428555319397863306573606661387266322459463533082122892
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.77771832661760373843313970720223036015248835935375176933618953944693534183960
Short name T12
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 200908 kb
Host smart-548aea75-6198-49a6-b9b8-1ea8cb421934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77771832661760373843313970720223036015248835935375176933618953944693534183960 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.77771832661760373843313970720223036015248835935375176933618953944693534183960
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.71883723760335803263941803480152258083822636510680239249890611273769368256122
Short name T740
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.45 seconds
Started Nov 22 01:59:52 PM PST 23
Finished Nov 22 02:00:19 PM PST 23
Peak memory 201252 kb
Host smart-57939099-0ef5-4339-a014-50c67142ace2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71883723760335803263941803480152258083822636510680239249890611273769368256122
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.71883723760335803263941803480152258083822636
510680239249890611273769368256122
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.69347151946414998935586909667982005158737309856559959717340135508725994410722
Short name T733
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.88 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 02:00:01 PM PST 23
Peak memory 201252 kb
Host smart-682cb0eb-1b7d-4f15-aba1-5eec56a65f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69347151946414998935586909667982005158737309856559959717340135508725994410722 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.69347151946414998935586909667982005158737309856559959717340135508725994410722
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.40387396853026572381260004690676097483204321775264475184303987743246138426496
Short name T701
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.58 seconds
Started Nov 22 01:59:52 PM PST 23
Finished Nov 22 02:01:01 PM PST 23
Peak memory 201200 kb
Host smart-3695e0d7-2df6-46a3-81ad-6d4844667d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387396853026572381260004690676097483204321775264475184303987743246138426496 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.40387396853026572381260004690676097483204321775264475184303987
743246138426496
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.7742223016851301164392955233435497730775750435524649764106880250388681580744
Short name T695
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Nov 22 01:59:56 PM PST 23
Finished Nov 22 02:00:01 PM PST 23
Peak memory 201108 kb
Host smart-f484efff-4a90-4b9b-b554-5457faabdd80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7742223016851301164392955233435497730775750
435524649764106880250388681580744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.7742
223016851301164392955233435497730775750435524649764106880250388681580744
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.28242587379055825799256478488469025566929442788023792357327541399897188071007
Short name T682
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Nov 22 01:59:59 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 201016 kb
Host smart-024439d9-af7e-4fb9-9bcb-8c7f11d2708c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242587379055825799256478488469025566929442788023792357327541399897188071007 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.28242587379055825799256478488469025566929442788023792357327541399897188071007
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.73351079380146027845196221414317205679726392067575917390016996888606914971587
Short name T749
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 01:59:57 PM PST 23
Peak memory 200920 kb
Host smart-1389b26a-e26e-48fa-9fb7-c9590adeacdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73351079380146027845196221414317205679726392067575917390016996888606914971587 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.73351079380146027845196221414317205679726392067575917390016996888606914971587
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.32446415075110045701249370611413204706414661255658410600161099813252472864493
Short name T82
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.07 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 02:00:20 PM PST 23
Peak memory 201204 kb
Host smart-9823d7fc-d861-42a8-8ac6-0b3914292a96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446415075110045701249370611413204706414661255658410600161099813252472864493
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.32446415075110045701249370611413204706414661
255658410600161099813252472864493
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.61622534363334782384502108825322471162127433884703836973628409178329995638245
Short name T10
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.68 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 201184 kb
Host smart-d6324a01-d63e-4255-8be0-35c71bdf86db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61622534363334782384502108825322471162127433884703836973628409178329995638245 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.61622534363334782384502108825322471162127433884703836973628409178329995638245
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.25142999932309456852835504531980410836527885699403311536738109667684342679632
Short name T678
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.97 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 02:01:02 PM PST 23
Peak memory 201336 kb
Host smart-c388cc4f-d697-43df-b878-2bb2a8518500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142999932309456852835504531980410836527885699403311536738109667684342679632 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.25142999932309456852835504531980410836527885699403311536738109
667684342679632
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.73722499466168528458520575107394517474040356826980234349055209535764537132631
Short name T70
Test name
Test status
Simulation time 41047879715 ps
CPU time 112.54 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 02:01:48 PM PST 23
Peak memory 200628 kb
Host smart-175d4cbc-fe7e-4e3c-b4eb-e77fef1700cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73722499466168528458520575107394517474040356826980234349055209535764537132631 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.73722499466168528458520575107394517474040356826980234349055209535764537132631
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.81619054031093331649902623888026056139880157295279839660120893750298523119233
Short name T727
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.04 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 201140 kb
Host smart-113815c1-0ba0-4461-ad7a-c7fc4ae3228e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81619054031093331649902623888026056139880157295279839660120893750298523119233 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.81619054031093331649902623888026056139880157295279839660120893750298523119233
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.68632143673881927472908945252778306666158667800620750278381867002277222080051
Short name T711
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201104 kb
Host smart-ec3a9ad1-254c-486e-996d-96058848f089
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6863214367388192747290894525277830666615866
7800620750278381867002277222080051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.6863
2143673881927472908945252778306666158667800620750278381867002277222080051
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.7711041742590292228892743637464302600834020525334912397472701304637858744362
Short name T13
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.01 seconds
Started Nov 22 01:59:49 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201040 kb
Host smart-6728c7bd-5387-480c-9e2c-7674467622bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7711041742590292228892743637464302600834020525334912397472701304637858744362 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.7711041742590292228892743637464302600834020525334912397472701304637858744362
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.46160643237577970650452711366317020494829409292244239160921152681339356758230
Short name T756
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 22 01:59:49 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201004 kb
Host smart-f2464edc-7d45-44eb-a1c6-7f2999c3b2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46160643237577970650452711366317020494829409292244239160921152681339356758230 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.46160643237577970650452711366317020494829409292244239160921152681339356758230
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.94596243657214341331437742600654243802875002141390469832073186026362272237108
Short name T697
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.03 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 02:00:20 PM PST 23
Peak memory 201040 kb
Host smart-2c4cff05-7ac4-41f6-a84b-1012cb23cc51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94596243657214341331437742600654243802875002141390469832073186026362272237108
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.945962436572143413314377426006542438028750021
41390469832073186026362272237108
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.110685050519844443590978692248254734761923924985507775950029179173929919557175
Short name T50
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.67 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 201284 kb
Host smart-68cd554c-5e72-4ba4-ac4e-0079f88cd482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110685050519844443590978692248254734761923924985507775950029179173929919557175 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.110685050519844443590978692248254734761923924985507775950029179173929919557175
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.29262085462782530466770904920819404133503965102891098153031527004553679065131
Short name T776
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.97 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 02:00:58 PM PST 23
Peak memory 201292 kb
Host smart-f4e8520c-70a2-4331-899a-3b060cb25e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262085462782530466770904920819404133503965102891098153031527004553679065131 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.292620854627825304667709049208194041335039651028910981530315270
04553679065131
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.73786838207904336614238062362058731507776357280272192860738668374170441153747
Short name T713
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 201020 kb
Host smart-c9043b03-aae0-4ff9-8a41-34a811f5aa90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73786838207904336614238062362058731507776357280272192860738668374170441153747 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.73786838207904336614238062362058731507776357280272192860738668374170441153747
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.48489943286474056113309454139827556075866233459009033866177294557566300175528
Short name T693
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 01:59:56 PM PST 23
Finished Nov 22 02:00:00 PM PST 23
Peak memory 201032 kb
Host smart-839efce1-278f-46b9-9155-341442582a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48489943286474056113309454139827556075866233459009033866177294557566300175528 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.48489943286474056113309454139827556075866233459009033866177294557566300175528
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.84259423004071580078071833224497123150046063403755757608476317191609903392557
Short name T715
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 01:59:58 PM PST 23
Peak memory 200984 kb
Host smart-cd783dc5-4799-4c3b-87ad-9299c7574ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84259423004071580078071833224497123150046063403755757608476317191609903392557 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.84259423004071580078071833224497123150046063403755757608476317191609903392557
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.47113510787474635800401936214643243239255806801047546423765975250482506686160
Short name T670
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 201052 kb
Host smart-ac483b6d-42d1-45e1-a4da-073418c8035c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47113510787474635800401936214643243239255806801047546423765975250482506686160 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.47113510787474635800401936214643243239255806801047546423765975250482506686160
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.66549912984140664212302648094395837063057576259991300152200353628946232653684
Short name T758
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 200908 kb
Host smart-3f3aec56-db04-460c-8c40-abbcbda07e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66549912984140664212302648094395837063057576259991300152200353628946232653684 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.66549912984140664212302648094395837063057576259991300152200353628946232653684
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.41272491369695682892591573729262127396284119348632232172237238351336901295011
Short name T760
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 200908 kb
Host smart-91bf1c27-696f-42fb-8029-31c18c9be127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41272491369695682892591573729262127396284119348632232172237238351336901295011 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.41272491369695682892591573729262127396284119348632232172237238351336901295011
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.47701247139331815005032955890444861684690414636843636157920458732506387927796
Short name T709
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:06 PM PST 23
Peak memory 200908 kb
Host smart-f7d71580-fdf9-4604-8160-d95e76c3cc9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47701247139331815005032955890444861684690414636843636157920458732506387927796 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.47701247139331815005032955890444861684690414636843636157920458732506387927796
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.101243634141421624353518175037839868235540165592769622526680723149099323470762
Short name T719
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 01:59:52 PM PST 23
Finished Nov 22 01:59:57 PM PST 23
Peak memory 201020 kb
Host smart-7f945013-e32e-436b-9a71-4f585cc3d6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101243634141421624353518175037839868235540165592769622526680723149099323470762 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.101243634141421624353518175037839868235540165592769622526680723149099323470762
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.89054976711565942737632069520020485362434332690750781456847656890089136640155
Short name T757
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.65 seconds
Started Nov 22 02:00:01 PM PST 23
Finished Nov 22 02:00:06 PM PST 23
Peak memory 200908 kb
Host smart-63665795-c6e8-4dd1-bd5d-71257fa0c5d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89054976711565942737632069520020485362434332690750781456847656890089136640155 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.89054976711565942737632069520020485362434332690750781456847656890089136640155
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.37021857235211104617006321908583022142695566599971678410884001552361635191334
Short name T765
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.66 seconds
Started Nov 22 02:00:00 PM PST 23
Finished Nov 22 02:00:05 PM PST 23
Peak memory 200908 kb
Host smart-430e1b1d-d6b6-4766-83a9-a631cf5f8eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021857235211104617006321908583022142695566599971678410884001552361635191334 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.37021857235211104617006321908583022142695566599971678410884001552361635191334
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.11728817438553267977521361538802166650274105526741509239687558504347610789564
Short name T74
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.41 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201180 kb
Host smart-19649d72-fb07-43c0-a86b-7a4d7abf1ac5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11728817438553267977521361538802166650274105526741509239687558504347610789564 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.11728817438553267977521361538802166650274105526741509239687558504347610789564
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.36145951106097256868140019141588641839053315966551636556932781957613634419405
Short name T69
Test name
Test status
Simulation time 41047879715 ps
CPU time 110.94 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 02:01:29 PM PST 23
Peak memory 201244 kb
Host smart-6da36f74-caee-4553-82f8-e043b62686cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36145951106097256868140019141588641839053315966551636556932781957613634419405 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.36145951106097256868140019141588641839053315966551636556932781957613634419405
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.44770599388560695716496167409636914743046659371221649431717450775971305984998
Short name T79
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.16 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 201076 kb
Host smart-bb9b7d36-e72e-4f19-9da2-5db1cca2ac94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44770599388560695716496167409636914743046659371221649431717450775971305984998 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.44770599388560695716496167409636914743046659371221649431717450775971305984998
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.85863667765613895552334769973181079335557632926818369495750829597955654681130
Short name T767
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.14 seconds
Started Nov 22 01:59:44 PM PST 23
Finished Nov 22 01:59:49 PM PST 23
Peak memory 201028 kb
Host smart-9759258f-aa39-41e5-b310-145ae4b60d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8586366776561389555233476997318107933555763
2926818369495750829597955654681130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.8586
3667765613895552334769973181079335557632926818369495750829597955654681130
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.739509534266036659146039421370603614470192630786590670652135322239313706883
Short name T780
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.02 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 201008 kb
Host smart-63192e59-de31-42a8-b685-57a774736800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739509534266036659146039421370603614470192630786590670652135322239313706883 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.739509534266036659146039421370603614470192630786590670652135322239313706883
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.37856157601351511625275858916403918846315428960527262983503751694315978641325
Short name T750
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 01:59:36 PM PST 23
Finished Nov 22 01:59:41 PM PST 23
Peak memory 201000 kb
Host smart-f689ca25-a892-43c3-8311-1fdc518f773f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856157601351511625275858916403918846315428960527262983503751694315978641325 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.37856157601351511625275858916403918846315428960527262983503751694315978641325
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.69677495927172204460454307214115538243897197794442510385758723445679230737768
Short name T708
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.63 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 201228 kb
Host smart-1a6ca6a3-5f53-4ecd-82d3-71d6ea281dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69677495927172204460454307214115538243897197794442510385758723445679230737768
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.696774959271722044604543072141155382438971977
94442510385758723445679230737768
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.87744771026983132984732333536269614856653272048942105527138525691485930645936
Short name T773
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.78 seconds
Started Nov 22 01:59:56 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 201340 kb
Host smart-0b3d0da7-48f1-4196-9412-62d1ac15889b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87744771026983132984732333536269614856653272048942105527138525691485930645936 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.87744771026983132984732333536269614856653272048942105527138525691485930645936
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.55349993436834045736909197340800778528240656697398755062288374810120647002208
Short name T48
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.57 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 02:00:55 PM PST 23
Peak memory 201272 kb
Host smart-b4442bd7-4577-4e25-91dd-c9c94926179c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55349993436834045736909197340800778528240656697398755062288374810120647002208 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.553499934368340457369091973408007785282406566973987550622883748
10120647002208
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.87865561937215246857753777209301413007283806359388486338035506749915360967420
Short name T11
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 22 02:00:02 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 200908 kb
Host smart-6e75b903-7485-4fa6-86f6-100752d32b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87865561937215246857753777209301413007283806359388486338035506749915360967420 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.87865561937215246857753777209301413007283806359388486338035506749915360967420
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.49272319417268046055826042292542279607873753876473460363904265623132512691589
Short name T63
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 22 01:59:55 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 200988 kb
Host smart-e8e532ea-cc1a-47e9-84e6-de2a8fdbccf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49272319417268046055826042292542279607873753876473460363904265623132512691589 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.49272319417268046055826042292542279607873753876473460363904265623132512691589
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.20975126787073993344960546264767464942017485392714737833267431441680113588810
Short name T126
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 22 02:00:16 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 201056 kb
Host smart-fea30362-bfd7-48a3-a0c2-c107564f81d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20975126787073993344960546264767464942017485392714737833267431441680113588810 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.20975126787073993344960546264767464942017485392714737833267431441680113588810
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.40912100270108002426118123621501965144172797901252415709915827832203568843151
Short name T127
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 02:00:09 PM PST 23
Finished Nov 22 02:00:14 PM PST 23
Peak memory 200900 kb
Host smart-34fe30cf-0ffa-4669-9ff1-64a2e18b5f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912100270108002426118123621501965144172797901252415709915827832203568843151 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.40912100270108002426118123621501965144172797901252415709915827832203568843151
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.74015826971439263110380947856440307268199252155205445052371059433131782653763
Short name T690
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 201016 kb
Host smart-44595fe2-03c7-48c3-a2d1-698d464bd1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74015826971439263110380947856440307268199252155205445052371059433131782653763 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.74015826971439263110380947856440307268199252155205445052371059433131782653763
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.51293233219460973819275675900259536044284451708202968364403912286628507973047
Short name T706
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 02:00:10 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 201016 kb
Host smart-b1bc1234-825c-4652-8c24-fff6dbd56b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51293233219460973819275675900259536044284451708202968364403912286628507973047 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.51293233219460973819275675900259536044284451708202968364403912286628507973047
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.46919039441837701903685030543849320627762095621496391701090976876150234782746
Short name T62
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:17 PM PST 23
Peak memory 201092 kb
Host smart-e6cb235d-bf2a-41e4-8fc9-5422b898aa86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46919039441837701903685030543849320627762095621496391701090976876150234782746 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.46919039441837701903685030543849320627762095621496391701090976876150234782746
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.98891975033880751075193575726481154371786245744152469689695705561679102123405
Short name T125
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Nov 22 02:00:10 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 200996 kb
Host smart-9c19a5f5-242a-4953-b3b4-3bc97cfe7401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98891975033880751075193575726481154371786245744152469689695705561679102123405 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.98891975033880751075193575726481154371786245744152469689695705561679102123405
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.86582981349407543719275668099221415336258853932534645995360671812510447957894
Short name T728
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:17 PM PST 23
Peak memory 201016 kb
Host smart-f8ed3c9e-8ed1-42cd-aaed-4c892f9939c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86582981349407543719275668099221415336258853932534645995360671812510447957894 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.86582981349407543719275668099221415336258853932534645995360671812510447957894
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.76114796114352540883623851559118801807510466078822049584956442857120805915498
Short name T77
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Nov 22 02:00:07 PM PST 23
Finished Nov 22 02:00:12 PM PST 23
Peak memory 200932 kb
Host smart-0f12047e-0806-4c51-a20d-e81a6fc5e434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76114796114352540883623851559118801807510466078822049584956442857120805915498 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.76114796114352540883623851559118801807510466078822049584956442857120805915498
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.956337567459376386108090460373221334543670486804885907190819188126901252916
Short name T71
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.47 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 201348 kb
Host smart-c8110cb0-e689-40c7-a312-dde58d41870b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956337567459376386108090460373221334543670486804885907190819188126901252916 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.956337567459376386108090460373221334543670486804885907190819188126901252916
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.95408508709552472305991500624547734846087434090645355468424508637375254730891
Short name T76
Test name
Test status
Simulation time 41047879715 ps
CPU time 111.47 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 02:01:30 PM PST 23
Peak memory 201168 kb
Host smart-899d68d8-2149-4abf-95be-b653d8a46b86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95408508709552472305991500624547734846087434090645355468424508637375254730891 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.95408508709552472305991500624547734846087434090645355468424508637375254730891
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.44013208227461055756815082792050710981424348557165267736935971246502368859751
Short name T60
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.08 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:57 PM PST 23
Peak memory 201152 kb
Host smart-8537b26f-85f4-403d-9b66-61cdc179c8b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44013208227461055756815082792050710981424348557165267736935971246502368859751 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.44013208227461055756815082792050710981424348557165267736935971246502368859751
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.45920196375362976949643633231597382451995731848316860700140745676652555098625
Short name T739
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 201100 kb
Host smart-226685e1-46b5-4d48-80b9-1033f359bd52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4592019637536297694964363323159738245199573
1848316860700140745676652555098625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4592
0196375362976949643633231597382451995731848316860700140745676652555098625
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.88545983923204175053521290596987372683494657648450383219342411894902952309144
Short name T57
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.08 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 01:59:35 PM PST 23
Peak memory 200992 kb
Host smart-dbbce7cd-e0bd-4d20-bab3-3714a2d77a28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88545983923204175053521290596987372683494657648450383219342411894902952309144 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.88545983923204175053521290596987372683494657648450383219342411894902952309144
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.112683119506732451563541608528239144503874124270633121047071841855939801863451
Short name T769
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.67 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 200920 kb
Host smart-19b1ab12-cfe0-469d-b5e1-6ceeb6eae804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112683119506732451563541608528239144503874124270633121047071841855939801863451 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.112683119506732451563541608528239144503874124270633121047071841855939801863451
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.956306008654628333948996444915865488069515793846064728592446581378483618624
Short name T751
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.6 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 201220 kb
Host smart-c6a1d4e7-5bc5-4ed0-9f0e-e015ccb13ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956306008654628333948996444915865488069515793846064728592446581378483618624 -a
ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.95630600865462833394899644491586548806951579384
6064728592446581378483618624
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.101216492033242740853534701874735581546687716601834924025953484913907191450947
Short name T6
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.65 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 01:59:39 PM PST 23
Peak memory 201356 kb
Host smart-9c16d902-d7cd-42aa-a2f8-a44a48b3c69f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101216492033242740853534701874735581546687716601834924025953484913907191450947 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.101216492033242740853534701874735581546687716601834924025953484913907191450947
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.54017042287348132941277431708751529336423953964742396486722894063746693982771
Short name T725
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.82 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 02:00:47 PM PST 23
Peak memory 201256 kb
Host smart-fd58aeb7-b2bb-4ac3-b61d-7673c0c70c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54017042287348132941277431708751529336423953964742396486722894063746693982771 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.540170422873481329412774317087515293364239539647423964867228940
63746693982771
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.30241467378962572743099931001700690461900029546395326310550427328483685053129
Short name T681
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 02:00:16 PM PST 23
Peak memory 201020 kb
Host smart-671a1ee6-e533-4f3a-ab91-d87416eb11bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30241467378962572743099931001700690461900029546395326310550427328483685053129 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.30241467378962572743099931001700690461900029546395326310550427328483685053129
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.51524910691068517540989917878891177632452836370973539843246452830599504183368
Short name T755
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:00:19 PM PST 23
Peak memory 200936 kb
Host smart-2453edf3-8c72-4a6b-879f-12f68675698d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51524910691068517540989917878891177632452836370973539843246452830599504183368 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.51524910691068517540989917878891177632452836370973539843246452830599504183368
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.62594583370723609584849973678114389483119256262347241642125017412230166698185
Short name T78
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 22 02:00:14 PM PST 23
Finished Nov 22 02:00:19 PM PST 23
Peak memory 200780 kb
Host smart-79cdf076-d22c-4a71-9c92-52832c33d2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62594583370723609584849973678114389483119256262347241642125017412230166698185 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.62594583370723609584849973678114389483119256262347241642125017412230166698185
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.32313760745808230675668292032850551454309779109332146524500026672194978324458
Short name T777
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 200968 kb
Host smart-1b54fc8e-983f-43a5-8628-a5b41cb3cb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32313760745808230675668292032850551454309779109332146524500026672194978324458 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.32313760745808230675668292032850551454309779109332146524500026672194978324458
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.100814651162490790865234976471484323436595824943974793537128568865999357640944
Short name T707
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:00:18 PM PST 23
Peak memory 201028 kb
Host smart-d1be9667-7b04-431f-87f1-af00d31bb142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100814651162490790865234976471484323436595824943974793537128568865999357640944 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.100814651162490790865234976471484323436595824943974793537128568865999357640944
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.4770772585657335543949803968322577119105618058825219181901819712939747146301
Short name T762
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:17 PM PST 23
Peak memory 201020 kb
Host smart-3fb97026-c856-4ef2-ba3e-f82e8f367e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4770772585657335543949803968322577119105618058825219181901819712939747146301 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.4770772585657335543949803968322577119105618058825219181901819712939747146301
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.45395546548993456967421341063979133608949775070903090113891008194718142025453
Short name T730
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 201020 kb
Host smart-61f71ed1-8727-46ba-8695-25fcc329f494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45395546548993456967421341063979133608949775070903090113891008194718142025453 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.45395546548993456967421341063979133608949775070903090113891008194718142025453
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.74787765266952815717189751525450531812032314038059940025779035113671639937576
Short name T735
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 22 02:00:14 PM PST 23
Finished Nov 22 02:00:20 PM PST 23
Peak memory 200920 kb
Host smart-fa626a45-fce4-4451-b83f-d5e3a1ce53f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74787765266952815717189751525450531812032314038059940025779035113671639937576 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.74787765266952815717189751525450531812032314038059940025779035113671639937576
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.84250043496047969828230322947556103814142342536213671593859613916780477215991
Short name T686
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 22 02:00:16 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 200996 kb
Host smart-e6671279-9b87-45ef-b340-baa226863899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84250043496047969828230322947556103814142342536213671593859613916780477215991 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.84250043496047969828230322947556103814142342536213671593859613916780477215991
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.34659353847703090683140335618128312021337759380788670811351808172959163656864
Short name T66
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 22 02:00:09 PM PST 23
Finished Nov 22 02:00:14 PM PST 23
Peak memory 201012 kb
Host smart-269bec9e-ad0c-4451-9364-fc5b3cbc36c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659353847703090683140335618128312021337759380788670811351808172959163656864 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.34659353847703090683140335618128312021337759380788670811351808172959163656864
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.62830380762140623978304095378874019077273322329865222222736940645417612065911
Short name T680
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.2 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 201080 kb
Host smart-b13b0925-f24c-4736-ad1a-0ce4cdf8fa3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6283038076214062397830409537887401907727332
2329865222222736940645417612065911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.6283
0380762140623978304095378874019077273322329865222222736940645417612065911
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.112550972746133786919314622675438806606299190058849067831975937198733398332961
Short name T721
Test name
Test status
Simulation time 2074977215 ps
CPU time 4 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 01:59:53 PM PST 23
Peak memory 201040 kb
Host smart-f463d82b-2e6a-463c-beca-128710302386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112550972746133786919314622675438806606299190058849067831975937198733398332961 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.112550972746133786919314622675438806606299190058849067831975937198733398332961
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.66101777594181342317542039353504892007653232746536776046709185736069556864291
Short name T675
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Nov 22 01:59:37 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 200968 kb
Host smart-8482b603-14b9-4fa5-a2f2-73c025350e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66101777594181342317542039353504892007653232746536776046709185736069556864291 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.66101777594181342317542039353504892007653232746536776046709185736069556864291
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.51940009274683980779597308764325745697420127847067522029933693481961254486522
Short name T763
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.7 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 201272 kb
Host smart-57d8b4e9-f9b7-4d29-8016-71a022068b98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51940009274683980779597308764325745697420127847067522029933693481961254486522
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.519400092746839807795973087643257456974201278
47067522029933693481961254486522
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2029453525812582260581696208457700411651693547956110060307141695448896231904
Short name T51
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.77 seconds
Started Nov 22 01:59:51 PM PST 23
Finished Nov 22 01:59:58 PM PST 23
Peak memory 200788 kb
Host smart-2e4dfc53-557a-478d-a126-66747a9eb607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029453525812582260581696208457700411651693547956110060307141695448896231904 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.2029453525812582260581696208457700411651693547956110060307141695448896231904
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.114004067616442616455721983391068507733587726596208525248400054623783673054181
Short name T723
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.34 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 02:00:55 PM PST 23
Peak memory 201288 kb
Host smart-1faf38f4-f69f-476e-aacd-e49e2c0fe6b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114004067616442616455721983391068507733587726596208525248400054623783673054181 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.11400406761644261645572198339106850773358772659620852524840005
4623783673054181
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.72082951848993311596592254070882417161966886004939270717771907901550756075836
Short name T722
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Nov 22 01:59:41 PM PST 23
Finished Nov 22 01:59:46 PM PST 23
Peak memory 201060 kb
Host smart-5785c40c-ae8b-4452-81f6-3625a8c887b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7208295184899331159659225407088241716196688
6004939270717771907901550756075836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.7208
2951848993311596592254070882417161966886004939270717771907901550756075836
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.40722734214117451710520631843647897828121237864449354593818767041881565301731
Short name T59
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.08 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 201056 kb
Host smart-b96cbb71-623b-4057-98ca-bb4c3aa9bb9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722734214117451710520631843647897828121237864449354593818767041881565301731 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.40722734214117451710520631843647897828121237864449354593818767041881565301731
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.91448851815740744128704751060568918600928303877305478865029228207803124342081
Short name T714
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:47 PM PST 23
Peak memory 201020 kb
Host smart-3bfdd332-a662-413c-b37d-7a3a62b59b58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91448851815740744128704751060568918600928303877305478865029228207803124342081 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.91448851815740744128704751060568918600928303877305478865029228207803124342081
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.15430554998455166072707619750735618900866761317507500283317423172420634506267
Short name T673
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.5 seconds
Started Nov 22 01:59:44 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 201272 kb
Host smart-a4a3a62a-87a0-4849-850c-9d0df14f0045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15430554998455166072707619750735618900866761317507500283317423172420634506267
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.154305549984551660727076197507356189008667613
17507500283317423172420634506267
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.103770893862974691176257255175107390332678054190193096427755904865469472628489
Short name T724
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.7 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 201268 kb
Host smart-3cb0a1b1-0e35-4e39-8a39-50b2e10ac184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103770893862974691176257255175107390332678054190193096427755904865469472628489 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.103770893862974691176257255175107390332678054190193096427755904865469472628489
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.49969543464788220145658063218098322265915387125235815927652140903223645682320
Short name T766
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.26 seconds
Started Nov 22 01:59:44 PM PST 23
Finished Nov 22 02:00:55 PM PST 23
Peak memory 201244 kb
Host smart-0dece811-9c49-4e71-939d-9de263ca8359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49969543464788220145658063218098322265915387125235815927652140903223645682320 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.499695434647882201456580632180983222659153871252358159276521409
03223645682320
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.103308149455344190255262122046024582394129273708870501999030899747643023888125
Short name T64
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 201116 kb
Host smart-9bd967b2-1da6-4a0a-bdff-d83199924447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033081494553441902552621220460245823941292
73708870501999030899747643023888125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.103
308149455344190255262122046024582394129273708870501999030899747643023888125
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.98428424107612868489861085191614008120968577276635662072295985619263670457169
Short name T771
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 01:59:58 PM PST 23
Peak memory 201008 kb
Host smart-e818b8b9-771c-4942-8b96-1c9d61e22058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98428424107612868489861085191614008120968577276635662072295985619263670457169 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.98428424107612868489861085191614008120968577276635662072295985619263670457169
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.65883912910868704817266480695560453909326063339588395722369884652388925745282
Short name T745
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 01:59:57 PM PST 23
Peak memory 200984 kb
Host smart-f27090f1-0354-48de-ad40-ce80f522227f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65883912910868704817266480695560453909326063339588395722369884652388925745282 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.65883912910868704817266480695560453909326063339588395722369884652388925745282
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.53072631154035804797802368361573734377790152180413609067712344850429524394374
Short name T753
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.43 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:00:10 PM PST 23
Peak memory 201240 kb
Host smart-d106a89a-159c-4c9f-afe1-b4d1b93b9de5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53072631154035804797802368361573734377790152180413609067712344850429524394374
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.530726311540358047978023683615737343777901521
80413609067712344850429524394374
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.19182923084651250029108671460494243368931621118711065087544396421641881411720
Short name T726
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.67 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 201272 kb
Host smart-33749cf1-12b9-473a-89f2-8454d5a60aef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182923084651250029108671460494243368931621118711065087544396421641881411720 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.19182923084651250029108671460494243368931621118711065087544396421641881411720
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.92818638945404510019888315062542346962092283219684516220389172032971275401286
Short name T781
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.39 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:00:53 PM PST 23
Peak memory 201324 kb
Host smart-b3bfc8a0-115d-4697-b566-ecc7191bcc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92818638945404510019888315062542346962092283219684516220389172032971275401286 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.928186389454045100198883150625423469620922832196845162203891720
32971275401286
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.69017285838569738830769396631857938566507511822390528050894335319887248663770
Short name T744
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.2 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 01:59:47 PM PST 23
Peak memory 201056 kb
Host smart-30ba8784-bd00-450e-b3a9-b3d03df3d139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6901728583856973883076939663185793856650751
1822390528050894335319887248663770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.6901
7285838569738830769396631857938566507511822390528050894335319887248663770
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.60344205584357885401043382684136588544070621798508997051983379580829614294495
Short name T674
Test name
Test status
Simulation time 2074977215 ps
CPU time 3.99 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 201024 kb
Host smart-75fe6408-d978-4065-9c76-841ab426d993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60344205584357885401043382684136588544070621798508997051983379580829614294495 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.60344205584357885401043382684136588544070621798508997051983379580829614294495
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.47076813332371469038518684358052632884753123215309334294674643741942344249257
Short name T774
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.67 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 01:59:53 PM PST 23
Peak memory 201016 kb
Host smart-128923cd-8c8d-49c7-a760-935bcade320e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47076813332371469038518684358052632884753123215309334294674643741942344249257 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.47076813332371469038518684358052632884753123215309334294674643741942344249257
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.5556319017276153580706380692145562043370625644486870184842872862799769460927
Short name T702
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.19 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 201244 kb
Host smart-037f9457-f7ed-45ac-81ac-acc414a02923
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5556319017276153580706380692145562043370625644486870184842872862799769460927 -
assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.5556319017276153580706380692145562043370625644
486870184842872862799769460927
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.104313953939277646824249465877884199137131891808151540832111495575003071000985
Short name T688
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.71 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 201268 kb
Host smart-8ac2ad1c-4dc9-4725-ab3f-d7a52918300c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104313953939277646824249465877884199137131891808151540832111495575003071000985 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.104313953939277646824249465877884199137131891808151540832111495575003071000985
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.87430152517727242087183646770919625280160543890373255439779385283898014186502
Short name T710
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.99 seconds
Started Nov 22 01:59:48 PM PST 23
Finished Nov 22 02:00:59 PM PST 23
Peak memory 201296 kb
Host smart-ef98673e-3954-423b-b7f9-3dc765dd1699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87430152517727242087183646770919625280160543890373255439779385283898014186502 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.874301525177272420871836467709196252801605438903732554397793852
83898014186502
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.62214541639724831017218591667862531173432501721201740754215210226890548376684
Short name T729
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Nov 22 01:59:47 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 201096 kb
Host smart-247584b9-887e-46fb-86a3-7b54444a99f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6221454163972483101721859166786253117343250
1721201740754215210226890548376684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.6221
4541639724831017218591667862531173432501721201740754215210226890548376684
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.111825858044261487464509511837836837167926476937177377897237005565234813453954
Short name T772
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.09 seconds
Started Nov 22 01:59:44 PM PST 23
Finished Nov 22 01:59:49 PM PST 23
Peak memory 201032 kb
Host smart-4813bcb2-e39a-40e7-b655-c8ea67aa8958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111825858044261487464509511837836837167926476937177377897237005565234813453954 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.111825858044261487464509511837836837167926476937177377897237005565234813453954
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.104749794119925680051768821803341235132274838274986112396284718006130611662650
Short name T775
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 200948 kb
Host smart-0b1e2ceb-7cf4-4ac4-96ed-d2b4633e96a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104749794119925680051768821803341235132274838274986112396284718006130611662650 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.104749794119925680051768821803341235132274838274986112396284718006130611662650
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.46946507866377026458835409722460876755932235597545199676179415621923153680126
Short name T742
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.09 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 201284 kb
Host smart-bca82da8-e764-4ddf-9f58-9ea8390d4dff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46946507866377026458835409722460876755932235597545199676179415621923153680126
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.469465078663770264588354097224608767559322355
97545199676179415621923153680126
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.89402621360163982936895305965167542217852073056378255781021665753704586717265
Short name T2
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.62 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 201280 kb
Host smart-8e0c91b4-0a40-4a53-a8f6-de9867abd723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89402621360163982936895305965167542217852073056378255781021665753704586717265 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.89402621360163982936895305965167542217852073056378255781021665753704586717265
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.9912869984659248068105298439658347273519799226373411673363901965806641391021
Short name T691
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.15 seconds
Started Nov 22 01:59:54 PM PST 23
Finished Nov 22 02:01:05 PM PST 23
Peak memory 200656 kb
Host smart-36ea1b14-3cfe-4ece-8c4b-ea546b63900d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9912869984659248068105298439658347273519799226373411673363901965806641391021 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.9912869984659248068105298439658347273519799226373411673363901965806641391021
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.33212017282136296800776186290445141702499271740853490774742352019553601034994
Short name T324
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 201240 kb
Host smart-131b7ced-6734-4fa2-a780-52c4ebddad55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33212017282136296800776186290445141702499271740853490774742352019553601034994 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.33212017282136296800776186290445141702499271740853490774742352019553601034994
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.106486725783708311368283559119551258663442081668711745633698956743231864346812
Short name T562
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201252 kb
Host smart-498b609e-6125-4391-bf22-8e1e240d23a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106486725783708311368283559119551258663442081668711745633698956743231864346812 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.106486725783708311368283559119551258663442081668711745633698956743231864346812
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.16812019787370997361906047912511531718870482066780858402681519103300810499154
Short name T408
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.95 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 201248 kb
Host smart-7e84223c-92f9-46f2-be26-2da8d7b50508
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812019787370997361906047912511531718870482066780858402681519103300810499154 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.168120197873709973619060479125115317188704820667808584026815191
03300810499154
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.81022203122004088665625948906554108406929188911847853045700503871964454977024
Short name T107
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.48 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201212 kb
Host smart-98f1deae-9e45-4419-8ac3-b7ad4dc7c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81022203122004088665625948906554108406929188911847853045700503871964454977024 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.81022203122004088665625948906554108406929188911847853
045700503871964454977024
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.69109901250764712455292371836132574570876815230659780338463569978577510336453
Short name T248
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.75 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201168 kb
Host smart-fd20a5df-2228-4863-9d2f-1bc6a7c9535d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69109901250764712455292371836132574570876815230659780338463569978577510336453 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.6910990125076471245529237183613257457087681523065978033846356
9978577510336453
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.75970421143534420933269689967088651234539234306225743850377158038883096040340
Short name T622
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.49 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 200800 kb
Host smart-a649ef77-d088-4bd7-8dda-454130510f8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75970421143534420933269689967088651234539234306225743850377158038883096040340 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.75970421143534420933269689967088651234539234306225743850377158038883096040340
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.13659810136249165919208309764496561687924226963050911624450959781930476444168
Short name T85
Test name
Test status
Simulation time 38606274248 ps
CPU time 60.06 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 201184 kb
Host smart-c3002c45-a9ae-4cfd-819c-45546ae709d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13659810136249165919208309764496561687924226963050911624450959781930476444168 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.13659810136249165919208309764496561687924226963050911624450959781930476444168
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.74509353621841967992824666344955044061319067749034983683089627888696370333099
Short name T99
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.78 seconds
Started Nov 22 01:24:17 PM PST 23
Finished Nov 22 01:24:27 PM PST 23
Peak memory 201148 kb
Host smart-b731434a-35fa-43e8-995d-c2a19e3facbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74509353621841967992824666344955044061319067749034983683089627888696370333099 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.74509353621841967992824666344955044061319067749034983683089627888696370333099
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.5293141823629808500062572460584286894314093562119303555267185004463486287834
Short name T262
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Nov 22 01:24:02 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 201272 kb
Host smart-7268a102-49a6-4af5-b84e-c4294e6b421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5293141823629808500062572460584286894314093562119303555267185004463486287834 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.5293141823629808500062572460584286894314093562119303555267185004463486287834
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.102732099614596792899399121382542077490021101104456773790696136430738836447016
Short name T645
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201168 kb
Host smart-bef3582e-48d1-4215-9176-c87e8cda2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102732099614596792899399121382542077490021101104456773790696136430738836447016 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.102732099614596792899399121382542077490021101104456773790696136430738836447016
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2484335054125342175759870345837813427953160540609369083471720564894071939121
Short name T165
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 201056 kb
Host smart-bbdff152-5283-47c3-a210-d84e2aa6054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484335054125342175759870345837813427953160540609369083471720564894071939121 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2484335054125342175759870345837813427953160540609369083471720564894071939121
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.45823879442218836292184747383687206633496864457000306878619592891878573947230
Short name T131
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.95 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 221436 kb
Host smart-5a10a79d-40be-4f1e-8dde-1c54b664da32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45823879442218836292184747383687206633496864457000306878619592891878573947230 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.45823879442218836292184747383687206633496864457000306878619592891878573947230
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.50158750451776288570290441211070719507513661085463650591526718695152311595233
Short name T258
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 22 01:23:54 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201132 kb
Host smart-12b85964-c05b-441b-acf2-f5dc5ac36f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50158750451776288570290441211070719507513661085463650591526718695152311595233 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_smoke.50158750451776288570290441211070719507513661085463650591526718695152311595233
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.26017892434459227068945872720325131376556318714775749891024853479452659650197
Short name T377
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.52 seconds
Started Nov 22 01:23:24 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 201416 kb
Host smart-bc245bea-1acd-4938-a334-c8f50dd9cbc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26017892434459227068945872720325131376556318714775749891024853479452659650197 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.26017892434459227068945872720325131376556318714775749891024853479452659650197
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.51510406496203799147011774002761795509008499127375169309479773621120947778306
Short name T446
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:23:24 PM PST 23
Finished Nov 22 01:23:45 PM PST 23
Peak memory 201024 kb
Host smart-7c9bc175-fc51-45be-b916-72ec9619f32d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51510406496203799147011774002761795509008499127375169309479773621120947778306 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.5151040649620379914701177400276179550900849912737516930947977
3621120947778306
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.10901808129789789003792867677932435348506253618816333279700881970063343450103
Short name T205
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201216 kb
Host smart-5c724f30-2259-45ab-80f3-89ddd10d6587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10901808129789789003792867677932435348506253618816333279700881970063343450103 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.10901808129789789003792867677932435348506253618816333279700881970063343450103
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.5999465733333212108200334988071776674251774452265636359711088960428538112741
Short name T524
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.55 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 201096 kb
Host smart-0f0c55c4-1894-4509-a8b1-e447701af63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5999465733333212108200334988071776674251774452265636359711088960428538112741 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.5999465733333212108200334988071776674251774452265636359711088960428538112741
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.58724183610156716214980046480640249677400517532447851178721423355310049897234
Short name T643
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.08 seconds
Started Nov 22 01:23:26 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 201436 kb
Host smart-18f36fdf-64ea-4167-90e9-f21c8fd8d90e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58724183610156716214980046480640249677400517532447851178721423355310049897234 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.587241836101567162149800464806402496774005175324478511787214233
55310049897234
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.56520388962283876958873581576798400721726045702473547473897744441246489775179
Short name T459
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.32 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 201060 kb
Host smart-d7587b77-7e43-442a-8f06-2b0aea99e35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56520388962283876958873581576798400721726045702473547473897744441246489775179 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.56520388962283876958873581576798400721726045702473547473897744441246489775179
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.105359956742563645811559984843503820295432357337048742728653280848311615056446
Short name T92
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.47 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:24:34 PM PST 23
Peak memory 200876 kb
Host smart-d36f51a6-6de3-4384-8bf1-22e5fc2f28f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105359956742563645811559984843503820295432357337048742728653280848311615056446 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1053599567425636458115599848435038202954323573370487
42728653280848311615056446
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.82414692233571450211033865945791233480019531847332360516140270885271208865823
Short name T510
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201180 kb
Host smart-b5db7eb3-2c37-4068-9d98-398e21dd665f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82414692233571450211033865945791233480019531847332360516140270885271208865823 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.8241469223357145021103386594579123348001953184733236051614027
0885271208865823
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.108590084563881517050252625646623110532415775594696082739410116436848153649287
Short name T537
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Nov 22 01:23:28 PM PST 23
Finished Nov 22 01:23:47 PM PST 23
Peak memory 201172 kb
Host smart-40a91104-36f7-40bd-b464-d75b137d061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108590084563881517050252625646623110532415775594696082739410116436848153649287 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.108590084563881517050252625646623110532415775594696082739410116436848153649287
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.30311117740679271321667018544534348334678083266761905705409673074266339729900
Short name T566
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201236 kb
Host smart-06766be4-04f8-4f42-8417-facd2d9361d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30311117740679271321667018544534348334678083266761905705409673074266339729900 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.30311117740679271321667018544534348334678083266761905705409673074266339729900
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.63885889929873992578582667985628031670908083342624866565683458045512613651654
Short name T578
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:23:44 PM PST 23
Peak memory 201080 kb
Host smart-ba5613f7-fb5c-40b9-8ce3-559b441fc4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63885889929873992578582667985628031670908083342624866565683458045512613651654 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.63885889929873992578582667985628031670908083342624866565683458045512613651654
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.71277954184411960860657134077426811040342239147579015157310658200030463447803
Short name T53
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201064 kb
Host smart-d8771d21-a484-4917-94a4-fa4200782cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71277954184411960860657134077426811040342239147579015157310658200030463447803 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.71277954184411960860657134077426811040342239147579015157310658200030463447803
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.49199866138493969966938517397228669297127856386868268614260624147855480514759
Short name T132
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.36 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:24:54 PM PST 23
Peak memory 221564 kb
Host smart-da3f0a0c-047a-4903-970a-17c94bb53ff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49199866138493969966938517397228669297127856386868268614260624147855480514759 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.49199866138493969966938517397228669297127856386868268614260624147855480514759
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.50830903660404899045255496875772430696087889773059296608630420701773621369925
Short name T546
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:23:44 PM PST 23
Peak memory 200992 kb
Host smart-913cbe74-feee-4c45-b2e6-d8b98e34c8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50830903660404899045255496875772430696087889773059296608630420701773621369925 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_smoke.50830903660404899045255496875772430696087889773059296608630420701773621369925
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.107944321028982985442286396202332396025685034251893633280937127422537275097281
Short name T630
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.8 seconds
Started Nov 22 01:23:44 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 201456 kb
Host smart-e1cf83f0-279d-4d71-a3ce-1892422805ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107944321028982985442286396202332396025685034251893633280937127422537275097281 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.107944321028982985442286396202332396025685034251893633280937127422537275097281
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.49013375283705394498938173168095579415488610598191820391209228057383823662251
Short name T411
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.97 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:24:20 PM PST 23
Peak memory 199148 kb
Host smart-52950b8d-9f6b-4a3f-92f8-004dfc83c7f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49013375283705394498938173168095579415488610598191820391209228057383823662251 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.4901337528370539449893817316809557941548861059819182039120922
8057383823662251
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.53465506058810539086112903945965182291109267567784413159435222890272562967627
Short name T223
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.58 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 200640 kb
Host smart-861a0762-e9e4-4437-acdf-864d3623fd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53465506058810539086112903945965182291109267567784413159435222890272562967627 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.53465506058810539086112903945965182291109267567784413159435222890272562967627
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.22514342704484161091304635134892767634135818085852617393987340453916028758453
Short name T352
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.23 seconds
Started Nov 22 01:23:56 PM PST 23
Finished Nov 22 01:27:06 PM PST 23
Peak memory 201324 kb
Host smart-9b9522db-3b85-4b68-83e9-fc006dbce5ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22514342704484161091304635134892767634135818085852617393987340453916028758453 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.22514342704484161091304635134892767634135818085852617393987340
453916028758453
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.40950216754081081316823696587822982505664904512537769254426041043235159324816
Short name T467
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201052 kb
Host smart-64666a06-a252-45e6-ad87-9762030e1d11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40950216754081081316823696587822982505664904512537769254426041043235159324816 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.409502167540810813168236965878229825056649045125377692544260
41043235159324816
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.82723257076321605768389721689344913310039916439912003895210336315550578204328
Short name T26
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.19 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:57 PM PST 23
Peak memory 200672 kb
Host smart-3f53aa34-a0c2-422e-ade7-07d2eb781bc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82723257076321605768389721689344913310039916439912003895210336315550578204328 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.8272325707632160576838972168934491331003991643991200389521033631
5550578204328
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.99640390287858753749177023283498802788292053308242239505791026191624525653358
Short name T565
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 201036 kb
Host smart-71b5085c-de5b-4f86-bb80-cea4002c7592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99640390287858753749177023283498802788292053308242239505791026191624525653358 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.99640390287858753749177023283498802788292053308242239505791026191624525653358
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.87222062967519775150081016374906065560405897583674967083493186191752358055196
Short name T293
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 22 01:24:26 PM PST 23
Finished Nov 22 01:24:32 PM PST 23
Peak memory 201096 kb
Host smart-5074c256-354d-48d5-a984-92335df4125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87222062967519775150081016374906065560405897583674967083493186191752358055196 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.87222062967519775150081016374906065560405897583674967083493186191752358055196
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.27215655294923124827338997367719043574949385909748327667870156064684564391155
Short name T239
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:23:58 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201204 kb
Host smart-36fa949a-b125-4837-aec8-25c6f00db113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27215655294923124827338997367719043574949385909748327667870156064684564391155 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.27215655294923124827338997367719043574949385909748327667870156064684564391155
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.12760229252148077733808605356377242778015412078966103889955160244633861220688
Short name T563
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201124 kb
Host smart-12c95955-c949-4e25-97b0-40dc4a7f8e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12760229252148077733808605356377242778015412078966103889955160244633861220688 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_smoke.12760229252148077733808605356377242778015412078966103889955160244633861220688
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.40361805506563140508884542328236474808985531697597234234679561435298215783456
Short name T113
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.16 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 201472 kb
Host smart-1f76fce2-84ca-4950-b70f-f0266f331ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361805506563140508884542328236474808985531697597234234679561435298215783456 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.40361805506563140508884542328236474808985531697597234234679561435298215783456
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.19971845047959808630398889342030947956172883734246579684998321733010255601422
Short name T368
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201176 kb
Host smart-adcfdb39-e557-43a8-a2fe-61d5b7523e72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19971845047959808630398889342030947956172883734246579684998321733010255601422 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.199718450479598086303988893420309479561728837342465796849983
21733010255601422
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.108846558825079078943315569641834875067476748313962184077110679722172810917079
Short name T290
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:02 PM PST 23
Peak memory 201196 kb
Host smart-985d3885-0ed4-400e-9723-4d0bc7d2f842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108846558825079078943315569641834875067476748313962184077110679722172810917079 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.108846558825079078943315569641834875067476748313962184077110679722172810917079
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.68576219317346177250160332386932917664376890936334327353709619688485992916689
Short name T348
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.59 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201172 kb
Host smart-c96c45ef-d517-42ba-85b9-b35e1eeb2895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68576219317346177250160332386932917664376890936334327353709619688485992916689 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.68576219317346177250160332386932917664376890936334327353709619688485992916689
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.30799627047415211032467675030800052969925237747240963016510549573528951377988
Short name T465
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.91 seconds
Started Nov 22 01:23:56 PM PST 23
Finished Nov 22 01:27:06 PM PST 23
Peak memory 201388 kb
Host smart-ed6ecd09-1a89-4ebc-8d20-6e780f77e8d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30799627047415211032467675030800052969925237747240963016510549573528951377988 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.30799627047415211032467675030800052969925237747240963016510549
573528951377988
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.16726253629004717824742003993707495403730087238931207252970127457553288912260
Short name T375
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.57 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:10 PM PST 23
Peak memory 201180 kb
Host smart-ff1c5307-006c-4a5e-9993-f16047955eb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16726253629004717824742003993707495403730087238931207252970127457553288912260 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.167262536290047178247420039937074954037300872389312072529701
27457553288912260
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.16058074400480710986146229153870301963424850332331618236393120031675387664847
Short name T122
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201180 kb
Host smart-f503bebd-be98-4bc8-88c4-96e8ea55faae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16058074400480710986146229153870301963424850332331618236393120031675387664847 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.1605807440048071098614622915387030196342485033233161823639312003
1675387664847
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.66653704831197498420555900795126365148719783730168729427124580316788215732704
Short name T225
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 01:24:18 PM PST 23
Peak memory 201164 kb
Host smart-2f64e698-f143-47d4-8966-8f060c231f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66653704831197498420555900795126365148719783730168729427124580316788215732704 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.66653704831197498420555900795126365148719783730168729427124580316788215732704
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.36848008781930878387233412415803232499109670634412150160654483109846781463208
Short name T395
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.97 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201252 kb
Host smart-5852060c-2ac1-471a-b2d0-77d255ba1982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36848008781930878387233412415803232499109670634412150160654483109846781463208 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.36848008781930878387233412415803232499109670634412150160654483109846781463208
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.115184054035309516442811897477130115975569157270003258871010994388314884481827
Short name T452
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:24:18 PM PST 23
Peak memory 201096 kb
Host smart-7eed1bf6-73fb-4b39-8c82-cb6da535c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115184054035309516442811897477130115975569157270003258871010994388314884481827 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.115184054035309516442811897477130115975569157270003258871010994388314884481827
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.74694666420573998544823791868236542352141774588043690118810286740880002185888
Short name T481
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 201192 kb
Host smart-7bec41c1-17bf-43ed-9933-e3bcbf2f576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74694666420573998544823791868236542352141774588043690118810286740880002185888 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.74694666420573998544823791868236542352141774588043690118810286740880002185888
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.100237747264934581074209506137852801456823519981069549879578732197390478574070
Short name T138
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201120 kb
Host smart-b3174406-f9e0-4f5f-a865-bf07f5634ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100237747264934581074209506137852801456823519981069549879578732197390478574070 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.sysrst_ctrl_smoke.100237747264934581074209506137852801456823519981069549879578732197390478574070
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.89232985173806585739578218854107738466230469548283100118514504281026193611958
Short name T374
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.4 seconds
Started Nov 22 01:23:43 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 201456 kb
Host smart-47d5ba6a-8930-4a16-aef4-b78138969ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89232985173806585739578218854107738466230469548283100118514504281026193611958 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.89232985173806585739578218854107738466230469548283100118514504281026193611958
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.27500663892686361979138891732132382139038381238423146154157077291413329363337
Short name T660
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 22 01:23:54 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201072 kb
Host smart-39e4ca47-d6f0-4a53-992f-84cc6d052340
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27500663892686361979138891732132382139038381238423146154157077291413329363337 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.275006638926863619791388917321323821390383812384231461541570
77291413329363337
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.51793037662841191535014519787704015975444912730219352877109171866073948800580
Short name T381
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 22 01:24:05 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 201052 kb
Host smart-72c19b1c-9772-415c-bd64-d67a0e56351e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51793037662841191535014519787704015975444912730219352877109171866073948800580 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.51793037662841191535014519787704015975444912730219352877109171866073948800580
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.6896552935980393627184168130532818322512671836738834581582913335658355020761
Short name T541
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Nov 22 01:24:19 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 201164 kb
Host smart-f966f0d2-f188-40de-8b1b-ba47142a313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6896552935980393627184168130532818322512671836738834581582913335658355020761 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.6896552935980393627184168130532818322512671836738834581582913335658355020761
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.38399564578394399342128434925434819428143736996733646056591484975559648930252
Short name T350
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.25 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:27:03 PM PST 23
Peak memory 201368 kb
Host smart-8dc1d1ec-17df-4c6d-8a43-eb558c9cab8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38399564578394399342128434925434819428143736996733646056591484975559648930252 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.38399564578394399342128434925434819428143736996733646056591484
975559648930252
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.112951238107760260873886985586036670181019893480661570926073787007625012546074
Short name T482
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Nov 22 01:24:19 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 201228 kb
Host smart-0854486a-fec1-46ca-a889-a1bce7facf96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112951238107760260873886985586036670181019893480661570926073787007625012546074 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.11295123810776026087388698558603667018101989348066157092607
3787007625012546074
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.107919942167108343951635078153938201203571854664278156686255977843382282281086
Short name T177
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 22 01:24:34 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201200 kb
Host smart-0a228637-ba49-4af8-877f-9020f3f5fdaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107919942167108343951635078153938201203571854664278156686255977843382282281086 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.107919942167108343951635078153938201203571854664278156686255977
843382282281086
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.66713445510887541240249807723090583422304369290228084647215496838838465090269
Short name T158
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201136 kb
Host smart-85addc7f-d27e-41e6-bc1c-df53f3fd5372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66713445510887541240249807723090583422304369290228084647215496838838465090269 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.66713445510887541240249807723090583422304369290228084647215496838838465090269
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.12870597842633736519039797687228793273332571931993407524639926134787240141044
Short name T647
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 22 01:23:58 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 201248 kb
Host smart-6a63d052-321d-4073-9167-75b116863301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12870597842633736519039797687228793273332571931993407524639926134787240141044 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.12870597842633736519039797687228793273332571931993407524639926134787240141044
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.55620126014979778170674262811192157791341495569088944349161572493167323886056
Short name T94
Test name
Test status
Simulation time 2074566504 ps
CPU time 4.19 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201136 kb
Host smart-9803ee56-2390-4890-a7f7-93ab19dac13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55620126014979778170674262811192157791341495569088944349161572493167323886056 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.55620126014979778170674262811192157791341495569088944349161572493167323886056
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.18919052125310240737315043550427728407947662670597316551690245063172243749928
Short name T149
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 01:24:18 PM PST 23
Peak memory 201104 kb
Host smart-32778500-e09b-4270-9891-c15c6fd1c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18919052125310240737315043550427728407947662670597316551690245063172243749928 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.18919052125310240737315043550427728407947662670597316551690245063172243749928
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.76747653033654434413502018044031730707014360490990596441857760995567949734562
Short name T219
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 22 01:24:22 PM PST 23
Finished Nov 22 01:24:28 PM PST 23
Peak memory 201132 kb
Host smart-6fd38580-83b6-4b2b-a5b6-e5096c48239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76747653033654434413502018044031730707014360490990596441857760995567949734562 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_smoke.76747653033654434413502018044031730707014360490990596441857760995567949734562
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.107160679066942611856636745095353244960397441616932463441943698335289050006859
Short name T542
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.56 seconds
Started Nov 22 01:24:40 PM PST 23
Finished Nov 22 01:26:58 PM PST 23
Peak memory 201532 kb
Host smart-cb5ccebd-cae3-4c10-b8d6-817420cd9056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107160679066942611856636745095353244960397441616932463441943698335289050006859 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.107160679066942611856636745095353244960397441616932463441943698335289050006859
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.18302970764974169422457502573421905418764675977962616453279163320704648810390
Short name T570
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.94 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 201208 kb
Host smart-24da360f-9c43-4b97-b664-89ef1a1297bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18302970764974169422457502573421905418764675977962616453279163320704648810390 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.183029707649741694224575025734219054187646759779626164532791
63320704648810390
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.84659354476115676809195617966846832649376534843764972069849967966738358436822
Short name T345
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 201248 kb
Host smart-aa8c4020-329e-4bc8-bc52-a0b8b2f529b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84659354476115676809195617966846832649376534843764972069849967966738358436822 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.84659354476115676809195617966846832649376534843764972069849967966738358436822
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.22550628325816879770111340901679231924307671747561152498777223868767860079298
Short name T588
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.89 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:28:53 PM PST 23
Peak memory 200892 kb
Host smart-e8639f95-3402-4277-9582-35f0cf60ac3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550628325816879770111340901679231924307671747561152498777223868767860079298 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.22550628325816879770111340901679231924307671747561152498777223
868767860079298
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.18815539119137873635642260805996983624287768567463135386710127961232626054820
Short name T361
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 200960 kb
Host smart-c83fcf84-b35d-4bd2-ad19-d559b137015e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815539119137873635642260805996983624287768567463135386710127961232626054820 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.1881553911913787363564226080599698362428776856746313538671012796
1232626054820
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.79679559163583672890229015600220638250499281860414890058272158107144621725199
Short name T491
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 201204 kb
Host smart-f6949991-abff-4f90-b49f-7ed6b03bf42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79679559163583672890229015600220638250499281860414890058272158107144621725199 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.79679559163583672890229015600220638250499281860414890058272158107144621725199
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.113894220549360642665387342867984817416170768441539360342793551214307127178054
Short name T648
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Nov 22 01:23:52 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201044 kb
Host smart-ec92ec5f-8c9c-44b8-bc74-02ebc051392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113894220549360642665387342867984817416170768441539360342793551214307127178054 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.113894220549360642665387342867984817416170768441539360342793551214307127178054
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.39624500203953752066033394568454656438585383271332327233116494369669789312270
Short name T669
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 22 01:24:42 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201164 kb
Host smart-dd891716-29c7-4c8e-864b-842d9f302f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39624500203953752066033394568454656438585383271332327233116494369669789312270 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.39624500203953752066033394568454656438585383271332327233116494369669789312270
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.51246888190538302739659456031718005190987852613017988856062101781955701021923
Short name T468
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Nov 22 01:23:56 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201164 kb
Host smart-4708a109-503e-4a89-94d4-b6fcd9af5ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51246888190538302739659456031718005190987852613017988856062101781955701021923 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.51246888190538302739659456031718005190987852613017988856062101781955701021923
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.79444314666697555393466988773473946000215701943588164269588516720219077815307
Short name T160
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.95 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:24:11 PM PST 23
Peak memory 201124 kb
Host smart-8c7e1b97-eb73-4516-92d8-bf08b1b47b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79444314666697555393466988773473946000215701943588164269588516720219077815307 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_smoke.79444314666697555393466988773473946000215701943588164269588516720219077815307
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.56111279399023024449020735615185204682137796370039292005582063401477941221720
Short name T597
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.37 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 201468 kb
Host smart-70d1e542-ebb4-44fb-b65c-db66fd7ba65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56111279399023024449020735615185204682137796370039292005582063401477941221720 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.56111279399023024449020735615185204682137796370039292005582063401477941221720
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.45290954425220315988599861034908742269638158670105535434745807168980226406652
Short name T522
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 200876 kb
Host smart-a411d9b8-1ff9-4b01-8285-dd9e4ebc3d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45290954425220315988599861034908742269638158670105535434745807168980226406652 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.452909544252203159885998610349087422696381586701055354347458
07168980226406652
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.103803010167816999770285772377999826320012874403650330858216937190076443797208
Short name T364
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.59 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 01:24:17 PM PST 23
Peak memory 201188 kb
Host smart-fec9af38-a585-429e-a9d4-793b9bf2d856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103803010167816999770285772377999826320012874403650330858216937190076443797208 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.103803010167816999770285772377999826320012874403650330858216937190076443797208
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.21405290836318314118699883895349196969396754348030730989163369363917457633388
Short name T620
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:24:44 PM PST 23
Peak memory 201240 kb
Host smart-111e20d2-75e1-4d50-b077-75108662fa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21405290836318314118699883895349196969396754348030730989163369363917457633388 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.21405290836318314118699883895349196969396754348030730989163369363917457633388
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.100388670987263695977832165415135338083074352108855046025042341897302620837606
Short name T282
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.77 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:27:01 PM PST 23
Peak memory 201448 kb
Host smart-db6d131e-d2d6-4aac-9e86-544cd63709b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100388670987263695977832165415135338083074352108855046025042341897302620837606 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.1003886709872636959778321654151353380830743521088550460250423
41897302620837606
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.43353529900077386238001166615036632795495383111652718182508344155247421585246
Short name T417
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201204 kb
Host smart-ed94f624-0a40-4dfa-bbb5-e2cd7c35be46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43353529900077386238001166615036632795495383111652718182508344155247421585246 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.433535299000773862380011666150366327954953831116527181825083
44155247421585246
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.21353965604514365140269753170843835425897292126494802761603034844203452348089
Short name T371
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201020 kb
Host smart-f0264753-71d5-4db6-8b13-b89740d68fc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21353965604514365140269753170843835425897292126494802761603034844203452348089 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.2135396560451436514026975317084383542589729212649480276160303484
4203452348089
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.94845713258686361326435778771009865959787078507675279636010219520692218071261
Short name T140
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Nov 22 01:25:48 PM PST 23
Finished Nov 22 01:25:57 PM PST 23
Peak memory 200688 kb
Host smart-db44def0-c4c0-4328-970c-e10303881a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94845713258686361326435778771009865959787078507675279636010219520692218071261 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.94845713258686361326435778771009865959787078507675279636010219520692218071261
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.115091294695133951579579749978294133693717775455882052412886289090464967301946
Short name T102
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Nov 22 01:24:40 PM PST 23
Finished Nov 22 01:24:47 PM PST 23
Peak memory 201192 kb
Host smart-08d64009-ea55-466a-911d-66b9ae4c98c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115091294695133951579579749978294133693717775455882052412886289090464967301946 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.115091294695133951579579749978294133693717775455882052412886289090464967301946
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.102985550136182362250723083079264368016663016352560630264803408386966176425240
Short name T167
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:02 PM PST 23
Peak memory 201188 kb
Host smart-71589092-3ed2-41a0-9ea4-dc1da347c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102985550136182362250723083079264368016663016352560630264803408386966176425240 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.102985550136182362250723083079264368016663016352560630264803408386966176425240
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.96491653857050100993577809783950611422712752924631634780481733347738396570155
Short name T457
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.44 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 200252 kb
Host smart-65c4db23-3cc1-45f4-abae-80805534d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96491653857050100993577809783950611422712752924631634780481733347738396570155 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.96491653857050100993577809783950611422712752924631634780481733347738396570155
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.15283817582757375451471242323986429246180055125819674798250124027836327845986
Short name T172
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 201108 kb
Host smart-a509ce56-54f5-4e9f-b65b-becb1c2159c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15283817582757375451471242323986429246180055125819674798250124027836327845986 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sysrst_ctrl_smoke.15283817582757375451471242323986429246180055125819674798250124027836327845986
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.96662817218518653464237766363539877608787809248680748433092648368148876800693
Short name T283
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:24:13 PM PST 23
Peak memory 201220 kb
Host smart-06b55ddb-e229-4966-9a1b-9c4623ecab66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96662817218518653464237766363539877608787809248680748433092648368148876800693 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.966628172185186534642377663635398776087878092486807484330926
48368148876800693
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.71406974604115062859628901490145216501002507633380695657986050899186168525183
Short name T230
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 22 01:23:54 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201192 kb
Host smart-19979ca8-552c-4b84-a4be-8fded31fbda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71406974604115062859628901490145216501002507633380695657986050899186168525183 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.71406974604115062859628901490145216501002507633380695657986050899186168525183
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.82883345354340394319769319082889342714048673772584691619291533148038807349086
Short name T543
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201172 kb
Host smart-d3389d34-30a5-4314-ac5e-d9caef64a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82883345354340394319769319082889342714048673772584691619291533148038807349086 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.82883345354340394319769319082889342714048673772584691619291533148038807349086
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.94353860920847229376077686411427163592890608857269455329851130416661021599084
Short name T303
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.46 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 201432 kb
Host smart-21c118d6-76a7-40e9-914d-f298e481fc83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94353860920847229376077686411427163592890608857269455329851130416661021599084 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.94353860920847229376077686411427163592890608857269455329851130
416661021599084
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.68032878171636726004049023190409773295857250828918451568797050878744606154024
Short name T134
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201208 kb
Host smart-ab0bb2d1-a7ee-4d98-9b53-84932ac047f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68032878171636726004049023190409773295857250828918451568797050878744606154024 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.680328781716367260040490231904097732958572508289184515687970
50878744606154024
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.5375299457662361060775959324420570799975642162999979169266921680544272995287
Short name T664
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201180 kb
Host smart-1ff90646-8b8a-46f6-8332-e801a95a249d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5375299457662361060775959324420570799975642162999979169266921680544272995287 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.5375299457662361060775959324420570799975642162999979169266921680544272995287
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.72717810066081804800186644169601307307318318276336404946356723915823747837352
Short name T152
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Nov 22 01:24:29 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 201196 kb
Host smart-a7e1fed1-3e11-48d2-a31b-121cf1c019e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72717810066081804800186644169601307307318318276336404946356723915823747837352 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.72717810066081804800186644169601307307318318276336404946356723915823747837352
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.55666379513382884529214501854238604048034157040779223620944966299650276413311
Short name T349
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.91 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201192 kb
Host smart-fd4cb94a-e9a9-4d50-9959-fd0748b9489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55666379513382884529214501854238604048034157040779223620944966299650276413311 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.55666379513382884529214501854238604048034157040779223620944966299650276413311
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.76293620367038350295030774662283653414752621531169239511310759970705634137014
Short name T415
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.86 seconds
Started Nov 22 01:24:40 PM PST 23
Finished Nov 22 01:24:47 PM PST 23
Peak memory 201148 kb
Host smart-208fac32-8b39-4992-8dfd-1e41df48a510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76293620367038350295030774662283653414752621531169239511310759970705634137014 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.76293620367038350295030774662283653414752621531169239511310759970705634137014
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.114658124341594927158621513629500782638070866915332136017769184361485964316969
Short name T451
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201180 kb
Host smart-96a776e6-e937-4b67-b829-b24394ad4a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114658124341594927158621513629500782638070866915332136017769184361485964316969 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.114658124341594927158621513629500782638070866915332136017769184361485964316969
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.478885202381086530178329205352333948241637383431858421558480113938740260428
Short name T353
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:24:13 PM PST 23
Peak memory 201176 kb
Host smart-75286380-8a00-4a31-b58c-44a73394f76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478885202381086530178329205352333948241637383431858421558480113938740260428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.sysrst_ctrl_smoke.478885202381086530178329205352333948241637383431858421558480113938740260428
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.85818054739640199060793356383719212974897283160751910235031999360849920586461
Short name T521
Test name
Test status
Simulation time 87228974549 ps
CPU time 138.12 seconds
Started Nov 22 01:24:39 PM PST 23
Finished Nov 22 01:26:59 PM PST 23
Peak memory 201356 kb
Host smart-b4d9afd3-0c59-4964-a414-0bbc1638b3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85818054739640199060793356383719212974897283160751910235031999360849920586461 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.85818054739640199060793356383719212974897283160751910235031999360849920586461
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.7437294252770074923246344372175761177368224296732442159647215718916939734816
Short name T433
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.91 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201188 kb
Host smart-e6e51f82-248c-454f-9a6a-d824bf16b6aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7437294252770074923246344372175761177368224296732442159647215718916939734816 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.7437294252770074923246344372175761177368224296732442159647215
718916939734816
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.55770142082667868642894132149456964137349759564825521378318697007392178674309
Short name T129
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Nov 22 01:23:54 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201184 kb
Host smart-2371b930-dccf-4086-8aea-e811e20084cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55770142082667868642894132149456964137349759564825521378318697007392178674309 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.55770142082667868642894132149456964137349759564825521378318697007392178674309
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.46203023927188851092653722448573128060167007077990654259668076003638197204819
Short name T88
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Nov 22 01:24:19 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 201276 kb
Host smart-556ce090-f445-4a2c-8d42-99a9dc43ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46203023927188851092653722448573128060167007077990654259668076003638197204819 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.46203023927188851092653722448573128060167007077990654259668076003638197204819
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.34342858087863728415975481201131660383646536218451248808774199917318357491376
Short name T332
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.01 seconds
Started Nov 22 01:24:19 PM PST 23
Finished Nov 22 01:27:25 PM PST 23
Peak memory 201444 kb
Host smart-28324bcd-a138-4058-b086-dd70a753bc31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34342858087863728415975481201131660383646536218451248808774199917318357491376 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.34342858087863728415975481201131660383646536218451248808774199
917318357491376
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.99484131184810534138991400184082157872436186117495531087905908125101548628493
Short name T224
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:24 PM PST 23
Peak memory 201184 kb
Host smart-a9955bf4-d3b2-4efe-811e-3a4542aa9814
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99484131184810534138991400184082157872436186117495531087905908125101548628493 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.994841311848105341389914001840821578724361861174955310879059
08125101548628493
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.46969741454043616441068892618119196963451222222868134314126838549850714440573
Short name T618
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201012 kb
Host smart-1fbea193-5aad-484b-a83c-0f50fd287e4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46969741454043616441068892618119196963451222222868134314126838549850714440573 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.4696974145404361644106889261811919696345122222286813431412683854
9850714440573
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.31216280848972745709055399502226965301634789460228292050143624639424244016645
Short name T506
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201180 kb
Host smart-4d420d5a-d6a4-43ad-8392-f1d9c4f85edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31216280848972745709055399502226965301634789460228292050143624639424244016645 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.31216280848972745709055399502226965301634789460228292050143624639424244016645
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.67051196008859536020159463347506228338979468728924338791766558728368150608821
Short name T624
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 200080 kb
Host smart-db3bd0b4-2e52-4bc0-b16e-261e709d86f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67051196008859536020159463347506228338979468728924338791766558728368150608821 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.67051196008859536020159463347506228338979468728924338791766558728368150608821
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.72477091873390644760888709997545346320397281007436039544411778311906426353304
Short name T232
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:24:13 PM PST 23
Peak memory 201188 kb
Host smart-95894126-7fea-4454-881e-e4831fbe8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72477091873390644760888709997545346320397281007436039544411778311906426353304 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.72477091873390644760888709997545346320397281007436039544411778311906426353304
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.19038023358218732447308613031107326057743232389983641691718942579392920255284
Short name T185
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201168 kb
Host smart-578dbf95-1ee1-49ad-8fa3-ef1f666f3972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19038023358218732447308613031107326057743232389983641691718942579392920255284 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.19038023358218732447308613031107326057743232389983641691718942579392920255284
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.14354972353944604163516453759491102648039876793957935150118232670325262960724
Short name T655
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 201120 kb
Host smart-0a3b6cc4-c7ec-415c-9325-ddc08e4195a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14354972353944604163516453759491102648039876793957935150118232670325262960724 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_smoke.14354972353944604163516453759491102648039876793957935150118232670325262960724
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.29968176524715604110651988052715557379264509729603677255452283120548923660259
Short name T474
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.63 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 201420 kb
Host smart-a4e1431a-5722-4a26-897e-dd91ddc88fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29968176524715604110651988052715557379264509729603677255452283120548923660259 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.29968176524715604110651988052715557379264509729603677255452283120548923660259
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.95039584573170879470962965095787013259056068177458819725398212568226809062711
Short name T574
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 201120 kb
Host smart-5dd5a1ac-4820-42c3-819c-1209be23283e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95039584573170879470962965095787013259056068177458819725398212568226809062711 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.950395845731708794709629650957870132590560681774588197253982
12568226809062711
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.98759883859043693386680753146154975252511235922461741446264562888327508622727
Short name T608
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Nov 22 01:24:03 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 201212 kb
Host smart-cfb7014b-456d-44c9-87ae-0451fd83ebd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98759883859043693386680753146154975252511235922461741446264562888327508622727 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.98759883859043693386680753146154975252511235922461741446264562888327508622727
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.70296339777815015314762632592231139523284710169663147368830910840321100526476
Short name T442
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 199600 kb
Host smart-2de8c710-100d-4dc0-ae0d-55383b36261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70296339777815015314762632592231139523284710169663147368830910840321100526476 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.70296339777815015314762632592231139523284710169663147368830910840321100526476
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.62444946376724348510639719662141672896388921115960580561564728356806453082275
Short name T206
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Nov 22 01:23:52 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201052 kb
Host smart-300b13bf-0d97-4635-b246-6ee4d52b1d4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62444946376724348510639719662141672896388921115960580561564728356806453082275 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.624449463767243485106397196621416728963889211159605805615647
28356806453082275
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.86336598480464888178913156176578831304295376990542873780437039574806283270996
Short name T449
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 22 01:24:02 PM PST 23
Finished Nov 22 01:24:17 PM PST 23
Peak memory 201144 kb
Host smart-a67ca22d-180c-48bc-b8b9-6492d918399b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86336598480464888178913156176578831304295376990542873780437039574806283270996 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.8633659848046488817891315617657883130429537699054287378043703957
4806283270996
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.14262238154345002745056082511424623387196468048382915189908523783988075434541
Short name T315
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201212 kb
Host smart-190e071d-97bd-4293-8f82-06acf136a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14262238154345002745056082511424623387196468048382915189908523783988075434541 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.14262238154345002745056082511424623387196468048382915189908523783988075434541
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.31536209301088699101064204565121112713004139301801734951981787761076438420843
Short name T182
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 22 01:23:53 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201068 kb
Host smart-7f8a6754-2746-44b4-a387-db57365ae826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31536209301088699101064204565121112713004139301801734951981787761076438420843 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.31536209301088699101064204565121112713004139301801734951981787761076438420843
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.29906141547444529569686973255166399430345643685895500968082860252786513853698
Short name T301
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 22 01:23:53 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201176 kb
Host smart-0f6cce51-9c90-4e58-96bd-610ba1aac801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29906141547444529569686973255166399430345643685895500968082860252786513853698 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.29906141547444529569686973255166399430345643685895500968082860252786513853698
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.113962980044418663787786730280570442264384428254391143214506291766273481064898
Short name T42
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201216 kb
Host smart-64b7c408-fb09-4863-95f7-301fcd4cbf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113962980044418663787786730280570442264384428254391143214506291766273481064898 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.113962980044418663787786730280570442264384428254391143214506291766273481064898
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.48878296354135780025145102861993113771572775134369661285429928916363869738689
Short name T654
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201124 kb
Host smart-b9784461-b9b3-4465-a7ca-aae952e70e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48878296354135780025145102861993113771572775134369661285429928916363869738689 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_smoke.48878296354135780025145102861993113771572775134369661285429928916363869738689
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.9777731718155659016900515644171666552071626571463517153598031971035374971596
Short name T114
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.61 seconds
Started Nov 22 01:23:54 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 201372 kb
Host smart-cff7c352-a786-457f-b369-1f6149fa4793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9777731718155659016900515644171666552071626571463517153598031971035374971596 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.9777731718155659016900515644171666552071626571463517153598031971035374971596
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.90680223116146092290050157302124262312615650768400002153543054256271116790654
Short name T428
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 22 01:23:59 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 201192 kb
Host smart-3b14389f-6671-49bd-8457-5c1afbafcee9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90680223116146092290050157302124262312615650768400002153543054256271116790654 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.906802231161460922900501573021242623126156507684000021535430
54256271116790654
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.45860769548523896012080940153407388813725179604279297403428494300650575155928
Short name T396
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 22 01:24:03 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 201140 kb
Host smart-b86e1a35-06a7-4d11-b8f1-c164b152b90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45860769548523896012080940153407388813725179604279297403428494300650575155928 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.45860769548523896012080940153407388813725179604279297403428494300650575155928
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.95426181121920730150337369639500629240830400776973449728643079650260455465323
Short name T391
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Nov 22 01:23:57 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 201260 kb
Host smart-d827daa3-2d3c-4c3d-8251-b75665835f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95426181121920730150337369639500629240830400776973449728643079650260455465323 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.95426181121920730150337369639500629240830400776973449728643079650260455465323
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.61815615419210570397833542400139501911447389951416262383712406786541617862293
Short name T629
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.75 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 201344 kb
Host smart-3c2cd0be-d9a9-4e80-92a2-0a96adfba1ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61815615419210570397833542400139501911447389951416262383712406786541617862293 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.61815615419210570397833542400139501911447389951416262383712406
786541617862293
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.17219752893485652128096525043527071256253334414497085852386009809733387907196
Short name T577
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:10 PM PST 23
Peak memory 201204 kb
Host smart-79f84b84-e39e-42a0-8db9-e610042079eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17219752893485652128096525043527071256253334414497085852386009809733387907196 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.172197528934856521280965250435270712562533344144970858523860
09809733387907196
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.33894354596660509460203005441667465017691902686676386016501880339852162633717
Short name T619
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:24:21 PM PST 23
Peak memory 201052 kb
Host smart-63601d4f-cbcc-429a-9033-a7d5c59c1ad0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894354596660509460203005441667465017691902686676386016501880339852162633717 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.3389435459666050946020300544166746501769190268667638601650188033
9852162633717
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.23996987572025477796100704504565218755228961191746784163414367431030684641037
Short name T421
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.89 seconds
Started Nov 22 01:24:04 PM PST 23
Finished Nov 22 01:24:17 PM PST 23
Peak memory 201188 kb
Host smart-58236b31-437e-4e9a-be5e-aa3ce6c51a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23996987572025477796100704504565218755228961191746784163414367431030684641037 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.23996987572025477796100704504565218755228961191746784163414367431030684641037
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.38512938580702859381428081297340659187990248096031306365100441040848439161891
Short name T233
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:24:19 PM PST 23
Peak memory 201248 kb
Host smart-e494f356-6ca3-4846-a04e-ae5be40d6c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38512938580702859381428081297340659187990248096031306365100441040848439161891 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.38512938580702859381428081297340659187990248096031306365100441040848439161891
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.34881819604321370372829336475487034297593106994596479757936373728610813352302
Short name T288
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201036 kb
Host smart-9d28ca50-fb45-4e69-b75d-d5d264177672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34881819604321370372829336475487034297593106994596479757936373728610813352302 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.34881819604321370372829336475487034297593106994596479757936373728610813352302
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.41345148138970457133405669751814320956969885745608476691730106806663326480071
Short name T104
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.85 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:49 PM PST 23
Peak memory 201192 kb
Host smart-ad59e634-46a9-4109-ae7d-343260a20f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41345148138970457133405669751814320956969885745608476691730106806663326480071 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.41345148138970457133405669751814320956969885745608476691730106806663326480071
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.36373039397876700899446775608099872346331187230271778757454199856552421989078
Short name T638
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:20 PM PST 23
Peak memory 201152 kb
Host smart-932493c3-18bd-46cb-938b-2f5e0a1e3d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36373039397876700899446775608099872346331187230271778757454199856552421989078 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_smoke.36373039397876700899446775608099872346331187230271778757454199856552421989078
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.25408796216022669631671026438733606127435807874580565403574762046697793184157
Short name T500
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.95 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:26:24 PM PST 23
Peak memory 201340 kb
Host smart-20e11db2-0bbe-4e2f-876a-8917c3512a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25408796216022669631671026438733606127435807874580565403574762046697793184157 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.25408796216022669631671026438733606127435807874580565403574762046697793184157
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.49287932935360842983344461331411116063245536858796221963551641261672088268859
Short name T45
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 22 01:24:06 PM PST 23
Finished Nov 22 01:24:17 PM PST 23
Peak memory 201088 kb
Host smart-760abfd6-c91b-4f14-bcb9-08c83d9d4be6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49287932935360842983344461331411116063245536858796221963551641261672088268859 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.492879329353608429833444613314111160632455368587962219635516
41261672088268859
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.8565158820170598219020551726768713608674188390710074896143421166409945911962
Short name T596
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.76 seconds
Started Nov 22 01:24:45 PM PST 23
Finished Nov 22 01:24:50 PM PST 23
Peak memory 201032 kb
Host smart-b17b2bd6-209d-4d3f-8815-cf30c1739483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8565158820170598219020551726768713608674188390710074896143421166409945911962 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.8565158820170598219020551726768713608674188390710074896143421166409945911962
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.42591489913168397194529955910931011662860367605639768461049831536503702960601
Short name T336
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 22 01:24:45 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 201164 kb
Host smart-f7198c34-5b89-4a48-a6bf-5bb1e2e449b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42591489913168397194529955910931011662860367605639768461049831536503702960601 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.42591489913168397194529955910931011662860367605639768461049831536503702960601
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.98588221441780659816175956566193382584802747107903749226818285823091023021247
Short name T335
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.58 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 201320 kb
Host smart-42dffc73-ff85-4a98-934c-dbed12fa3687
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98588221441780659816175956566193382584802747107903749226818285823091023021247 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.98588221441780659816175956566193382584802747107903749226818285
823091023021247
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.44993988560682328048632441161181623278623699282553708257899724128030086929164
Short name T263
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Nov 22 01:25:26 PM PST 23
Finished Nov 22 01:25:42 PM PST 23
Peak memory 198720 kb
Host smart-eb3c95b5-b6bc-4763-96ff-ce6335e10a16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44993988560682328048632441161181623278623699282553708257899724128030086929164 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.449939885606823280486324411611816232786236992825537082578997
24128030086929164
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.14287211968892270927456992795288074810287305156357616555737010955065689089215
Short name T354
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Nov 22 01:24:43 PM PST 23
Finished Nov 22 01:24:51 PM PST 23
Peak memory 201188 kb
Host smart-ef65903c-7371-4aa9-b42a-076166974478
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14287211968892270927456992795288074810287305156357616555737010955065689089215 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.1428721196889227092745699279528807481028730515635761655573701095
5065689089215
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.9374588348445028040578337253461964694466735069530559948674414474034813088920
Short name T366
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 22 01:24:15 PM PST 23
Finished Nov 22 01:24:24 PM PST 23
Peak memory 201124 kb
Host smart-234bd1ed-1878-4a67-8429-cf3be8d3ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9374588348445028040578337253461964694466735069530559948674414474034813088920 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.9374588348445028040578337253461964694466735069530559948674414474034813088920
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.20693705693310863908924409230330146042543308451000239383735772519878000979157
Short name T159
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Nov 22 01:24:39 PM PST 23
Finished Nov 22 01:24:46 PM PST 23
Peak memory 201212 kb
Host smart-3006b208-30f0-4d35-92bc-65e907d74c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20693705693310863908924409230330146042543308451000239383735772519878000979157 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.20693705693310863908924409230330146042543308451000239383735772519878000979157
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.110615772940267196664887324742558747115286409912413614036264139422719729930042
Short name T156
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:24:01 PM PST 23
Finished Nov 22 01:24:12 PM PST 23
Peak memory 201260 kb
Host smart-d14fcfbb-9039-4fa8-a568-f67899e4f621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110615772940267196664887324742558747115286409912413614036264139422719729930042 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.110615772940267196664887324742558747115286409912413614036264139422719729930042
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.94786087946951673653277984028817155007072676896359349678268596218531597506710
Short name T312
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.51 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201216 kb
Host smart-e71ee621-2082-4752-9e3d-f32e21ca21ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94786087946951673653277984028817155007072676896359349678268596218531597506710 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.94786087946951673653277984028817155007072676896359349678268596218531597506710
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.77380892619007359030329448922272221747341826084549958353789695160815922283138
Short name T154
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Nov 22 01:24:00 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 201148 kb
Host smart-c82859f5-147d-42ca-88d2-d36a025bed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77380892619007359030329448922272221747341826084549958353789695160815922283138 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sysrst_ctrl_smoke.77380892619007359030329448922272221747341826084549958353789695160815922283138
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.42995217418868601317831486169839294987785286344320426088777351650159189946231
Short name T17
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.42 seconds
Started Nov 22 01:24:32 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 201360 kb
Host smart-2f700b7f-6eb0-49a1-ae36-d72162938e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42995217418868601317831486169839294987785286344320426088777351650159189946231 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.42995217418868601317831486169839294987785286344320426088777351650159189946231
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.48985520515739200168365685040356640797206356047646624213741065226878605736603
Short name T472
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 22 01:24:42 PM PST 23
Finished Nov 22 01:24:49 PM PST 23
Peak memory 201084 kb
Host smart-8e0451e0-9305-404a-a45a-0206ec16b0d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48985520515739200168365685040356640797206356047646624213741065226878605736603 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.489855205157392001683656850403566407972063560476466242137410
65226878605736603
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.60020973041559540468807013292364221662731620332636976501833009721270772709588
Short name T308
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 201212 kb
Host smart-06de2670-4c9c-4c4e-b522-642f1cd6e8b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60020973041559540468807013292364221662731620332636976501833009721270772709588 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.60020973041559540468807013292364221662731620332636976501833009721270772709588
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.7540190290992719717079144206500187022883039076901824869832459390263690254692
Short name T516
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.52 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201280 kb
Host smart-7f2f9c59-3d73-4eb3-a9bd-b4ab5883d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7540190290992719717079144206500187022883039076901824869832459390263690254692 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.7540190290992719717079144206500187022883039076901824869832459390263690254692
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.12522992212142072207248440053202806638908513334915631887867987518705066952872
Short name T211
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.31 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 201444 kb
Host smart-c777468b-336b-4c7b-95c8-2d157e98a5e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12522992212142072207248440053202806638908513334915631887867987518705066952872 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.125229922121420722072484400532028066389085133349156318878679875
18705066952872
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.31911617419814577406716352234428801773098535965228234893158949795859694561707
Short name T220
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.38 seconds
Started Nov 22 01:23:58 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201188 kb
Host smart-33858716-5c1c-4c28-a293-6a45c494842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31911617419814577406716352234428801773098535965228234893158949795859694561707 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.31911617419814577406716352234428801773098535965228234893158949795859694561707
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.34555808970008383614684660119763969844485621547269805618502372820217673407199
Short name T86
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.46 seconds
Started Nov 22 01:23:52 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201028 kb
Host smart-a86a0f35-cbb8-4ba9-8895-5b8ec2dc7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34555808970008383614684660119763969844485621547269805618502372820217673407199 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.34555808970008383614684660119763969844485621547269805
618502372820217673407199
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.60845560157511303842468876602285106128891022722977356512432052663742161932458
Short name T246
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 22 01:24:40 PM PST 23
Finished Nov 22 01:24:50 PM PST 23
Peak memory 201196 kb
Host smart-2724c541-0eb0-4611-b8d9-c8461c23f14e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60845560157511303842468876602285106128891022722977356512432052663742161932458 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.6084556015751130384246887660228510612889102272297735651243205
2663742161932458
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.80089061621091058064945936442207717737950071339252753023458242378076196017324
Short name T401
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:23:57 PM PST 23
Peak memory 201104 kb
Host smart-f5f0d8ab-8444-4b8c-be23-18a0f07c038c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80089061621091058064945936442207717737950071339252753023458242378076196017324 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.80089061621091058064945936442207717737950071339252753023458242378076196017324
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.5305048095494081747999402057142623446125688019660187659286545411204647831056
Short name T606
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201180 kb
Host smart-c317d4ae-a08a-4b6d-896d-ee42de14670b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5305048095494081747999402057142623446125688019660187659286545411204647831056 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.5305048095494081747999402057142623446125688019660187659286545411204647831056
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.29876061808311522864472067142288230793715503001932029942992319037605605388405
Short name T280
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201096 kb
Host smart-70ec1758-84c0-4407-b88c-bed13aa1fa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29876061808311522864472067142288230793715503001932029942992319037605605388405 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.29876061808311522864472067142288230793715503001932029942992319037605605388405
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.28100183074056146014704798941347018249593241291347881858722225743030113242670
Short name T196
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201184 kb
Host smart-380e32e6-b249-42cb-a017-390845d8eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28100183074056146014704798941347018249593241291347881858722225743030113242670 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.28100183074056146014704798941347018249593241291347881858722225743030113242670
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.20092375666362307580606444294689111856376605485029556334823882980355386153935
Short name T281
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201216 kb
Host smart-ee1e0f5e-6052-4ddc-937d-f4b0185d142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20092375666362307580606444294689111856376605485029556334823882980355386153935 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.20092375666362307580606444294689111856376605485029556334823882980355386153935
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.105095933143531048482999861214672449908706826377358686922805860141329781911402
Short name T123
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.26 seconds
Started Nov 22 01:24:09 PM PST 23
Finished Nov 22 01:25:17 PM PST 23
Peak memory 221532 kb
Host smart-d033dbcd-149e-4394-a891-33a5b4b423ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105095933143531048482999861214672449908706826377358686922805860141329781911402 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.105095933143531048482999861214672449908706826377358686922805860141329781911402
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.90227412243105447360437486628523369823442104269827466240462079630852274465123
Short name T527
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:23:37 PM PST 23
Peak memory 200960 kb
Host smart-7407b34d-e605-4cb2-8f79-1cd59eeb9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90227412243105447360437486628523369823442104269827466240462079630852274465123 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_smoke.90227412243105447360437486628523369823442104269827466240462079630852274465123
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.64893342002486644104849007694271869070774848250840776739208902097469567456996
Short name T183
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.96 seconds
Started Nov 22 01:24:08 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 201308 kb
Host smart-e36d2a37-6799-496f-879c-beee5327e7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64893342002486644104849007694271869070774848250840776739208902097469567456996 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.64893342002486644104849007694271869070774848250840776739208902097469567456996
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.10374170100055386216372955275376885703041747867494208760006122131315089694098
Short name T437
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201196 kb
Host smart-4df02ef6-353e-4261-81fa-949da1cf9a87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374170100055386216372955275376885703041747867494208760006122131315089694098 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.1037417010005538621637295527537688570304174786749420876000612
2131315089694098
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.29487174523204784030133456332865993821017557000613118069113614225125647489074
Short name T146
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 22 01:25:27 PM PST 23
Finished Nov 22 01:25:39 PM PST 23
Peak memory 200736 kb
Host smart-86427dc0-b663-450d-906a-b041590241dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29487174523204784030133456332865993821017557000613118069113614225125647489074 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.29487174523204784030133456332865993821017557000613118069113614225125647489074
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4296819686946629903997892449208534675369699778154670536336605838092902878466
Short name T389
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 22 01:24:27 PM PST 23
Finished Nov 22 01:24:34 PM PST 23
Peak memory 201228 kb
Host smart-b8a6ecbd-bd91-446a-ad2d-6d5247af8fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4296819686946629903997892449208534675369699778154670536336605838092902878466 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4296819686946629903997892449208534675369699778154670536336605838092902878466
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.114340830834386233497141665735981272978776085811438833775617377583277868590221
Short name T602
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.69 seconds
Started Nov 22 01:24:43 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 201436 kb
Host smart-dee66a8e-5000-4a63-b39b-885a33837581
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114340830834386233497141665735981272978776085811438833775617377583277868590221 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.1143408308343862334971416657359812729787760858114388337756173
77583277868590221
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.60744960007160160805618507978598116053652015758640933187926601750859712458984
Short name T554
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:23 PM PST 23
Peak memory 201164 kb
Host smart-68276ecb-08aa-475e-9d4e-e9c0e0aa3064
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60744960007160160805618507978598116053652015758640933187926601750859712458984 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.607449600071601608056185079785981160536520157586409331879266
01750859712458984
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.79755334659873083958472312237678643583656338884093026263710770241675325436802
Short name T28
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Nov 22 01:25:26 PM PST 23
Finished Nov 22 01:25:41 PM PST 23
Peak memory 198916 kb
Host smart-57efcaa3-5fb3-4609-8c76-43f58c34a112
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79755334659873083958472312237678643583656338884093026263710770241675325436802 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.7975533465987308395847231223767864358365633888409302626371077024
1675325436802
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.60777358445020013495379663299423603342893264990423039019464134367554992417982
Short name T508
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201220 kb
Host smart-d4a973fa-4d7a-4e7c-9434-19fc7acba724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60777358445020013495379663299423603342893264990423039019464134367554992417982 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.60777358445020013495379663299423603342893264990423039019464134367554992417982
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.12357119710146013366537032212442296395527463878798649406661224736954723054610
Short name T155
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:20 PM PST 23
Peak memory 201204 kb
Host smart-3e2e7bc2-4b92-4bad-8495-03abf56dd41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12357119710146013366537032212442296395527463878798649406661224736954723054610 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.12357119710146013366537032212442296395527463878798649406661224736954723054610
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.69539906919082937925176112222881342000667831338541944105976537525781169502628
Short name T551
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.85 seconds
Started Nov 22 01:25:26 PM PST 23
Finished Nov 22 01:25:39 PM PST 23
Peak memory 198700 kb
Host smart-a8c025af-6258-4f19-9ded-c0ba90950e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69539906919082937925176112222881342000667831338541944105976537525781169502628 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.69539906919082937925176112222881342000667831338541944105976537525781169502628
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.99245967478007705124953463306565092562557033373755391878178206261302355487391
Short name T583
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.65 seconds
Started Nov 22 01:25:27 PM PST 23
Finished Nov 22 01:25:41 PM PST 23
Peak memory 200764 kb
Host smart-03f7e9d4-2648-46b1-8385-62a9f56b14e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99245967478007705124953463306565092562557033373755391878178206261302355487391 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.99245967478007705124953463306565092562557033373755391878178206261302355487391
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.35440134660499184005657279221714371482208197025294809777015446059734945805351
Short name T141
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 201108 kb
Host smart-9ffb9f52-3ee9-4f13-9245-691b92403f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35440134660499184005657279221714371482208197025294809777015446059734945805351 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_smoke.35440134660499184005657279221714371482208197025294809777015446059734945805351
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.44010259895283391415027218414349576018476230387228020094862421030475791963713
Short name T316
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.6 seconds
Started Nov 22 01:24:23 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 201428 kb
Host smart-f14cdf13-d16a-402c-a25b-5b8c26ffaf66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44010259895283391415027218414349576018476230387228020094862421030475791963713 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.44010259895283391415027218414349576018476230387228020094862421030475791963713
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.40721687038010442323903312000000155017251786371073104674885630373044570192317
Short name T37
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 201184 kb
Host smart-ac17a441-206c-4fa6-9894-9982cf7d9a70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721687038010442323903312000000155017251786371073104674885630373044570192317 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.407216870380104423239033120000001550172517863710731046748856
30373044570192317
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.79914297955047433466943514532259313624315037674746600590606153165038405972101
Short name T130
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Nov 22 01:24:15 PM PST 23
Finished Nov 22 01:24:23 PM PST 23
Peak memory 201208 kb
Host smart-4193c65f-513d-4854-9d4e-88f8df104d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79914297955047433466943514532259313624315037674746600590606153165038405972101 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.79914297955047433466943514532259313624315037674746600590606153165038405972101
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.9204324592631979754199838995242671288410293772609223805091047767557666176740
Short name T380
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Nov 22 01:24:15 PM PST 23
Finished Nov 22 01:24:24 PM PST 23
Peak memory 201248 kb
Host smart-9fb4dc76-c0db-4f23-a538-537618c8310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9204324592631979754199838995242671288410293772609223805091047767557666176740 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.9204324592631979754199838995242671288410293772609223805091047767557666176740
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.52142408163808022921433366552863430883076020876298670789645427581767802883667
Short name T157
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.6 seconds
Started Nov 22 01:24:43 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 201344 kb
Host smart-949587c1-e094-4cea-a066-77740ff67896
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52142408163808022921433366552863430883076020876298670789645427581767802883667 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.52142408163808022921433366552863430883076020876298670789645427
581767802883667
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.26808654926318549854777710314021541113605005671265533476594109369202765751790
Short name T235
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 22 01:24:41 PM PST 23
Finished Nov 22 01:24:51 PM PST 23
Peak memory 201132 kb
Host smart-cc406822-dbda-4c9c-bd69-e86b967abd00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808654926318549854777710314021541113605005671265533476594109369202765751790 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.268086549263185498547777103140215411136050056712655334765941
09369202765751790
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.53539108813908954624031131142822058503147167050227645167049990011018069347753
Short name T646
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Nov 22 01:24:46 PM PST 23
Finished Nov 22 01:24:54 PM PST 23
Peak memory 201188 kb
Host smart-6e45a535-a154-4978-9872-d2879555f46d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53539108813908954624031131142822058503147167050227645167049990011018069347753 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.5353910881390895462403113114282205850314716705022764516704999001
1018069347753
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.17363199448220875960002748919479977760895934283041604211028538343744253992252
Short name T384
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Nov 22 01:24:23 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 201064 kb
Host smart-5467ca7a-eb21-471c-9dd5-f52e4582657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17363199448220875960002748919479977760895934283041604211028538343744253992252 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.17363199448220875960002748919479977760895934283041604211028538343744253992252
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.82141385470738022975976402267289501422986578290606899593411607865575504129139
Short name T199
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 22 01:24:43 PM PST 23
Finished Nov 22 01:24:50 PM PST 23
Peak memory 201240 kb
Host smart-2d0351b8-d1fc-4ad9-889e-5506bfd9dc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82141385470738022975976402267289501422986578290606899593411607865575504129139 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.82141385470738022975976402267289501422986578290606899593411607865575504129139
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.68943314476808629165549704273950920249286899423121909932348874676465313543188
Short name T632
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.81 seconds
Started Nov 22 01:24:13 PM PST 23
Finished Nov 22 01:24:21 PM PST 23
Peak memory 201128 kb
Host smart-62e87918-89c7-42f3-849d-c24921c1752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68943314476808629165549704273950920249286899423121909932348874676465313543188 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.68943314476808629165549704273950920249286899423121909932348874676465313543188
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.20933367620942886457336890315525152762951474056022513409356695692584239836436
Short name T601
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.75 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:21 PM PST 23
Peak memory 201044 kb
Host smart-2cb6579a-ff24-4724-9f50-bcc4adecca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20933367620942886457336890315525152762951474056022513409356695692584239836436 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.20933367620942886457336890315525152762951474056022513409356695692584239836436
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.55566671381557749481841411043005186550574658526519061090124889635704143012491
Short name T628
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Nov 22 01:24:46 PM PST 23
Finished Nov 22 01:24:51 PM PST 23
Peak memory 201120 kb
Host smart-9b528769-b4bd-45fa-a993-17ec11e330bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55566671381557749481841411043005186550574658526519061090124889635704143012491 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_smoke.55566671381557749481841411043005186550574658526519061090124889635704143012491
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.99174984582536083801696410768608189792904778252970317221913024242898703305351
Short name T174
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.73 seconds
Started Nov 22 01:24:44 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 201484 kb
Host smart-f6d798d0-3642-498f-a0ef-a02c3a9c8f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99174984582536083801696410768608189792904778252970317221913024242898703305351 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.99174984582536083801696410768608189792904778252970317221913024242898703305351
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.104258815316201893653911667597654465389621287530146435576841790264164188175393
Short name T572
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201176 kb
Host smart-273b9c1f-a6fd-4bce-a79a-9b6915062433
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104258815316201893653911667597654465389621287530146435576841790264164188175393 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.10425881531620189365391166759765446538962128753014643557684
1790264164188175393
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.107035565365034453280635887268854152132715620477564577320699952086502757264908
Short name T195
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Nov 22 01:24:15 PM PST 23
Finished Nov 22 01:24:23 PM PST 23
Peak memory 201152 kb
Host smart-8c1e042b-7b04-4438-8e4a-6c9182403949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107035565365034453280635887268854152132715620477564577320699952086502757264908 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.107035565365034453280635887268854152132715620477564577320699952086502757264908
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.53021996593339397536605401233192403300442486225253600901677148765732528370428
Short name T89
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 22 01:24:25 PM PST 23
Finished Nov 22 01:24:32 PM PST 23
Peak memory 201180 kb
Host smart-9508ce34-265b-4749-a581-66d7fcc686fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53021996593339397536605401233192403300442486225253600901677148765732528370428 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.53021996593339397536605401233192403300442486225253600901677148765732528370428
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.6684201102222345361225292919165094920270160604149282427875773820116197473441
Short name T342
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.25 seconds
Started Nov 22 01:24:42 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 201424 kb
Host smart-66a5fb38-ba4e-46d9-b49e-7f2170b42983
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6684201102222345361225292919165094920270160604149282427875773820116197473441 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.668420110222234536122529291916509492027016060414928242787577382
0116197473441
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.93788615198671057700220500390391969794712774851327965630791751866025751370902
Short name T392
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Nov 22 01:24:43 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 201204 kb
Host smart-f2091ff1-1233-41a8-869f-20a8b3c5d4cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93788615198671057700220500390391969794712774851327965630791751866025751370902 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.937886151986710577002205003903919697947127748513279656307917
51866025751370902
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.108191435303026855431106002398471484218941332291923690713957102379424631056522
Short name T582
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 22 01:25:27 PM PST 23
Finished Nov 22 01:25:41 PM PST 23
Peak memory 200052 kb
Host smart-6fbd31ac-8c1a-4029-8a65-da4c05c4f525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108191435303026855431106002398471484218941332291923690713957102379424631056522 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.108191435303026855431106002398471484218941332291923690713957102
379424631056522
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.40965416536139967184168294261255193961869112186402149166733638404269376157102
Short name T379
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Nov 22 01:24:42 PM PST 23
Finished Nov 22 01:24:49 PM PST 23
Peak memory 201204 kb
Host smart-be5b695c-e48c-40c7-a0b0-2c49614e2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40965416536139967184168294261255193961869112186402149166733638404269376157102 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.40965416536139967184168294261255193961869112186402149166733638404269376157102
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.90546281186421855324497570800243168569845001542633660503973782228221875177484
Short name T463
Test name
Test status
Simulation time 2470384766 ps
CPU time 5.13 seconds
Started Nov 22 01:24:15 PM PST 23
Finished Nov 22 01:24:24 PM PST 23
Peak memory 201220 kb
Host smart-43633aec-db25-4152-83f3-5e27c7ca5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90546281186421855324497570800243168569845001542633660503973782228221875177484 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.90546281186421855324497570800243168569845001542633660503973782228221875177484
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.81016526677438116266687257792008589397645197110677256003254202290725646482367
Short name T213
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:24:16 PM PST 23
Finished Nov 22 01:24:25 PM PST 23
Peak memory 201112 kb
Host smart-eaeb1cdc-26e9-45f2-84d5-105d883559e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81016526677438116266687257792008589397645197110677256003254202290725646482367 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.81016526677438116266687257792008589397645197110677256003254202290725646482367
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.80735281837262313500370501320534681668483111514833174348116434045036532851722
Short name T179
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Nov 22 01:24:16 PM PST 23
Finished Nov 22 01:24:25 PM PST 23
Peak memory 201064 kb
Host smart-1204efa1-7c7a-4b0a-9e96-30df3d8286cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80735281837262313500370501320534681668483111514833174348116434045036532851722 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.80735281837262313500370501320534681668483111514833174348116434045036532851722
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.54032331869624419308887013396155500183742443215077718142891611545431176398643
Short name T115
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:25:28 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 200692 kb
Host smart-5096bcbb-d8ac-4421-b091-4b2c63c689b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54032331869624419308887013396155500183742443215077718142891611545431176398643 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_smoke.54032331869624419308887013396155500183742443215077718142891611545431176398643
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.108331661138554954338835204893230225684516431125714737834313449309264699933025
Short name T556
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.88 seconds
Started Nov 22 01:25:26 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 198984 kb
Host smart-bf1ce5ca-d707-4ab1-ac95-d19370428349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108331661138554954338835204893230225684516431125714737834313449309264699933025 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.108331661138554954338835204893230225684516431125714737834313449309264699933025
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.33273229471640818955942632610620172590996495340295123063757667419365162550633
Short name T623
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:24:27 PM PST 23
Finished Nov 22 01:24:32 PM PST 23
Peak memory 201096 kb
Host smart-ce384001-c48b-4e8a-89bc-78f2d5b6d62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33273229471640818955942632610620172590996495340295123063757667419365162550633 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.33273229471640818955942632610620172590996495340295123063757667419365162550633
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.48411230073533223011041549217189431052690919159402648833566979311626742694781
Short name T419
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Nov 22 01:24:18 PM PST 23
Finished Nov 22 01:24:28 PM PST 23
Peak memory 201276 kb
Host smart-558b6048-d682-45f6-ad9d-a43782a011ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48411230073533223011041549217189431052690919159402648833566979311626742694781 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.48411230073533223011041549217189431052690919159402648833566979311626742694781
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.45895844404351487114558530728783385154437656215877268049280371211024455627263
Short name T640
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.52 seconds
Started Nov 22 01:24:25 PM PST 23
Finished Nov 22 01:27:29 PM PST 23
Peak memory 201344 kb
Host smart-0fd89f74-3cb8-44a6-aef4-3f18aed0644c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45895844404351487114558530728783385154437656215877268049280371211024455627263 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.45895844404351487114558530728783385154437656215877268049280371
211024455627263
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.27015118173486019630729247545646580237071398053914591180970410924129202337481
Short name T557
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Nov 22 01:24:27 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 201084 kb
Host smart-6b084ea6-048b-414b-ab74-d91dfd1aa557
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27015118173486019630729247545646580237071398053914591180970410924129202337481 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.270151181734860196307292475456465802370713980539145911809704
10924129202337481
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.78466916069391510127045355799783210250195432933077102389870140198591421189719
Short name T637
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Nov 22 01:24:44 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 201060 kb
Host smart-b5d7810a-74fb-4eef-8c7a-722fdaee93e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78466916069391510127045355799783210250195432933077102389870140198591421189719 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.7846691606939151012704535579978321025019543293307710238987014019
8591421189719
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.25474619766584231715991438637851133254369261435381452234118575277183569184336
Short name T250
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.78 seconds
Started Nov 22 01:24:17 PM PST 23
Finished Nov 22 01:24:26 PM PST 23
Peak memory 201216 kb
Host smart-85372e5f-2c4e-4c75-b2da-09653ffebfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25474619766584231715991438637851133254369261435381452234118575277183569184336 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.25474619766584231715991438637851133254369261435381452234118575277183569184336
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.30039021449650552545373555840566359195154255570344175833780606031789595077773
Short name T425
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 22 01:24:23 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 201212 kb
Host smart-d2815246-a19f-40dc-9b8f-a713494e6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30039021449650552545373555840566359195154255570344175833780606031789595077773 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.30039021449650552545373555840566359195154255570344175833780606031789595077773
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.8166764478745443240931234180609871624398353190294681865228757787907861934185
Short name T137
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Nov 22 01:24:26 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 201028 kb
Host smart-7172fc2c-5632-4313-b06e-24b3a0250227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8166764478745443240931234180609871624398353190294681865228757787907861934185 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.8166764478745443240931234180609871624398353190294681865228757787907861934185
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.73510207373183029915200716097893638540675868408966938015215269431700108232286
Short name T484
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Nov 22 01:24:19 PM PST 23
Finished Nov 22 01:24:28 PM PST 23
Peak memory 201220 kb
Host smart-f6e474a8-c850-494c-bb01-b741f0192cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73510207373183029915200716097893638540675868408966938015215269431700108232286 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.73510207373183029915200716097893638540675868408966938015215269431700108232286
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.900264299147635231873715311714098366891544165961624052509268572571443926869
Short name T367
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 22 01:25:27 PM PST 23
Finished Nov 22 01:25:39 PM PST 23
Peak memory 199408 kb
Host smart-95e5c430-6d59-48e1-b33c-bbd37cc61eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900264299147635231873715311714098366891544165961624052509268572571443926869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.sysrst_ctrl_smoke.900264299147635231873715311714098366891544165961624052509268572571443926869
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.96323039947912190558743558753756910167905467430579606242661995559913120792812
Short name T307
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.24 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 201372 kb
Host smart-2fd3665a-6185-43d7-9e5b-0b02186d60f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96323039947912190558743558753756910167905467430579606242661995559913120792812 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.96323039947912190558743558753756910167905467430579606242661995559913120792812
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.71740257312438460217981196939431703836900950361368322132429977807732308986340
Short name T586
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 22 01:24:16 PM PST 23
Finished Nov 22 01:24:25 PM PST 23
Peak memory 201108 kb
Host smart-178e5162-0309-4120-b65b-8cde1fa27fa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71740257312438460217981196939431703836900950361368322132429977807732308986340 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.717402573124384602179811969394317038369009503613683221324299
77807732308986340
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.57759039816377172027255631457943500090726058332966734938515549806237804371719
Short name T128
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 201196 kb
Host smart-bf4baf62-7096-4f05-a312-80ca8d844797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57759039816377172027255631457943500090726058332966734938515549806237804371719 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.57759039816377172027255631457943500090726058332966734938515549806237804371719
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.35787599126330448893955219386230443571654579293054408049435174678330745877019
Short name T604
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 201228 kb
Host smart-db8283f1-3221-49a2-b7a7-de89c7e90453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35787599126330448893955219386230443571654579293054408049435174678330745877019 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.35787599126330448893955219386230443571654579293054408049435174678330745877019
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.110057665591547830502681829098502928824720177352064399299644447765263991068267
Short name T277
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.91 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 201272 kb
Host smart-a13a363c-47ea-4b92-a271-5f09ed0fd22b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110057665591547830502681829098502928824720177352064399299644447765263991068267 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.1100576655915478305026818290985029288247201773520643992996444
47765263991068267
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.49229138484358881884345404605067166347132861903379898223231881326826712666148
Short name T289
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:45 PM PST 23
Peak memory 201104 kb
Host smart-77b9cff8-f41c-4ed2-a175-ebd333bef3ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49229138484358881884345404605067166347132861903379898223231881326826712666148 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.492291384843588818843454046050671663471328619033798982232318
81326826712666148
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.85062189668465672789590669065854914713121762427849335415328817520317511577771
Short name T242
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:38 PM PST 23
Peak memory 201100 kb
Host smart-4ea80dce-ea8e-467d-ba55-f467fcfa63a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85062189668465672789590669065854914713121762427849335415328817520317511577771 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.8506218966846567278959066906585491471312176242784933541532881752
0317511577771
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.68351310851436229398899630820737770936782389273413160353600178752838944891368
Short name T571
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Nov 22 01:24:27 PM PST 23
Finished Nov 22 01:24:33 PM PST 23
Peak memory 201068 kb
Host smart-f5cf9bde-2a88-4c04-8801-f6b5450329eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68351310851436229398899630820737770936782389273413160353600178752838944891368 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.68351310851436229398899630820737770936782389273413160353600178752838944891368
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.5608262913422208350807618806324179158448737313168931546981077748870322936417
Short name T410
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.93 seconds
Started Nov 22 01:24:25 PM PST 23
Finished Nov 22 01:24:32 PM PST 23
Peak memory 201128 kb
Host smart-d061494d-1ed6-486c-bbb7-25ae927bc372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5608262913422208350807618806324179158448737313168931546981077748870322936417 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.5608262913422208350807618806324179158448737313168931546981077748870322936417
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.56252931509846683125957896159114223032403350998553632904419351439904556449358
Short name T617
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 201140 kb
Host smart-7f53695f-7dae-4397-8042-0f29ed75068b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56252931509846683125957896159114223032403350998553632904419351439904556449358 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.56252931509846683125957896159114223032403350998553632904419351439904556449358
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2761439015733427200397565561976022283752577735630518236753384381678546756847
Short name T110
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 22 01:24:26 PM PST 23
Finished Nov 22 01:24:32 PM PST 23
Peak memory 201120 kb
Host smart-afb80b9c-c53d-4eec-97b0-fb6b8cb6e390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761439015733427200397565561976022283752577735630518236753384381678546756847 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2761439015733427200397565561976022283752577735630518236753384381678546756847
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.99588823616327489001277026106051802618300757850276086262973913012845961115595
Short name T215
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 200996 kb
Host smart-852f5007-7d09-4cbf-a14e-4078132efef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99588823616327489001277026106051802618300757850276086262973913012845961115595 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_smoke.99588823616327489001277026106051802618300757850276086262973913012845961115595
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.27447389264752492908839524221921240192722329619626091526943224618411833653410
Short name T530
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.95 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 201432 kb
Host smart-9bde9e16-4bb0-44d9-946b-9c3ff452851c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27447389264752492908839524221921240192722329619626091526943224618411833653410 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.27447389264752492908839524221921240192722329619626091526943224618411833653410
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.99555905423344283754034582148863530460304342776968918670680377012989289884383
Short name T237
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201076 kb
Host smart-6e5189ce-906e-4935-a068-4ee044498be0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99555905423344283754034582148863530460304342776968918670680377012989289884383 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.995559054233442837540345821488635304603043427769689186706803
77012989289884383
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.70338870126031123999912980649790429203513345907223239954960300689276498928717
Short name T501
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:24:35 PM PST 23
Finished Nov 22 01:24:41 PM PST 23
Peak memory 201184 kb
Host smart-f8545df6-4d3c-4d8b-9df4-930355694c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70338870126031123999912980649790429203513345907223239954960300689276498928717 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.70338870126031123999912980649790429203513345907223239954960300689276498928717
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.93826069780035987760542476217081785487588039582716138072792921259111630573650
Short name T470
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Nov 22 01:25:02 PM PST 23
Finished Nov 22 01:25:09 PM PST 23
Peak memory 201220 kb
Host smart-185bb6b3-6257-4e82-9459-e4a8db1effde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93826069780035987760542476217081785487588039582716138072792921259111630573650 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.93826069780035987760542476217081785487588039582716138072792921259111630573650
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.33223427180073373186915282860329141773826181991494659084479600392768378662896
Short name T306
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.52 seconds
Started Nov 22 01:24:33 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 201436 kb
Host smart-9b3d3291-1d7e-4e3d-8968-d94b43231015
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33223427180073373186915282860329141773826181991494659084479600392768378662896 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.33223427180073373186915282860329141773826181991494659084479600
392768378662896
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.73807615397928297408568352319474364447771834972801638033935584958172828981341
Short name T186
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 22 01:24:35 PM PST 23
Finished Nov 22 01:24:45 PM PST 23
Peak memory 201260 kb
Host smart-a888f771-28f3-456d-9b70-0bcc76d84685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73807615397928297408568352319474364447771834972801638033935584958172828981341 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.738076153979282974085683523194743644477718349728016380339355
84958172828981341
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.12037368113621413635092056044460393349697928948521716372671877053077901757610
Short name T317
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Nov 22 01:24:32 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201068 kb
Host smart-fde7264a-253d-4a02-be25-b9230c7b5b2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037368113621413635092056044460393349697928948521716372671877053077901757610 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.1203736811362141363509205604446039334969792894852171637267187705
3077901757610
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.96847767871286131602002751438068033940220512162152188074387786145857857039160
Short name T334
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 22 01:25:07 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201152 kb
Host smart-86ab59b8-e175-4a90-8aea-b9a06f753590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96847767871286131602002751438068033940220512162152188074387786145857857039160 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.96847767871286131602002751438068033940220512162152188074387786145857857039160
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.74948043472328970558283123546453635572451982123473951676476972551617269689942
Short name T663
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 199496 kb
Host smart-22375cc7-e87b-474a-bac8-02843945b03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74948043472328970558283123546453635572451982123473951676476972551617269689942 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.74948043472328970558283123546453635572451982123473951676476972551617269689942
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.32052074123705641962292982826965288998010828757682797012613812480667009508114
Short name T600
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:41 PM PST 23
Peak memory 201176 kb
Host smart-ea592954-0df3-4a78-8ffb-553cf4d5de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32052074123705641962292982826965288998010828757682797012613812480667009508114 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.32052074123705641962292982826965288998010828757682797012613812480667009508114
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.99733194538354597224545127578953711356528316978258664434537747013658217087448
Short name T633
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 22 01:25:00 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201176 kb
Host smart-a6b8fd26-7dee-4869-9244-43105835b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99733194538354597224545127578953711356528316978258664434537747013658217087448 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.99733194538354597224545127578953711356528316978258664434537747013658217087448
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.44488301996084249554542785870476621096450869297483719607930506101581942454039
Short name T447
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 201104 kb
Host smart-251e92b9-f846-4ccf-af25-3c3ff216bd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44488301996084249554542785870476621096450869297483719607930506101581942454039 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_smoke.44488301996084249554542785870476621096450869297483719607930506101581942454039
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.54770761936544322123675808220299742203505577501302220151483147223499553136690
Short name T344
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.98 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:26:47 PM PST 23
Peak memory 201456 kb
Host smart-b433b971-55c7-4018-8012-2145b6519358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54770761936544322123675808220299742203505577501302220151483147223499553136690 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.54770761936544322123675808220299742203505577501302220151483147223499553136690
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.88540332294397491061604139956647443161558778819077674520444576584241091505661
Short name T642
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Nov 22 01:25:00 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201028 kb
Host smart-ac200b2d-7117-4e96-af97-9bbcc0d92458
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88540332294397491061604139956647443161558778819077674520444576584241091505661 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.885403322943974910616041399566474431615587788190776745204445
76584241091505661
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.58855021709190733439969007306456020160734223648498232974850518925189957255841
Short name T198
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.79 seconds
Started Nov 22 01:24:30 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 201096 kb
Host smart-896b5832-21ec-46f8-977f-723a62e666d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58855021709190733439969007306456020160734223648498232974850518925189957255841 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.58855021709190733439969007306456020160734223648498232974850518925189957255841
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.105773390299687035768154616039783855140987555403164022074039913801345919418061
Short name T614
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 22 01:24:59 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201236 kb
Host smart-0af23c7e-504c-47e5-8300-c90177a86271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105773390299687035768154616039783855140987555403164022074039913801345919418061 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.105773390299687035768154616039783855140987555403164022074039913801345919418061
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.76776779881486093023204213712159818470651630803572497035868584903366994293651
Short name T560
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.31 seconds
Started Nov 22 01:24:35 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 201452 kb
Host smart-83f2eb73-9af5-4e75-b91b-ac53035ccf7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76776779881486093023204213712159818470651630803572497035868584903366994293651 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.76776779881486093023204213712159818470651630803572497035868584
903366994293651
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.78721507713255021625459452527473268329113558308966152753367785850192558629100
Short name T169
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 22 01:25:48 PM PST 23
Finished Nov 22 01:25:59 PM PST 23
Peak memory 200704 kb
Host smart-ffa0e45f-ddab-4b0c-bbc5-c1f53f310bc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78721507713255021625459452527473268329113558308966152753367785850192558629100 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.787215077132550216254594525274732683291135583089661527533677
85850192558629100
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.88627506834416710763924028109599928063078183593923633511576636246854112172206
Short name T261
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Nov 22 01:24:32 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201016 kb
Host smart-83f2f59e-8afb-4982-aca8-318a61cf23f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88627506834416710763924028109599928063078183593923633511576636246854112172206 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.8862750683441671076392402810959992806307818359392363351157663624
6854112172206
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.115465016489346023952648130826744172569376960019142673497587103855724950774642
Short name T145
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 22 01:24:33 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201212 kb
Host smart-328feb29-cb0e-4a7c-98da-958d3ebfc3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115465016489346023952648130826744172569376960019142673497587103855724950774642 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.115465016489346023952648130826744172569376960019142673497587103855724950774642
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.91106026207683993753975115174409264617219784648129158394993849162127371603809
Short name T665
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 22 01:24:33 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201188 kb
Host smart-ee182c25-2dcf-4709-8503-7673ffae5118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91106026207683993753975115174409264617219784648129158394993849162127371603809 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.91106026207683993753975115174409264617219784648129158394993849162127371603809
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.61401852697180523161372939110067059616707679278692373262798786608123538927553
Short name T18
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 201188 kb
Host smart-3ad5cadd-3c29-4e7a-a8e2-e2f3e24780eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61401852697180523161372939110067059616707679278692373262798786608123538927553 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.61401852697180523161372939110067059616707679278692373262798786608123538927553
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.58548709621055715448737354404152572263937310351431800285990338924703347079058
Short name T429
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Nov 22 01:24:33 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201208 kb
Host smart-7e438fa3-58e2-424b-8200-de24c2b1dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58548709621055715448737354404152572263937310351431800285990338924703347079058 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.58548709621055715448737354404152572263937310351431800285990338924703347079058
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.51220250670641591828754453467082898850673985891275512972185831371289318240284
Short name T214
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201136 kb
Host smart-ae46fb21-7ab1-495a-ab41-b963ff0cdae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51220250670641591828754453467082898850673985891275512972185831371289318240284 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_smoke.51220250670641591828754453467082898850673985891275512972185831371289318240284
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.37230766405906368518282509637316259738822244657508400065319274294969187449241
Short name T98
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.46 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 201536 kb
Host smart-f55c2b71-22f7-418c-a74a-4b8dd87512be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37230766405906368518282509637316259738822244657508400065319274294969187449241 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.37230766405906368518282509637316259738822244657508400065319274294969187449241
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.463855119782081685161889620202847285653851695307313475636498484740039881305
Short name T20
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 22 01:25:01 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201028 kb
Host smart-0df8b303-7c34-4433-a91e-996c5f4194fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463855119782081685161889620202847285653851695307313475636498484740039881305 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.46385511978208168516188962020284728565385169530731347563649848
4740039881305
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.44355205668227334697783643030618702755810601737696276924753635289037607870852
Short name T503
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201076 kb
Host smart-1a53baca-4850-47a4-a095-1ff54dab732f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44355205668227334697783643030618702755810601737696276924753635289037607870852 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.44355205668227334697783643030618702755810601737696276924753635289037607870852
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.83085905011977229185562882225107235291503595326815451012236653809870486462808
Short name T490
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Nov 22 01:24:34 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201248 kb
Host smart-8c5035d3-c493-4bd8-82d4-b43ba5ffcf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83085905011977229185562882225107235291503595326815451012236653809870486462808 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.83085905011977229185562882225107235291503595326815451012236653809870486462808
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.27974840985348334810068583832126118922643031779764700602097051981199533452301
Short name T635
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.65 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:27:42 PM PST 23
Peak memory 201432 kb
Host smart-fd04c1e4-3dce-4c5c-81ec-3151d55d5559
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974840985348334810068583832126118922643031779764700602097051981199533452301 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.27974840985348334810068583832126118922643031779764700602097051
981199533452301
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.72860220423836046181660922914470374973117467246571798426650786380810324497706
Short name T487
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201224 kb
Host smart-8aa78809-56f6-4541-bc4f-5fe28a5fe272
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72860220423836046181660922914470374973117467246571798426650786380810324497706 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.728602204238360461816609229144703749731174672465717984266507
86380810324497706
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.68800997702401997880911963613497730252096779299454728449706437535158794388952
Short name T561
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:39 PM PST 23
Peak memory 201208 kb
Host smart-e1712d78-8a52-49ed-ac76-a4a152489475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68800997702401997880911963613497730252096779299454728449706437535158794388952 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.6880099770240199788091196361349773025209677929945472844970643753
5158794388952
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.78271162663775130407531170249024187004034335806067882008315020910420350044833
Short name T435
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Nov 22 01:24:32 PM PST 23
Finished Nov 22 01:24:38 PM PST 23
Peak memory 201208 kb
Host smart-cf00fda0-eb1e-4fde-b65c-728cddfa671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78271162663775130407531170249024187004034335806067882008315020910420350044833 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.78271162663775130407531170249024187004034335806067882008315020910420350044833
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.47128558532147800637250345127176014107563967234299661667092343706335004398707
Short name T477
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 201200 kb
Host smart-2a50908d-391f-4450-935d-beb01e701088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47128558532147800637250345127176014107563967234299661667092343706335004398707 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.47128558532147800637250345127176014107563967234299661667092343706335004398707
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.102220975448729657060038795465999130857211568780167612001497551531620594945084
Short name T189
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 200984 kb
Host smart-d74d1d1f-e438-4982-9417-b9b4de9ae125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102220975448729657060038795465999130857211568780167612001497551531620594945084 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.102220975448729657060038795465999130857211568780167612001497551531620594945084
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.16150022689985102689782347271777235283515196020332048098432129892173182921779
Short name T272
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:24:44 PM PST 23
Peak memory 201184 kb
Host smart-0799f12b-bfdd-4787-b67e-b1f5c87c0298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16150022689985102689782347271777235283515196020332048098432129892173182921779 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.16150022689985102689782347271777235283515196020332048098432129892173182921779
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.85895385681730774332267126389498794516380748952517897842389531176819191572800
Short name T400
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 22 01:24:35 PM PST 23
Finished Nov 22 01:24:41 PM PST 23
Peak memory 201148 kb
Host smart-7dfb3aeb-fe09-41e6-8853-7578a58b23e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85895385681730774332267126389498794516380748952517897842389531176819191572800 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_smoke.85895385681730774332267126389498794516380748952517897842389531176819191572800
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.68091377001501097018187204257247988279036147236302747180139263236827605698126
Short name T23
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.46 seconds
Started Nov 22 01:24:57 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 201408 kb
Host smart-b7ed9339-f168-4805-aab1-2e5cb7fe3e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68091377001501097018187204257247988279036147236302747180139263236827605698126 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.68091377001501097018187204257247988279036147236302747180139263236827605698126
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.20735110362009199588455257233907210823538242440171338345037520905272605851675
Short name T652
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 22 01:24:35 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201204 kb
Host smart-08f8583b-9eb1-47bb-b629-b79f9819b8ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735110362009199588455257233907210823538242440171338345037520905272605851675 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.207351103620091995884552572339072108235382424401713383450375
20905272605851675
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.98770803970967929914201085086310798872436434119030184409510894612282784962106
Short name T298
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 22 01:24:52 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201212 kb
Host smart-3bde2453-47dd-4cb5-b77c-ce0b7a9e3bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98770803970967929914201085086310798872436434119030184409510894612282784962106 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.98770803970967929914201085086310798872436434119030184409510894612282784962106
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.97362483949447684831873016079906325653177332139965727295910861746936037705147
Short name T358
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Nov 22 01:24:32 PM PST 23
Finished Nov 22 01:24:39 PM PST 23
Peak memory 201276 kb
Host smart-d04ed858-995c-4f34-be96-48d020de52ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97362483949447684831873016079906325653177332139965727295910861746936037705147 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.97362483949447684831873016079906325653177332139965727295910861746936037705147
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.22826575055749382201544269440082633137198814435655796879008020022986407052874
Short name T153
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.42 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:27:57 PM PST 23
Peak memory 201424 kb
Host smart-79805442-3562-42b3-a43f-4c66e51983e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22826575055749382201544269440082633137198814435655796879008020022986407052874 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.22826575055749382201544269440082633137198814435655796879008020
022986407052874
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.59125536421277315449728965593494832648604823841193754713186299808542844704462
Short name T453
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:24:31 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 201060 kb
Host smart-d4c15a92-c184-4472-aa42-4752e20c39c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59125536421277315449728965593494832648604823841193754713186299808542844704462 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.591255364212773154497289655934948326486048238411937547131862
99808542844704462
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.112307150095990101046812156016746359340468002228832523900868011660870614494515
Short name T626
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:06 PM PST 23
Peak memory 201148 kb
Host smart-cd7f94d7-282c-4a49-921a-3c6d9a79c9ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112307150095990101046812156016746359340468002228832523900868011660870614494515 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.112307150095990101046812156016746359340468002228832523900868011
660870614494515
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.30109062785488301023253072128664408320280121030954723580888174389854226815878
Short name T365
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 22 01:24:36 PM PST 23
Finished Nov 22 01:24:43 PM PST 23
Peak memory 201204 kb
Host smart-45a31be7-02f1-4293-a056-4010e88da39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30109062785488301023253072128664408320280121030954723580888174389854226815878 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.30109062785488301023253072128664408320280121030954723580888174389854226815878
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.68004325986108256391689350264523018579245196504909299270197272803243192551474
Short name T517
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 22 01:24:33 PM PST 23
Finished Nov 22 01:24:39 PM PST 23
Peak memory 201248 kb
Host smart-2cfc0676-45b4-4460-bb2d-fdcc5b18a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68004325986108256391689350264523018579245196504909299270197272803243192551474 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.68004325986108256391689350264523018579245196504909299270197272803243192551474
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.52089874909726702163385639115313135228473684072291533216858028879432615721268
Short name T424
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 22 01:25:00 PM PST 23
Finished Nov 22 01:25:07 PM PST 23
Peak memory 201128 kb
Host smart-e14c50ae-8443-4e9f-93f2-ad698cff3e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52089874909726702163385639115313135228473684072291533216858028879432615721268 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.52089874909726702163385639115313135228473684072291533216858028879432615721268
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.34109623011426281590029179412845977778908738234055217213961584224992072312339
Short name T579
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.73 seconds
Started Nov 22 01:24:35 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 201168 kb
Host smart-aab02d11-fd61-47eb-9271-9a57792c2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34109623011426281590029179412845977778908738234055217213961584224992072312339 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.34109623011426281590029179412845977778908738234055217213961584224992072312339
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.31143758060492756277260398431671372015796221031324632351236775457617923410452
Short name T136
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Nov 22 01:24:34 PM PST 23
Finished Nov 22 01:24:41 PM PST 23
Peak memory 201148 kb
Host smart-0b0d9c83-549e-4097-9776-e86b500851e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31143758060492756277260398431671372015796221031324632351236775457617923410452 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_smoke.31143758060492756277260398431671372015796221031324632351236775457617923410452
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.7835541322015749398808006150554782642478749733149138605225628869155217078078
Short name T372
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.69 seconds
Started Nov 22 01:26:15 PM PST 23
Finished Nov 22 01:28:35 PM PST 23
Peak memory 201244 kb
Host smart-9c9c0f47-bca0-496e-b1fe-a9b48498a0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7835541322015749398808006150554782642478749733149138605225628869155217078078 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.7835541322015749398808006150554782642478749733149138605225628869155217078078
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.100402148214638504675488230531024472116574247456527567704994630447214756022178
Short name T382
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Nov 22 01:24:32 PM PST 23
Finished Nov 22 01:24:38 PM PST 23
Peak memory 201076 kb
Host smart-2c756bc2-1c75-42cd-b378-9f1a204bf087
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100402148214638504675488230531024472116574247456527567704994630447214756022178 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.10040214821463850467548823053102447211657424745652756770499
4630447214756022178
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.25236892163393024537127120789068471676566499375951823804450534486223750646083
Short name T271
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 201040 kb
Host smart-61c6e6d0-bc03-432e-91b3-8203087f4c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236892163393024537127120789068471676566499375951823804450534486223750646083 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.25236892163393024537127120789068471676566499375951823804450534486223750646083
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.110003783824927370848036768315217122771230168663686001836375504667803572133266
Short name T611
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:57 PM PST 23
Peak memory 201084 kb
Host smart-a4b103f5-e269-4a24-8904-d1199f4baf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110003783824927370848036768315217122771230168663686001836375504667803572133266 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.110003783824927370848036768315217122771230168663686001836375504667803572133266
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.42363811938236824426578767159559825657508208240567532551966851122791201455255
Short name T327
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.11 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 201368 kb
Host smart-c7a2c9db-b4f6-4343-aabd-200b0b3b6593
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363811938236824426578767159559825657508208240567532551966851122791201455255 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.42363811938236824426578767159559825657508208240567532551966851
122791201455255
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.91215385664408734963463711757484578113950824031544921842192886632234962557107
Short name T548
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.3 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201152 kb
Host smart-910cf60e-23e4-4e75-8903-43578eaa83dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91215385664408734963463711757484578113950824031544921842192886632234962557107 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.912153856644087349634637117574845781139508240315449218421928
86632234962557107
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.17549495863349371171090330004005847630794164473042524589470314573213776473155
Short name T265
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Nov 22 01:26:15 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 200956 kb
Host smart-b396c40d-e6a4-4130-92bb-c0f8f71a02d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17549495863349371171090330004005847630794164473042524589470314573213776473155 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.1754949586334937117109033000400584763079416447304252458947031457
3213776473155
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.103096324884875363816061711510575051828389797267705477609202017609783629705409
Short name T268
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201196 kb
Host smart-650d8e77-b72b-41d9-bb35-b596c5c03142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103096324884875363816061711510575051828389797267705477609202017609783629705409 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.103096324884875363816061711510575051828389797267705477609202017609783629705409
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.25824699898896036470729518565720046322430069492439460879477767092051062365647
Short name T476
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201144 kb
Host smart-8eaf7c95-1a7d-41d1-8f10-9aaade494c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25824699898896036470729518565720046322430069492439460879477767092051062365647 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.25824699898896036470729518565720046322430069492439460879477767092051062365647
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.5069095669664725849020543009911775655635902229930772081124725784771094919513
Short name T509
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 200932 kb
Host smart-295e871c-cacb-4cfd-8124-f5117ac12f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5069095669664725849020543009911775655635902229930772081124725784771094919513 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.5069095669664725849020543009911775655635902229930772081124725784771094919513
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.20313493985388254801418763571875701768868491155774425246699611844868239357311
Short name T448
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201216 kb
Host smart-045c7226-d3dc-4ebc-9417-bfede09a462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20313493985388254801418763571875701768868491155774425246699611844868239357311 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.20313493985388254801418763571875701768868491155774425246699611844868239357311
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.65983355520790378859216748840268299127745269975927042638470327782955003079649
Short name T555
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Nov 22 01:25:41 PM PST 23
Finished Nov 22 01:25:52 PM PST 23
Peak memory 199140 kb
Host smart-b2a9a09f-c1d9-400f-99ef-2c137d24bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65983355520790378859216748840268299127745269975927042638470327782955003079649 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_smoke.65983355520790378859216748840268299127745269975927042638470327782955003079649
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.8158848740163102819057558581744212028333583377181564775396513073245277520531
Short name T313
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.49 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 200868 kb
Host smart-82ffb9dc-500a-47a4-998a-43ff8f5a612b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8158848740163102819057558581744212028333583377181564775396513073245277520531 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.8158848740163102819057558581744212028333583377181564775396513073245277520531
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.112964566046426472682621586286389497899054783283351942172154437411668905740167
Short name T458
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 201192 kb
Host smart-f8bf97d8-fb5e-44b5-ba9b-32821c1f0838
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112964566046426472682621586286389497899054783283351942172154437411668905740167 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.11296456604642647268262158628638949789905478328335194217215
4437411668905740167
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.114902283145285734000584264546713324277299648050139857246612770996806771678308
Short name T634
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:00 PM PST 23
Peak memory 201216 kb
Host smart-20749f59-c1dd-4e8d-acb6-7153a88e0bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114902283145285734000584264546713324277299648050139857246612770996806771678308 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.114902283145285734000584264546713324277299648050139857246612770996806771678308
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.47102996792667211097485917826060731177688943025386039154555339602747830565178
Short name T658
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.52 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201228 kb
Host smart-5a44e809-8448-4d15-8234-f77d587f572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47102996792667211097485917826060731177688943025386039154555339602747830565178 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.47102996792667211097485917826060731177688943025386039154555339602747830565178
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.8024454762436220977273493165138809358933180879661551892803656736282801157735
Short name T387
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.53 seconds
Started Nov 22 01:24:38 PM PST 23
Finished Nov 22 01:27:41 PM PST 23
Peak memory 201448 kb
Host smart-aa1cd044-3953-4697-bb23-d786a7e11560
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8024454762436220977273493165138809358933180879661551892803656736282801157735 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.8024454762436220977273493165138809358933180879661551892803656736282801157735
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4990971782924544628121246049381621607681361426729968138149756143012825597295
Short name T412
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.3 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 201100 kb
Host smart-3694451b-f72b-4ac5-bd2f-50eb77e5129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4990971782924544628121246049381621607681361426729968138149756143012825597295 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.4990971782924544628121246049381621607681361426729968138149756143012825597295
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.69603252768203435730644559922526168049061372132272364875443999731646841537782
Short name T108
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.61 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201200 kb
Host smart-38f8b311-dc4d-4a36-ac27-7e6a3c5215f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69603252768203435730644559922526168049061372132272364875443999731646841537782 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.69603252768203435730644559922526168049061372132272364
875443999731646841537782
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.50831293894385170587739974923939701823412769325794620747977074093035551779604
Short name T184
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.46 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:06 PM PST 23
Peak memory 201136 kb
Host smart-88a3838c-d71d-45a0-80a7-440208bdc2e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50831293894385170587739974923939701823412769325794620747977074093035551779604 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.5083129389438517058773997492393970182341276932579462074797707
4093035551779604
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.84764138463129376218789915114151860398736097613654865713841526502937752925376
Short name T30
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Nov 22 01:23:54 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201068 kb
Host smart-8aedc39a-1b4a-4cd0-8bc7-852a0c8d455b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84764138463129376218789915114151860398736097613654865713841526502937752925376 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.84764138463129376218789915114151860398736097613654865713841526502937752925376
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2272104865621587975410285821798940513479836101412450567996255614264630221605
Short name T234
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 22 01:23:56 PM PST 23
Finished Nov 22 01:24:08 PM PST 23
Peak memory 201168 kb
Host smart-d0145de4-45b8-4add-8771-642c52ebb943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272104865621587975410285821798940513479836101412450567996255614264630221605 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2272104865621587975410285821798940513479836101412450567996255614264630221605
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.93843253575264534729240935661107230534380014725992464894066987055618339961289
Short name T534
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.69 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 200664 kb
Host smart-f2283ac9-6362-452e-9a4e-aa284a37fc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93843253575264534729240935661107230534380014725992464894066987055618339961289 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.93843253575264534729240935661107230534380014725992464894066987055618339961289
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.97332931614251118979075586620016314728122879226181261668558605191982476606398
Short name T166
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 22 01:23:43 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201128 kb
Host smart-c7b67e84-0058-4919-8387-07ca932a4a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97332931614251118979075586620016314728122879226181261668558605191982476606398 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.97332931614251118979075586620016314728122879226181261668558605191982476606398
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.100092399873556963495431588272405073081852447944548570886992771686349775913212
Short name T200
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:19 PM PST 23
Peak memory 201152 kb
Host smart-40bceec7-4e67-47ff-a334-260dc24c1b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100092399873556963495431588272405073081852447944548570886992771686349775913212 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.100092399873556963495431588272405073081852447944548570886992771686349775913212
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.112707345021048401906093448637240262702823872787265867374428673663558755825779
Short name T252
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201144 kb
Host smart-f9e60498-456c-4530-bc94-5b85dd1a68fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112707345021048401906093448637240262702823872787265867374428673663558755825779 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.sysrst_ctrl_smoke.112707345021048401906093448637240262702823872787265867374428673663558755825779
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.4102213448905807350865176044787237163447154754816107539499244310792522421086
Short name T112
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.44 seconds
Started Nov 22 01:23:45 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 201492 kb
Host smart-e5557bb3-782f-494e-9e36-93c781230b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102213448905807350865176044787237163447154754816107539499244310792522421086 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.4102213448905807350865176044787237163447154754816107539499244310792522421086
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.63159702831770049255657565584053220197549699899353067061289405841216891162680
Short name T32
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 201184 kb
Host smart-8b24293d-60c9-480f-8280-e14582da02e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63159702831770049255657565584053220197549699899353067061289405841216891162680 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.6315970283177004925565756558405322019754969989935306706128940
5841216891162680
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.108625155069982215637192629061650033219802483055405809849573249526775904868455
Short name T191
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:57 PM PST 23
Peak memory 201084 kb
Host smart-e802d859-8c9f-4b00-9892-95ee5ee36a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108625155069982215637192629061650033219802483055405809849573249526775904868455 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.108625155069982215637192629061650033219802483055405809849573249526775904868455
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.85108503807171494902484548750355763158706822391024433673975061465258972027472
Short name T116
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Nov 22 01:24:48 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201080 kb
Host smart-b82eefdc-7a35-40cf-9be9-e3c92b042abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85108503807171494902484548750355763158706822391024433673975061465258972027472 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.85108503807171494902484548750355763158706822391024433673975061465258972027472
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.15654171354312268748717036385247057050383939289682793407730555808495447793530
Short name T331
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.99 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:27:57 PM PST 23
Peak memory 201424 kb
Host smart-b08f7a57-1b2a-4139-871d-822947074e71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15654171354312268748717036385247057050383939289682793407730555808495447793530 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.15654171354312268748717036385247057050383939289682793407730555
808495447793530
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.86339441988347549027458478736799275282091540903505475004033489084686146508876
Short name T497
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Nov 22 01:24:58 PM PST 23
Finished Nov 22 01:25:09 PM PST 23
Peak memory 201192 kb
Host smart-28d489a7-61b3-4013-b4f1-3f5226ce5682
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86339441988347549027458478736799275282091540903505475004033489084686146508876 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.863394419883475490274584787367992752820915409035054750040334
89084686146508876
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.115362528238766975437994029198243052295171619590917884933576732401649125484515
Short name T528
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201020 kb
Host smart-66879b5d-cc74-4b71-8d12-844ccb013d25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115362528238766975437994029198243052295171619590917884933576732401649125484515 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.115362528238766975437994029198243052295171619590917884933576732
401649125484515
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.742196529375257159178101485335798601096165303847378185489665157024166154992
Short name T511
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201220 kb
Host smart-fccb6749-978f-4bf8-ac39-738fac56ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742196529375257159178101485335798601096165303847378185489665157024166154992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.742196529375257159178101485335798601096165303847378185489665157024166154992
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.99311827871352695959554003807630128114476302196343263788675681444784537040990
Short name T193
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 22 01:25:40 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 199268 kb
Host smart-581bb2b5-a38e-417b-85cf-4d987b13d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99311827871352695959554003807630128114476302196343263788675681444784537040990 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.99311827871352695959554003807630128114476302196343263788675681444784537040990
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.61277418794972479507080497667436369066363158741042174660199263208899523022262
Short name T341
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:24:48 PM PST 23
Finished Nov 22 01:24:54 PM PST 23
Peak memory 201124 kb
Host smart-5214f555-4440-4016-8155-b2159cfbe884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61277418794972479507080497667436369066363158741042174660199263208899523022262 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.61277418794972479507080497667436369066363158741042174660199263208899523022262
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.59643256220474733798764258496150292224350569029669226799207870777191734275890
Short name T592
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.5 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:24:57 PM PST 23
Peak memory 201132 kb
Host smart-c8858e38-5999-4a40-acc0-1d9ab3ce5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59643256220474733798764258496150292224350569029669226799207870777191734275890 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.59643256220474733798764258496150292224350569029669226799207870777191734275890
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.54797630815462738418528234991000432080874666145508904405458038813977442153022
Short name T322
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:24:52 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201124 kb
Host smart-bc8ca257-60ea-4515-9509-8b932b083325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54797630815462738418528234991000432080874666145508904405458038813977442153022 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sysrst_ctrl_smoke.54797630815462738418528234991000432080874666145508904405458038813977442153022
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.12308716006522392678469512403673394082213184185253636197967987930569936816003
Short name T222
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.85 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:27:07 PM PST 23
Peak memory 201356 kb
Host smart-54bedf87-b296-48ac-af3b-98754ab98b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12308716006522392678469512403673394082213184185253636197967987930569936816003 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.12308716006522392678469512403673394082213184185253636197967987930569936816003
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.4582980516089966862067656549743137817262355714169634106981513199542038918086
Short name T300
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.84 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:25:02 PM PST 23
Peak memory 201020 kb
Host smart-8b9e756c-b31e-4685-a051-ed91e74b8bff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4582980516089966862067656549743137817262355714169634106981513199542038918086 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.4582980516089966862067656549743137817262355714169634106981513
199542038918086
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.25043459001520879006169318441331930217134555553360701703792400019998295494692
Short name T187
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201040 kb
Host smart-3bbf2e2e-0fa0-46a2-8956-727edce5e3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25043459001520879006169318441331930217134555553360701703792400019998295494692 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.25043459001520879006169318441331930217134555553360701703792400019998295494692
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.64026523714176937620112904548089604325778482040721096874920434217399432881149
Short name T39
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.38 seconds
Started Nov 22 01:24:48 PM PST 23
Finished Nov 22 01:24:55 PM PST 23
Peak memory 201272 kb
Host smart-07af20f3-4f0c-47f4-81e8-24045a37705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64026523714176937620112904548089604325778482040721096874920434217399432881149 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.64026523714176937620112904548089604325778482040721096874920434217399432881149
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.101877955239398034339559804433558306035379946083395746985048557897778843054139
Short name T227
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.09 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201268 kb
Host smart-3195054b-6cd0-4b11-8e34-b6b7b110de5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101877955239398034339559804433558306035379946083395746985048557897778843054139 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.1018779552393980343395598044335583060353799460833957469850485
57897778843054139
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.36385254578130828358783448624900991496257797225312768031311814797770274527669
Short name T240
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:25:00 PM PST 23
Peak memory 201240 kb
Host smart-002a1cf8-d5cd-400f-bfe8-323f5037a0fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385254578130828358783448624900991496257797225312768031311814797770274527669 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.363852545781308283587834486249009914962577972253127680313118
14797770274527669
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.4277551797260803274060066378930553502382205004076139537230811327799864195715
Short name T538
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.36 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201024 kb
Host smart-34c6068f-991d-422d-a6b7-5dc9e324de8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277551797260803274060066378930553502382205004076139537230811327799864195715 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.4277551797260803274060066378930553502382205004076139537230811327799864195715
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.42636591222338350897802024012489020485831688203225251126427744830812592588053
Short name T325
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:04 PM PST 23
Peak memory 201168 kb
Host smart-8e557ddc-f237-4b4d-9625-97a6b6c7a9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42636591222338350897802024012489020485831688203225251126427744830812592588053 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.42636591222338350897802024012489020485831688203225251126427744830812592588053
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.107369979461036865097768758180366044955110948673660933766888844079952724198254
Short name T295
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201240 kb
Host smart-d6bf5217-e609-4ed9-9ca6-18a9fb40876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107369979461036865097768758180366044955110948673660933766888844079952724198254 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.107369979461036865097768758180366044955110948673660933766888844079952724198254
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.41716120452500012707327660446913076348994783829510764085392823291564241892845
Short name T631
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:55 PM PST 23
Peak memory 201148 kb
Host smart-4841ebe5-fc01-4b4f-98c4-15eeb91be8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41716120452500012707327660446913076348994783829510764085392823291564241892845 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.41716120452500012707327660446913076348994783829510764085392823291564241892845
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.115036033434082140972906904280882060471720398288088856447165208995023684646885
Short name T584
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201220 kb
Host smart-a5edd69e-462e-4e08-8e45-316d64a30789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115036033434082140972906904280882060471720398288088856447165208995023684646885 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.115036033434082140972906904280882060471720398288088856447165208995023684646885
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.21543815968977273183195059332974716214128887902115950309542757267826902060913
Short name T192
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201136 kb
Host smart-26521228-dab6-459c-9daa-a3915438d932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21543815968977273183195059332974716214128887902115950309542757267826902060913 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_smoke.21543815968977273183195059332974716214128887902115950309542757267826902060913
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.74391282328775101856076490793684498867357288974906192918718733195560290813571
Short name T35
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.44 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:27:08 PM PST 23
Peak memory 201392 kb
Host smart-1bb0043e-cdae-4bd9-953c-e828dbe1c9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74391282328775101856076490793684498867357288974906192918718733195560290813571 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.74391282328775101856076490793684498867357288974906192918718733195560290813571
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.18775181425514978658190437623333253942013881293115564594366597663726709677628
Short name T275
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:57 PM PST 23
Peak memory 201172 kb
Host smart-391359b4-f354-4f23-b477-a28c4fb6b162
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18775181425514978658190437623333253942013881293115564594366597663726709677628 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.187751814255149786581904376233332539420138812931155645943665
97663726709677628
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.99342633429348512489265543702799976233419853269346912652615137357589804050826
Short name T286
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 22 01:25:02 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201224 kb
Host smart-0e2063ad-8328-4684-97d0-9d10d67ce512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99342633429348512489265543702799976233419853269346912652615137357589804050826 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.99342633429348512489265543702799976233419853269346912652615137357589804050826
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.62615210070342122426664836988835024707909296907694853002883821360391766714138
Short name T117
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:25:00 PM PST 23
Peak memory 201352 kb
Host smart-25dbfda2-90b9-4927-b9f8-ca8a2f638998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62615210070342122426664836988835024707909296907694853002883821360391766714138 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.62615210070342122426664836988835024707909296907694853002883821360391766714138
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.39250587267840971615992898726815307195787310012958605496391698048999784488151
Short name T558
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.24 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 201392 kb
Host smart-b69ff398-876c-43ac-bcc7-4b59304ed241
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39250587267840971615992898726815307195787310012958605496391698048999784488151 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.39250587267840971615992898726815307195787310012958605496391698
048999784488151
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.97087349051921645834824800526973381863690635960989119139547632143899003922636
Short name T323
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.43 seconds
Started Nov 22 01:24:57 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201216 kb
Host smart-7c92fe91-3242-498a-8b3a-b0dcb3ca74f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97087349051921645834824800526973381863690635960989119139547632143899003922636 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.970873490519216458348248005269733818636906359609891191395476
32143899003922636
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.93215285891763694936071394474302023228596781144786950629667960269744786822689
Short name T25
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Nov 22 01:24:58 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201064 kb
Host smart-d809d05f-dade-47cc-a82c-e17a275c56cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93215285891763694936071394474302023228596781144786950629667960269744786822689 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.9321528589176369493607139447430202322859678114478695062966796026
9744786822689
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.108375857047397900887047918034554347801018900276856356348701220227118250282057
Short name T549
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201164 kb
Host smart-653e98d2-8ccf-4ec9-8491-62157eb2b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108375857047397900887047918034554347801018900276856356348701220227118250282057 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.108375857047397900887047918034554347801018900276856356348701220227118250282057
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3886899035595427083354941515399163434440683870331486991690157136032775435937
Short name T464
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:25:00 PM PST 23
Peak memory 201240 kb
Host smart-1764007a-b7b7-4252-94f5-0c458d2ed62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886899035595427083354941515399163434440683870331486991690157136032775435937 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3886899035595427083354941515399163434440683870331486991690157136032775435937
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.80337689318666529975382164648784197327192125765118003175746642769426182771703
Short name T460
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201176 kb
Host smart-b2afabb4-28e8-4c10-8f36-5112bc282005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80337689318666529975382164648784197327192125765118003175746642769426182771703 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.80337689318666529975382164648784197327192125765118003175746642769426182771703
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.36744236701781462106901498109196581901166415621037234857438469984984385529770
Short name T394
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 22 01:25:40 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 198880 kb
Host smart-a5136e7e-b601-4121-a767-56703d359624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36744236701781462106901498109196581901166415621037234857438469984984385529770 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.36744236701781462106901498109196581901166415621037234857438469984984385529770
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.29286131656083421823628847078946160343825556291927936814011908349256773679152
Short name T254
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Nov 22 01:25:40 PM PST 23
Finished Nov 22 01:25:52 PM PST 23
Peak memory 198636 kb
Host smart-e61595f9-adc6-4221-92ac-2604720afce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29286131656083421823628847078946160343825556291927936814011908349256773679152 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_smoke.29286131656083421823628847078946160343825556291927936814011908349256773679152
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.61026530221115144989392367769883615034686506387289371299887194033659232813172
Short name T450
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.9 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 201184 kb
Host smart-3a043910-fdc4-415c-b4d6-2aaddc7e5b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61026530221115144989392367769883615034686506387289371299887194033659232813172 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.61026530221115144989392367769883615034686506387289371299887194033659232813172
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.89447373415464393717686808719768943404973242113500487243649843744501123797354
Short name T636
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.64 seconds
Started Nov 22 01:25:42 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 199368 kb
Host smart-2ec3b878-09cc-4b1d-80ca-85a40b6fbd81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89447373415464393717686808719768943404973242113500487243649843744501123797354 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.894473734154643937176868087197689434049732421135004872436498
43744501123797354
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.80134543481801547092605347951019799652438683119013959864140378035025521412272
Short name T378
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Nov 22 01:25:09 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201020 kb
Host smart-1e08dcba-a275-4a90-a570-023f1e3df41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80134543481801547092605347951019799652438683119013959864140378035025521412272 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.80134543481801547092605347951019799652438683119013959864140378035025521412272
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.85524686868193566634167913125475672600717059578174089489828981751095529456034
Short name T492
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.38 seconds
Started Nov 22 01:25:59 PM PST 23
Finished Nov 22 01:26:10 PM PST 23
Peak memory 201004 kb
Host smart-16278ec6-fe62-4c1a-87e3-0848ebdb3f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85524686868193566634167913125475672600717059578174089489828981751095529456034 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.85524686868193566634167913125475672600717059578174089489828981751095529456034
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.84218877927286568350359780986062760218753318384073148647663014535909817770335
Short name T441
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.18 seconds
Started Nov 22 01:25:54 PM PST 23
Finished Nov 22 01:29:04 PM PST 23
Peak memory 198936 kb
Host smart-0a40a561-077d-4ca1-bf53-ce4af8d2138c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84218877927286568350359780986062760218753318384073148647663014535909817770335 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.84218877927286568350359780986062760218753318384073148647663014
535909817770335
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.81196938141352551592660069054958235857956116202037582542441148569983522541808
Short name T260
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201188 kb
Host smart-d9f3ad66-f59f-4175-986d-f9008d1c05aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81196938141352551592660069054958235857956116202037582542441148569983522541808 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.811969381413525515926600690549582358579561162020375825424411
48569983522541808
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.9465356387186737620275212088922864572031384930907187496352111036435192077638
Short name T204
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:25:17 PM PST 23
Peak memory 201140 kb
Host smart-41e9d904-754e-4410-b05e-36f779b2ebde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9465356387186737620275212088922864572031384930907187496352111036435192077638 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.9465356387186737620275212088922864572031384930907187496352111036435192077638
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.90114944998963381690850808624672010816091858952071050903233106392382350586481
Short name T164
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.79 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 198608 kb
Host smart-50a51388-fbd6-4040-a426-7936a40bb6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90114944998963381690850808624672010816091858952071050903233106392382350586481 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.90114944998963381690850808624672010816091858952071050903233106392382350586481
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.25205936827048907398726122316472214740796580472284540224476728298396170808052
Short name T585
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201196 kb
Host smart-01c2130c-e73e-4c9c-9b89-759c815be675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25205936827048907398726122316472214740796580472284540224476728298396170808052 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.25205936827048907398726122316472214740796580472284540224476728298396170808052
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.22802302735683118341633787884362168896092332569353628898156882282020025711237
Short name T462
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.97 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 198492 kb
Host smart-6e0d302b-c1dd-4294-ae9e-431312f9e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22802302735683118341633787884362168896092332569353628898156882282020025711237 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.22802302735683118341633787884362168896092332569353628898156882282020025711237
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.68533471703118624750280090093613919970493187156643697302706296596301038780906
Short name T653
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 198592 kb
Host smart-4b81db27-2f06-4276-b698-2ac7fb8ed02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68533471703118624750280090093613919970493187156643697302706296596301038780906 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.68533471703118624750280090093613919970493187156643697302706296596301038780906
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.105806666250252421934016838835102981848583798194853489426919058254105719857714
Short name T302
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201176 kb
Host smart-42f7d2f7-8cca-42c1-ac21-0548fddbf939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105806666250252421934016838835102981848583798194853489426919058254105719857714 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.sysrst_ctrl_smoke.105806666250252421934016838835102981848583798194853489426919058254105719857714
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.78212120661988715617741052215368236964532586303165568147537478281107685280129
Short name T314
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.21 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:27:24 PM PST 23
Peak memory 201316 kb
Host smart-37a904c8-823d-47e1-93f1-055cda7095ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78212120661988715617741052215368236964532586303165568147537478281107685280129 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.78212120661988715617741052215368236964532586303165568147537478281107685280129
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.19397038325259285140294903498336500725138563113361333332427312108713764568910
Short name T46
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.94 seconds
Started Nov 22 01:25:04 PM PST 23
Finished Nov 22 01:25:12 PM PST 23
Peak memory 201076 kb
Host smart-5bf541ce-6e0d-47d9-8c3b-dccc73084b8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19397038325259285140294903498336500725138563113361333332427312108713764568910 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.193970383252592851402949034983365007251385631133613333324273
12108713764568910
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.17079280503660989388091704851224804534781577715133481649374055648708301686719
Short name T564
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 201184 kb
Host smart-7c0a314c-754c-4154-89ea-1ff3d401fdda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17079280503660989388091704851224804534781577715133481649374055648708301686719 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.17079280503660989388091704851224804534781577715133481649374055648708301686719
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.95598621190609332317543304096531159210799503857811701476686565282706270413502
Short name T236
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 22 01:25:54 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 198856 kb
Host smart-a85edf73-2917-46aa-8a44-ec7af6e19662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95598621190609332317543304096531159210799503857811701476686565282706270413502 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.95598621190609332317543304096531159210799503857811701476686565282706270413502
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.35318276955348435801376259987990611440021203925001730632895553358001891537164
Short name T31
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.59 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:28:14 PM PST 23
Peak memory 201444 kb
Host smart-48776f1e-7949-47c9-ad36-bca2892506ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35318276955348435801376259987990611440021203925001730632895553358001891537164 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.35318276955348435801376259987990611440021203925001730632895553
358001891537164
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.21031885246425164250080763232932048290273743130432857660195513743994274156553
Short name T180
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:16 PM PST 23
Peak memory 201232 kb
Host smart-535d5ce0-f435-49d5-962d-f8432b601e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21031885246425164250080763232932048290273743130432857660195513743994274156553 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.210318852464251642500807632329320482902737431304328576601955
13743994274156553
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.80181821546154793489390583917471772861291319546271283925105899597303286446506
Short name T496
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Nov 22 01:25:07 PM PST 23
Finished Nov 22 01:25:16 PM PST 23
Peak memory 201172 kb
Host smart-ab9e4b9b-73b3-4e2c-b72c-6ced397ae0f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80181821546154793489390583917471772861291319546271283925105899597303286446506 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.8018182154615479348939058391747177286129131954627128392510589959
7303286446506
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.74093583120003033889003759404789752638610068803549622403176003214741971221763
Short name T142
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201208 kb
Host smart-5b6ca3e7-6ea2-4c9b-a17c-e02731b10e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74093583120003033889003759404789752638610068803549622403176003214741971221763 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.74093583120003033889003759404789752638610068803549622403176003214741971221763
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.97296868921130920712139500871442587016206679567546565234775554782721044216551
Short name T504
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201248 kb
Host smart-fa41755d-54f3-4c7f-b214-443486391fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97296868921130920712139500871442587016206679567546565234775554782721044216551 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.97296868921130920712139500871442587016206679567546565234775554782721044216551
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.39036292423231105575364576929543280617066123458682584793144456249881332408054
Short name T403
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:25:00 PM PST 23
Finished Nov 22 01:25:06 PM PST 23
Peak memory 201036 kb
Host smart-4f06c987-b52b-46d6-8051-5e013b7b811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39036292423231105575364576929543280617066123458682584793144456249881332408054 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.39036292423231105575364576929543280617066123458682584793144456249881332408054
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.63644011871186396511623736557327050003613012797126283206979987745224407582610
Short name T659
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.67 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201124 kb
Host smart-64dc5605-4310-4f17-a664-0d51a700e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63644011871186396511623736557327050003613012797126283206979987745224407582610 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.63644011871186396511623736557327050003613012797126283206979987745224407582610
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.112946174505393080220489529347454246812010372902459585745084421788751929524799
Short name T650
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:12 PM PST 23
Peak memory 201080 kb
Host smart-c28796ab-1603-4c63-9eef-460461ddf029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112946174505393080220489529347454246812010372902459585745084421788751929524799 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.sysrst_ctrl_smoke.112946174505393080220489529347454246812010372902459585745084421788751929524799
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2564071275969559940464685595432899256271119606362155271141594240608254782549
Short name T212
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.22 seconds
Started Nov 22 01:25:09 PM PST 23
Finished Nov 22 01:27:28 PM PST 23
Peak memory 201484 kb
Host smart-44410785-5b78-422c-92c2-596f48ec8410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564071275969559940464685595432899256271119606362155271141594240608254782549 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.2564071275969559940464685595432899256271119606362155271141594240608254782549
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.52216971420726938687045126709240383199057432823605631629595655261918658244228
Short name T569
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.66 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 200932 kb
Host smart-387d9385-f98c-4617-8171-90440720214e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52216971420726938687045126709240383199057432823605631629595655261918658244228 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.522169714207269386870451267092403831990574328236056316295956
55261918658244228
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.22235745094998891267048358292249274238168375857007066134270703958035203084072
Short name T434
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201000 kb
Host smart-1a6c0c72-3cea-4eef-aa85-e1dcab065d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22235745094998891267048358292249274238168375857007066134270703958035203084072 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.22235745094998891267048358292249274238168375857007066134270703958035203084072
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.38310923281549931002565355676109458238109381517009197474215425924025590832073
Short name T310
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:25:00 PM PST 23
Peak memory 201260 kb
Host smart-ea723014-296a-4fb2-a8ff-2a177175f7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38310923281549931002565355676109458238109381517009197474215425924025590832073 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.38310923281549931002565355676109458238109381517009197474215425924025590832073
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.42952621524987616196844516333698822635352886587940307157526294635995995266903
Short name T150
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.97 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 201344 kb
Host smart-924717cb-5849-4ca2-9d1f-e855aecdb0cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42952621524987616196844516333698822635352886587940307157526294635995995266903 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.42952621524987616196844516333698822635352886587940307157526294
635995995266903
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.99594740898805387292168966182566869008657081394478564927407186974935366986785
Short name T639
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.58 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:25:00 PM PST 23
Peak memory 201240 kb
Host smart-c345d02d-92b0-4f87-9d86-b883fdc5ec03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99594740898805387292168966182566869008657081394478564927407186974935366986785 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.995947408988053872921689661825668690086570813944785649274071
86974935366986785
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.84015038571514510156256249025921235461093527544634656905935082578709978971744
Short name T589
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:25:02 PM PST 23
Peak memory 201196 kb
Host smart-33d001a1-4b85-41f9-a6b2-5f2f63ed94f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84015038571514510156256249025921235461093527544634656905935082578709978971744 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.8401503857151451015625624902592123546109352754463465690593508257
8709978971744
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.98759750012958510896803574216770341851434160804981947126040551162579716091611
Short name T251
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 22 01:24:48 PM PST 23
Finished Nov 22 01:24:55 PM PST 23
Peak memory 201152 kb
Host smart-20d6897b-2994-4757-bef9-e48bb4ad253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98759750012958510896803574216770341851434160804981947126040551162579716091611 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.98759750012958510896803574216770341851434160804981947126040551162579716091611
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.104009739921733197127712603420190088925218941593253413668524884300884296831671
Short name T357
Test name
Test status
Simulation time 2470384766 ps
CPU time 5.04 seconds
Started Nov 22 01:24:58 PM PST 23
Finished Nov 22 01:25:07 PM PST 23
Peak memory 201120 kb
Host smart-636c9a33-2869-4d89-a383-06d480476355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104009739921733197127712603420190088925218941593253413668524884300884296831671 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.104009739921733197127712603420190088925218941593253413668524884300884296831671
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.24651111323667719034425974347849877849582320316144846452624093792759660711710
Short name T466
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 22 01:24:55 PM PST 23
Finished Nov 22 01:25:02 PM PST 23
Peak memory 201236 kb
Host smart-d0b3db27-ee94-4ed4-ae99-1107ed1a1f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24651111323667719034425974347849877849582320316144846452624093792759660711710 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.24651111323667719034425974347849877849582320316144846452624093792759660711710
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.43756415057158403793265355351168463955893942222089751508745853345848912439113
Short name T532
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 22 01:25:56 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 200964 kb
Host smart-4bd222f9-fe9e-4605-9892-6893184f5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43756415057158403793265355351168463955893942222089751508745853345848912439113 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.43756415057158403793265355351168463955893942222089751508745853345848912439113
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.50418889651993538774165065009788041490793857565302876683180133563335048054380
Short name T536
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Nov 22 01:24:55 PM PST 23
Finished Nov 22 01:25:02 PM PST 23
Peak memory 200960 kb
Host smart-bd47d97d-ae73-4d63-a14b-8222c29df09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50418889651993538774165065009788041490793857565302876683180133563335048054380 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_smoke.50418889651993538774165065009788041490793857565302876683180133563335048054380
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.100332493650129328675963689030537731349489201769324555723470296692977123243978
Short name T292
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.81 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:28:18 PM PST 23
Peak memory 201240 kb
Host smart-ac9d84be-203e-4810-8c5b-6c4d50400ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100332493650129328675963689030537731349489201769324555723470296692977123243978 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.100332493650129328675963689030537731349489201769324555723470296692977123243978
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.82585940822076242498047297885451307740918405596236480565542106222586926448716
Short name T445
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201224 kb
Host smart-edc471ac-5d04-4a08-bfbb-e383fb23d9e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82585940822076242498047297885451307740918405596236480565542106222586926448716 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.825859408220762424980472978854513077409184055962364805655421
06222586926448716
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.65914595807513352645627773352944128357241054990234661383782442364144007291208
Short name T151
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 22 01:24:59 PM PST 23
Finished Nov 22 01:25:06 PM PST 23
Peak memory 201056 kb
Host smart-ba5666fa-fed8-46f0-9058-91979cb6eed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65914595807513352645627773352944128357241054990234661383782442364144007291208 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.65914595807513352645627773352944128357241054990234661383782442364144007291208
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.21708642623946044576836521767948613355029730352044536527140510820721722478392
Short name T210
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.54 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:25:03 PM PST 23
Peak memory 201252 kb
Host smart-0dbe5858-0da1-4532-812c-fa49c767bda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21708642623946044576836521767948613355029730352044536527140510820721722478392 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.21708642623946044576836521767948613355029730352044536527140510820721722478392
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.108674405148677197547097893523047745083981436668778326044574119075096383335045
Short name T416
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.83 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:28:53 PM PST 23
Peak memory 200868 kb
Host smart-8548b46f-7ba5-4764-b357-c6597a748734
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108674405148677197547097893523047745083981436668778326044574119075096383335045 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.1086744051486771975470978935230477450839814366687783260445741
19075096383335045
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.48799697546010537714680523271192915211490271943932722986222492449352296384487
Short name T101
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 22 01:24:58 PM PST 23
Finished Nov 22 01:25:09 PM PST 23
Peak memory 201176 kb
Host smart-22986ed1-1626-4f3c-a9fe-a267b0195b67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48799697546010537714680523271192915211490271943932722986222492449352296384487 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.487996975460105377146805232711929152114902719439327229862224
92449352296384487
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.84447732945002161948454648342695457382777640675071727714321224162419222302863
Short name T495
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201172 kb
Host smart-bc3f5f90-b206-4d5b-8620-51120a564283
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84447732945002161948454648342695457382777640675071727714321224162419222302863 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.8444773294500216194845464834269545738277764067507172771432122416
2419222302863
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.9227867000995027988507842520603563944363102196192228402362692060868776710250
Short name T202
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Nov 22 01:25:42 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 199720 kb
Host smart-704ec123-cde9-4205-a86e-17d567dc5a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9227867000995027988507842520603563944363102196192228402362692060868776710250 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.9227867000995027988507842520603563944363102196192228402362692060868776710250
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.42692474249897880963413110278301817827587178998841235765133531007828033970944
Short name T319
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.85 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 201252 kb
Host smart-0b716c91-9f85-49b8-b796-4459c9c4e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42692474249897880963413110278301817827587178998841235765133531007828033970944 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.42692474249897880963413110278301817827587178998841235765133531007828033970944
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.114333162910900216559435958118515607468865170304098135391930947606799930481537
Short name T147
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:24:57 PM PST 23
Peak memory 201160 kb
Host smart-32060896-385a-4ca2-b8e1-b05ee0ddced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114333162910900216559435958118515607468865170304098135391930947606799930481537 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.114333162910900216559435958118515607468865170304098135391930947606799930481537
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.51722721797317282443535137994089320149597207798951099589028964785368532450833
Short name T666
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Nov 22 01:24:59 PM PST 23
Finished Nov 22 01:25:07 PM PST 23
Peak memory 201084 kb
Host smart-ec679ab8-8481-4d9e-83b2-9fb9a242d9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51722721797317282443535137994089320149597207798951099589028964785368532450833 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.51722721797317282443535137994089320149597207798951099589028964785368532450833
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.57560109903076675505748792510955858458147985135763014573002140169150597146535
Short name T573
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 199904 kb
Host smart-83b2baae-e5a6-4d6e-9fd4-beb6ce7d6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57560109903076675505748792510955858458147985135763014573002140169150597146535 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sysrst_ctrl_smoke.57560109903076675505748792510955858458147985135763014573002140169150597146535
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.8848553407988196416672401251909746157890831456179685775531622355429533998214
Short name T519
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.8 seconds
Started Nov 22 01:24:58 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 201392 kb
Host smart-b97bf217-f520-4c87-b753-6637503f9204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8848553407988196416672401251909746157890831456179685775531622355429533998214 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.8848553407988196416672401251909746157890831456179685775531622355429533998214
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.21577850048408641404125830680519324535842819376970834576889432813375681525140
Short name T627
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 22 01:24:57 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201172 kb
Host smart-2197ae0c-df15-415c-96a6-5fd90b72c91e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577850048408641404125830680519324535842819376970834576889432813375681525140 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.215778500484086414041258306805193245358428193769708345768894
32813375681525140
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.26645737244234499353351077288521236225641436351072087446032616773256287457074
Short name T333
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:03 PM PST 23
Peak memory 201100 kb
Host smart-3699e49c-2047-4a6f-944d-58ef4cc33537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645737244234499353351077288521236225641436351072087446032616773256287457074 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.26645737244234499353351077288521236225641436351072087446032616773256287457074
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.44881465261490639695983032693866400753598589279128040038159007409956538227193
Short name T305
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.52 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:06 PM PST 23
Peak memory 201072 kb
Host smart-548811e3-7548-4579-b960-57c21488b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44881465261490639695983032693866400753598589279128040038159007409956538227193 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.44881465261490639695983032693866400753598589279128040038159007409956538227193
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.33317188018129746763066254393328641675597879635613350590006574984665050096609
Short name T485
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.54 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 201492 kb
Host smart-eb43422f-1e62-4956-bd2a-95e95176c739
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33317188018129746763066254393328641675597879635613350590006574984665050096609 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.33317188018129746763066254393328641675597879635613350590006574
984665050096609
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.27369932639684782784025791461518241419805979532555426190666636556504476875307
Short name T218
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 201052 kb
Host smart-915160d1-b5f0-4631-864d-cbdb3ac94ebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369932639684782784025791461518241419805979532555426190666636556504476875307 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.273699326396847827840257914615182414198059795325554261906666
36556504476875307
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.19099998612721818806159593473634103766990601132533883756408911310364303700786
Short name T609
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:25:00 PM PST 23
Peak memory 201184 kb
Host smart-56eb3d6b-a7a9-4508-ab3e-75df26be1c9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099998612721818806159593473634103766990601132533883756408911310364303700786 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.1909999861272181880615959347363410376699060113253388375640891131
0364303700786
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.30539002386234683282677437483223822305101992475507008267330621451164532662282
Short name T393
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 22 01:25:42 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 199236 kb
Host smart-386cf5c5-7374-4e78-b8b2-18e860fc494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30539002386234683282677437483223822305101992475507008267330621451164532662282 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.30539002386234683282677437483223822305101992475507008267330621451164532662282
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.54447402141429965341736175239384457341797007715576391216055647007291007766168
Short name T340
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201232 kb
Host smart-3ffa4fd0-53d0-4003-98a1-57e3b1acebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54447402141429965341736175239384457341797007715576391216055647007291007766168 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.54447402141429965341736175239384457341797007715576391216055647007291007766168
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.65015399222494735269634237434388907976241982361133008629704405280318507436252
Short name T667
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 22 01:24:57 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201168 kb
Host smart-fbf1b8b1-9bbb-4229-89ca-cbf3e488278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65015399222494735269634237434388907976241982361133008629704405280318507436252 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.65015399222494735269634237434388907976241982361133008629704405280318507436252
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.50947482306461562799296943143320119087909291509180564618097198987002901740293
Short name T175
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Nov 22 01:24:59 PM PST 23
Finished Nov 22 01:25:07 PM PST 23
Peak memory 201084 kb
Host smart-379fb42b-2c98-42be-bd26-211e4f01df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50947482306461562799296943143320119087909291509180564618097198987002901740293 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.50947482306461562799296943143320119087909291509180564618097198987002901740293
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.21137378230545771775540088894673829065853517648076377734843654602658214494712
Short name T208
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 201060 kb
Host smart-33285d4a-c809-4d0a-bbfe-f021fa72c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21137378230545771775540088894673829065853517648076377734843654602658214494712 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_smoke.21137378230545771775540088894673829065853517648076377734843654602658214494712
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.72307438700723683525424050160606280671003843367926120556417214856514596408461
Short name T217
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.89 seconds
Started Nov 22 01:25:07 PM PST 23
Finished Nov 22 01:27:26 PM PST 23
Peak memory 201308 kb
Host smart-c3d8758f-c2c8-475b-904a-4d10b3e8a87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72307438700723683525424050160606280671003843367926120556417214856514596408461 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.72307438700723683525424050160606280671003843367926120556417214856514596408461
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.24535352116201846503337091827623765567123427281686405828591682386800883942924
Short name T475
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 200876 kb
Host smart-93aea1e9-bff9-4cca-a5df-cd25218e62b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24535352116201846503337091827623765567123427281686405828591682386800883942924 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.245353521162018465033370918276237655671234272816864058285916
82386800883942924
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.81309312803098769251698148380143465256699013200998559575495129569816981336689
Short name T197
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Nov 22 01:25:04 PM PST 23
Finished Nov 22 01:25:11 PM PST 23
Peak memory 201236 kb
Host smart-cc7138ed-f8f3-48f6-8b1f-e13c401f839b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81309312803098769251698148380143465256699013200998559575495129569816981336689 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.81309312803098769251698148380143465256699013200998559575495129569816981336689
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.115248613749898929690699820156419611673712118397392204796533324100229556258395
Short name T406
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Nov 22 01:25:09 PM PST 23
Finished Nov 22 01:25:17 PM PST 23
Peak memory 201240 kb
Host smart-5117d4bf-2301-434e-af04-5e210a178283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115248613749898929690699820156419611673712118397392204796533324100229556258395 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.115248613749898929690699820156419611673712118397392204796533324100229556258395
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.12872475429086133105589939600381369321950889363630605333708943906183357352286
Short name T33
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.24 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 201492 kb
Host smart-58c46e4c-1e22-4d8f-b9f4-af60df26cae2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872475429086133105589939600381369321950889363630605333708943906183357352286 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.12872475429086133105589939600381369321950889363630605333708943
906183357352286
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.26702068568909959857672254205324314525932470462621508137159351075194679938998
Short name T383
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.52 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:08 PM PST 23
Peak memory 201148 kb
Host smart-b3b2fe32-e5ca-4c5b-9ddf-10a1e5273d4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26702068568909959857672254205324314525932470462621508137159351075194679938998 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.267020685689099598576722542053243145259324704626215081371593
51075194679938998
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.90295239999915250787576828207578150623204615691065913629101639957913336117035
Short name T226
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201028 kb
Host smart-02ac8d17-c8e7-4cb7-ae7c-6549e35390c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90295239999915250787576828207578150623204615691065913629101639957913336117035 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.9029523999991525078757682820757815062320461569106591362910163995
7913336117035
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.35467642970760909955457554778050775732672322388171053000779041480202122605261
Short name T297
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201188 kb
Host smart-fe7c7099-0bae-4bd4-a40d-50036e9a9f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35467642970760909955457554778050775732672322388171053000779041480202122605261 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.35467642970760909955457554778050775732672322388171053000779041480202122605261
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.91412529919188448888225435714211709367449563670760913688631799460868244169125
Short name T95
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.71 seconds
Started Nov 22 01:25:59 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 200984 kb
Host smart-7cbed9fe-d1d4-4f40-a229-07ecba1849f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91412529919188448888225435714211709367449563670760913688631799460868244169125 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.91412529919188448888225435714211709367449563670760913688631799460868244169125
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.69531217009592915088340980914470236494299149080917295067620662239888997243884
Short name T644
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 22 01:25:07 PM PST 23
Finished Nov 22 01:25:14 PM PST 23
Peak memory 201112 kb
Host smart-b146ddf4-24d2-453f-ad81-10300ce0d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69531217009592915088340980914470236494299149080917295067620662239888997243884 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.69531217009592915088340980914470236494299149080917295067620662239888997243884
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.48065765051315104088434512143493218450172687669106063172218424314467470178558
Short name T207
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201064 kb
Host smart-ac31cb30-74dd-40d8-af64-50976fe64546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48065765051315104088434512143493218450172687669106063172218424314467470178558 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.48065765051315104088434512143493218450172687669106063172218424314467470178558
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.24839464986322023406822998140085295041974832005780267197781631565945522500804
Short name T337
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 22 01:25:04 PM PST 23
Finished Nov 22 01:25:11 PM PST 23
Peak memory 201080 kb
Host smart-a67050b0-43ed-4811-9ec2-684523b39dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24839464986322023406822998140085295041974832005780267197781631565945522500804 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_smoke.24839464986322023406822998140085295041974832005780267197781631565945522500804
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.107421012417700198382357196568128588970573912496390442390745103410455790771352
Short name T238
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.56 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:27:24 PM PST 23
Peak memory 201480 kb
Host smart-c32605cc-d79f-4a8e-927e-1068a334f07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107421012417700198382357196568128588970573912496390442390745103410455790771352 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.107421012417700198382357196568128588970573912496390442390745103410455790771352
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.9381561812251537915205901635888984645325702436596971295009280676977030647444
Short name T545
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:25:14 PM PST 23
Peak memory 201028 kb
Host smart-d354afde-0a5e-4fbf-b514-9742e8436bc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9381561812251537915205901635888984645325702436596971295009280676977030647444 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.9381561812251537915205901635888984645325702436596971295009280
676977030647444
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.8498789828922544747984467537930599565208681435799853433149390278552650875946
Short name T279
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.6 seconds
Started Nov 22 01:24:53 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 201204 kb
Host smart-c73314d5-e328-43dc-9c23-ca8712c71e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8498789828922544747984467537930599565208681435799853433149390278552650875946 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.8498789828922544747984467537930599565208681435799853433149390278552650875946
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.24303004246526595144280044771904558198169858133223192037020927239505087802510
Short name T385
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 22 01:25:09 PM PST 23
Finished Nov 22 01:25:17 PM PST 23
Peak memory 201192 kb
Host smart-2f966a73-de10-46c0-9c5f-e7c32106ab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24303004246526595144280044771904558198169858133223192037020927239505087802510 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.24303004246526595144280044771904558198169858133223192037020927239505087802510
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.38856480501955195032386353887926205159286820619107595177495849944193749153963
Short name T255
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.21 seconds
Started Nov 22 01:25:09 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 201252 kb
Host smart-99234c04-071c-4429-86ff-3e5c0978ea3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38856480501955195032386353887926205159286820619107595177495849944193749153963 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.38856480501955195032386353887926205159286820619107595177495849
944193749153963
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.34173709838517439540736262104906204465842012554781322477341271828490589996220
Short name T469
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:26 PM PST 23
Peak memory 200964 kb
Host smart-d7a496dc-ff40-4d43-b583-1780318d3c7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173709838517439540736262104906204465842012554781322477341271828490589996220 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.341737098385174395407362621049062044658420125547813224773412
71828490589996220
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.76844943241812142766151692029849022575587324284947754631411240722438064430636
Short name T423
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Nov 22 01:25:12 PM PST 23
Finished Nov 22 01:25:19 PM PST 23
Peak memory 201144 kb
Host smart-835641d2-923d-4583-a413-385ffd282d36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76844943241812142766151692029849022575587324284947754631411240722438064430636 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.7684494324181214276615169202984902257558732428494775463141124072
2438064430636
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.7093471340101044436809530846405667243261087592235898240145617881077798920899
Short name T105
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 200944 kb
Host smart-f23f3e96-7266-4485-bc9a-23b3e9aca4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7093471340101044436809530846405667243261087592235898240145617881077798920899 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.7093471340101044436809530846405667243261087592235898240145617881077798920899
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.735982823494190768200047920108097540354452551573125364474313837751852966009
Short name T97
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 22 01:25:05 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201224 kb
Host smart-4513ed43-9973-47a9-ab50-1430dfefd977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735982823494190768200047920108097540354452551573125364474313837751852966009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.735982823494190768200047920108097540354452551573125364474313837751852966009
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.16709329046275112461545079285316545456525084464165662130929096204017257080517
Short name T651
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:25:14 PM PST 23
Peak memory 201184 kb
Host smart-74e6f78e-c372-4ff9-9851-983c1a6c28b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16709329046275112461545079285316545456525084464165662130929096204017257080517 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.16709329046275112461545079285316545456525084464165662130929096204017257080517
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.75050910938462535923216609822488434339202596168886771833960165988351117526484
Short name T139
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 200648 kb
Host smart-272f1065-dd15-4665-9d55-42a5f42afe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75050910938462535923216609822488434339202596168886771833960165988351117526484 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.75050910938462535923216609822488434339202596168886771833960165988351117526484
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.105228134966807631357607765892211261554214672229048971609973629630288408540929
Short name T135
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:22 PM PST 23
Peak memory 200872 kb
Host smart-8246ca46-92e8-417d-a75c-20c3f0d60b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105228134966807631357607765892211261554214672229048971609973629630288408540929 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.sysrst_ctrl_smoke.105228134966807631357607765892211261554214672229048971609973629630288408540929
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.104698917535405171523474298554883447577503876747431302386654798152279933103069
Short name T294
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.98 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 199932 kb
Host smart-ba09f13d-2f4f-4738-8561-dd05bf604791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104698917535405171523474298554883447577503876747431302386654798152279933103069 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.104698917535405171523474298554883447577503876747431302386654798152279933103069
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.11434851609864710779935737664536294727722702604118462829354242067761146131458
Short name T523
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:25:10 PM PST 23
Finished Nov 22 01:25:16 PM PST 23
Peak memory 201184 kb
Host smart-274d29a1-4df3-4322-87da-08c61973788b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434851609864710779935737664536294727722702604118462829354242067761146131458 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.114348516098647107799357376645362947277227026041184628293542
42067761146131458
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.107477001449705715603817941387253917521967046749043685147648931464187679759368
Short name T407
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 22 01:24:19 PM PST 23
Finished Nov 22 01:24:27 PM PST 23
Peak memory 201224 kb
Host smart-ec21edaa-1f6e-4c68-8367-2246d286fdfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107477001449705715603817941387253917521967046749043685147648931464187679759368 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.107477001449705715603817941387253917521967046749043685147648931464187679759368
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.32273272311262023384665350918056038103923295128667638732992935175224298774864
Short name T41
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201088 kb
Host smart-8e7de37b-e356-40c6-8334-9a60d96649d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32273272311262023384665350918056038103923295128667638732992935175224298774864 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.32273272311262023384665350918056038103923295128667638732992935175224298774864
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.96800146598520394534894362435395586647162494284870655949843705538673524383299
Short name T231
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.73 seconds
Started Nov 22 01:23:53 PM PST 23
Finished Nov 22 01:27:03 PM PST 23
Peak memory 201444 kb
Host smart-8baf7534-53a4-4b6e-80ac-142a3564c997
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96800146598520394534894362435395586647162494284870655949843705538673524383299 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.968001465985203945348943624353955866471624942848706559498437055
38673524383299
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.94179202173480699246893389785572422080171926731457208493489161316879710278540
Short name T133
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.43 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 01:23:39 PM PST 23
Peak memory 201200 kb
Host smart-1678c9ea-173b-4c01-bae1-bac6a35ed5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94179202173480699246893389785572422080171926731457208493489161316879710278540 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.94179202173480699246893389785572422080171926731457208493489161316879710278540
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.29235042980823532365233161353978502543162568367854595288153777297346367769685
Short name T109
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.5 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:01 PM PST 23
Peak memory 201156 kb
Host smart-92b93dad-3018-4594-aaae-5ba85c657c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29235042980823532365233161353978502543162568367854595288153777297346367769685 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.29235042980823532365233161353978502543162568367854595
288153777297346367769685
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.89638187992530061312920629684109798496940322429262780393938174001379212989467
Short name T526
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:23:27 PM PST 23
Finished Nov 22 01:23:49 PM PST 23
Peak memory 200384 kb
Host smart-28b9a743-70c8-483e-b694-a5688492d87a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89638187992530061312920629684109798496940322429262780393938174001379212989467 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.8963818799253006131292062968410979849694032242926278039393817
4001379212989467
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.58043632081298831585006675770174918328636586118138934493385721387565877168703
Short name T455
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 22 01:23:36 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201172 kb
Host smart-f31f9625-2094-41b1-aa85-0e2146e73e0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58043632081298831585006675770174918328636586118138934493385721387565877168703 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.58043632081298831585006675770174918328636586118138934493385721387565877168703
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.61402263121765695503255727597634907969221060494164379300213982829372871622613
Short name T488
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201100 kb
Host smart-edd339ff-f5e7-45b2-95f4-ec7834225307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61402263121765695503255727597634907969221060494164379300213982829372871622613 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.61402263121765695503255727597634907969221060494164379300213982829372871622613
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.112857186701106421690241266063839650909574042619909924769580405642122593924997
Short name T668
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201144 kb
Host smart-673f23cd-786b-4718-ba8f-8202afea0784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112857186701106421690241266063839650909574042619909924769580405642122593924997 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.112857186701106421690241266063839650909574042619909924769580405642122593924997
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.95345062771816686952409468464514224810157913900510781307869157829494750098439
Short name T438
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201184 kb
Host smart-81fe3144-9b66-4739-9f99-5eb32ce7bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95345062771816686952409468464514224810157913900510781307869157829494750098439 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.95345062771816686952409468464514224810157913900510781307869157829494750098439
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.87713284592207979982101344273901298929490999512989919583052144611992356050324
Short name T168
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:24:03 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 201172 kb
Host smart-1769d5b9-46f7-45ba-9316-693b6b381a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87713284592207979982101344273901298929490999512989919583052144611992356050324 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.87713284592207979982101344273901298929490999512989919583052144611992356050324
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.99933570218686089462339448544911706380338184546978618131190420884409234723326
Short name T124
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.44 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:25:44 PM PST 23
Peak memory 221448 kb
Host smart-273ef108-5def-4619-83a8-0ba646e9fe3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99933570218686089462339448544911706380338184546978618131190420884409234723326 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.99933570218686089462339448544911706380338184546978618131190420884409234723326
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.14004683918265519477446645671109458226127598271167269383174204109112714400358
Short name T351
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201148 kb
Host smart-1e26dc01-a644-4825-8ff4-9a7a8c7a09fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14004683918265519477446645671109458226127598271167269383174204109112714400358 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_smoke.14004683918265519477446645671109458226127598271167269383174204109112714400358
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.85594034881806628845375831574073675941418781860071140131587885265306320044464
Short name T201
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.23 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:26:04 PM PST 23
Peak memory 201460 kb
Host smart-530bcf74-8c2b-4735-a3b5-ef67387a5293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85594034881806628845375831574073675941418781860071140131587885265306320044464 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.85594034881806628845375831574073675941418781860071140131587885265306320044464
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.56198471915480006691419388340550673481097824495672606999223332015177091373046
Short name T615
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:23:51 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201048 kb
Host smart-9f042beb-91f4-4b30-b478-1cc0626d0263
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56198471915480006691419388340550673481097824495672606999223332015177091373046 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.5619847191548000669141938834055067348109782449567260699922333
2015177091373046
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.76810604859875613187269625838467350550191720990288163397694947377873734522799
Short name T599
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 22 01:24:54 PM PST 23
Finished Nov 22 01:25:02 PM PST 23
Peak memory 201212 kb
Host smart-4a85a39a-2f8d-49db-afbe-83702600cc46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76810604859875613187269625838467350550191720990288163397694947377873734522799 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.76810604859875613187269625838467350550191720990288163397694947377873734522799
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.61928182658510201779744581286064516845108092975301088908816838763080489473727
Short name T535
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 22 01:24:50 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201192 kb
Host smart-e84e9395-de1b-411d-a782-b49793285974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61928182658510201779744581286064516845108092975301088908816838763080489473727 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.61928182658510201779744581286064516845108092975301088908816838763080489473727
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.111782254153664953548352724364258294376221297455918857679537949358889293574173
Short name T657
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.9 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:28:52 PM PST 23
Peak memory 198920 kb
Host smart-a97f1560-9a1e-4776-8e9c-4d32670405bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111782254153664953548352724364258294376221297455918857679537949358889293574173 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.1117822541536649535483527243642582943762212974559188576795379
49358889293574173
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.60056053251149125599887628291443343570646391488082453324494574154463965336160
Short name T499
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Nov 22 01:24:55 PM PST 23
Finished Nov 22 01:25:07 PM PST 23
Peak memory 201180 kb
Host smart-db844c79-20a9-499a-855d-0efd7b673a4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60056053251149125599887628291443343570646391488082453324494574154463965336160 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.600560532511491255998876282914433435706463914880824533244945
74154463965336160
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.49212472684853761167473809519981528471356302060202383779655281257523109362656
Short name T603
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.35 seconds
Started Nov 22 01:25:40 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 198700 kb
Host smart-488f4382-478e-4e8c-9915-88acf51a2495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49212472684853761167473809519981528471356302060202383779655281257523109362656 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.4921247268485376116747380951998152847135630206020238377965528125
7523109362656
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.86636476037543841885341952368674023864198708684421832151738110257056157233510
Short name T483
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Nov 22 01:24:49 PM PST 23
Finished Nov 22 01:24:57 PM PST 23
Peak memory 200984 kb
Host smart-f0be54f9-68e3-479e-9d21-3433d450edda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86636476037543841885341952368674023864198708684421832151738110257056157233510 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.86636476037543841885341952368674023864198708684421832151738110257056157233510
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.83469478933699993513640721378380927277181396739153556036562362498886146052769
Short name T103
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Nov 22 01:25:07 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201240 kb
Host smart-2976616a-1465-43a5-aa66-318e0bf8031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83469478933699993513640721378380927277181396739153556036562362498886146052769 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.83469478933699993513640721378380927277181396739153556036562362498886146052769
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.43159119930222733686331919390009120286184354204603707664613054372228003761834
Short name T259
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201156 kb
Host smart-d967160a-b672-4af2-9dc7-01852081a325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43159119930222733686331919390009120286184354204603707664613054372228003761834 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.43159119930222733686331919390009120286184354204603707664613054372228003761834
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.14174220006465001163523852875000534068091771325741819133119925937877679069423
Short name T587
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 22 01:24:57 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201192 kb
Host smart-f95c9791-f750-4c22-a96b-9200a37b2b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14174220006465001163523852875000534068091771325741819133119925937877679069423 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.14174220006465001163523852875000534068091771325741819133119925937877679069423
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.34673048375740181781902011295439763158590921174410497604327496411916189523324
Short name T591
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 198624 kb
Host smart-669c7918-7026-453c-aeb4-2db0e4e94fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34673048375740181781902011295439763158590921174410497604327496411916189523324 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_smoke.34673048375740181781902011295439763158590921174410497604327496411916189523324
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.92816237079911343685232971142673487265908426636617670438663355357632200428449
Short name T478
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.73 seconds
Started Nov 22 01:24:52 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 201440 kb
Host smart-2127baeb-6036-4c27-9811-89f18c4579c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92816237079911343685232971142673487265908426636617670438663355357632200428449 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.92816237079911343685232971142673487265908426636617670438663355357632200428449
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.63134713207439773724648899514400613693317431926512816571981406921965434350957
Short name T568
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Nov 22 01:24:56 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 201176 kb
Host smart-e486a47e-82b9-4ef3-a6c4-3f468189ec9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63134713207439773724648899514400613693317431926512816571981406921965434350957 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.631347132074397737246488995144006136933174319265128165719814
06921965434350957
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.78287885560934355287282860521677365280017217694990784078961877571159368916861
Short name T362
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 201236 kb
Host smart-dc6b3cb3-b779-4d92-afb2-f9c8787ac401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78287885560934355287282860521677365280017217694990784078961877571159368916861 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.78287885560934355287282860521677365280017217694990784078961877571159368916861
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.92127821315313334838749237404705952737833786908300764528307269246635610432397
Short name T203
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Nov 22 01:25:55 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 200880 kb
Host smart-8b892bbb-ed46-48aa-b572-aac4eb01cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92127821315313334838749237404705952737833786908300764528307269246635610432397 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.92127821315313334838749237404705952737833786908300764528307269246635610432397
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.94693025678122502048101845649264368866742732298364220560473117039723596553031
Short name T440
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.41 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:28:52 PM PST 23
Peak memory 199180 kb
Host smart-e373d8df-218a-4187-a3b8-f522cbfd08a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94693025678122502048101845649264368866742732298364220560473117039723596553031 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.94693025678122502048101845649264368866742732298364220560473117
039723596553031
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.40457934808977295740007913430194810989563571376719117816853799937565884853904
Short name T567
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:10 PM PST 23
Peak memory 200988 kb
Host smart-a24aeef4-63bf-4a48-8317-a559842ebc4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457934808977295740007913430194810989563571376719117816853799937565884853904 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.404579348089772957400079134301948109895635713767191178168537
99937565884853904
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.36626834901396610471467300164107803215479959780519788918047488519102819091304
Short name T386
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 22 01:25:02 PM PST 23
Finished Nov 22 01:25:10 PM PST 23
Peak memory 201080 kb
Host smart-3babcb40-8cf3-4f71-b394-efa4392aa0f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626834901396610471467300164107803215479959780519788918047488519102819091304 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.3662683490139661047146730016410780321547995978051978891804748851
9102819091304
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.85598001561631539075646663694185967241195451078975250621738605685645286083793
Short name T256
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 199796 kb
Host smart-f0d81e47-2136-45f1-aaec-b4b991d785a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85598001561631539075646663694185967241195451078975250621738605685645286083793 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.85598001561631539075646663694185967241195451078975250621738605685645286083793
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.46136775166218986140947329895905018972323923262025510946323317259695905258742
Short name T502
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 201004 kb
Host smart-b2357152-6c3c-4cce-90ab-f9705d66108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46136775166218986140947329895905018972323923262025510946323317259695905258742 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.46136775166218986140947329895905018972323923262025510946323317259695905258742
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.80946273384892489183478408454155917198456152465635704971209849499646479393702
Short name T409
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 200932 kb
Host smart-900b8ba8-b613-4b45-808e-173dd92a09c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80946273384892489183478408454155917198456152465635704971209849499646479393702 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.80946273384892489183478408454155917198456152465635704971209849499646479393702
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.88763594761742899792748050010860800982415138478511475932941269483102821144077
Short name T320
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Nov 22 01:25:41 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 199300 kb
Host smart-c71d81e5-6493-496f-b22d-44bb3c5882ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88763594761742899792748050010860800982415138478511475932941269483102821144077 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.88763594761742899792748050010860800982415138478511475932941269483102821144077
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.97210900770361996282628555260344474503694939010244023904242807664448855259975
Short name T194
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Nov 22 01:24:51 PM PST 23
Finished Nov 22 01:24:58 PM PST 23
Peak memory 201124 kb
Host smart-e8ce38cd-8b6a-44e9-8e42-3d3a89410638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97210900770361996282628555260344474503694939010244023904242807664448855259975 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_smoke.97210900770361996282628555260344474503694939010244023904242807664448855259975
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.94824615403483959674735147494857205176212512939612579705496674048781234888512
Short name T181
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.08 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 199112 kb
Host smart-05845898-a4db-4071-8bb4-4276abcbd335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94824615403483959674735147494857205176212512939612579705496674048781234888512 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.94824615403483959674735147494857205176212512939612579705496674048781234888512
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.105558830874567564194754359183836193070636763484586115487488484370251047747034
Short name T44
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 22 01:24:57 PM PST 23
Finished Nov 22 01:25:06 PM PST 23
Peak memory 201196 kb
Host smart-7753fd6f-d9fa-408d-918d-2578ddefb201
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105558830874567564194754359183836193070636763484586115487488484370251047747034 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.10555883087456756419475435918383619307063676348458611548748
8484370251047747034
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.89994059794960213921432009029131832410585557287331545454262668340733305085034
Short name T243
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 200648 kb
Host smart-73a14b00-18e7-44c8-a939-ef9a34a25f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89994059794960213921432009029131832410585557287331545454262668340733305085034 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.89994059794960213921432009029131832410585557287331545454262668340733305085034
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.105599307955714501824750261598318968820661851238030251484136834282030733625645
Short name T480
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Nov 22 01:25:03 PM PST 23
Finished Nov 22 01:25:10 PM PST 23
Peak memory 201088 kb
Host smart-e02e8408-c45b-4303-826d-a3914ad21692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105599307955714501824750261598318968820661851238030251484136834282030733625645 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.105599307955714501824750261598318968820661851238030251484136834282030733625645
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.11797905604060677639955956561227827230213229538837784755391801733429584344571
Short name T273
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.9 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:28:53 PM PST 23
Peak memory 199344 kb
Host smart-c2155825-a7e4-4eb8-9c2b-40a1983178ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11797905604060677639955956561227827230213229538837784755391801733429584344571 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.11797905604060677639955956561227827230213229538837784755391801
733429584344571
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.79578578102228775783045640109923025487746050702692275292745192680486949917457
Short name T373
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Nov 22 01:25:06 PM PST 23
Finished Nov 22 01:25:17 PM PST 23
Peak memory 201204 kb
Host smart-80f67647-78bf-4faf-ad80-92c2568ef511
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79578578102228775783045640109923025487746050702692275292745192680486949917457 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.795785781022287757830456401099230254877460507026922752927451
92680486949917457
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.21838424925672263510296233326336875858767850443316954950624690473741793829567
Short name T111
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.53 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 199004 kb
Host smart-fd4f1627-9bfe-4cf8-bd36-f67bf37f4dec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21838424925672263510296233326336875858767850443316954950624690473741793829567 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.2183842492567226351029623332633687585876785044331695495062469047
3741793829567
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.21033166551177345525061310445756942733117120366857932058619068491302781512781
Short name T559
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 201180 kb
Host smart-812d56c4-aab9-48bf-901a-591067fe0de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21033166551177345525061310445756942733117120366857932058619068491302781512781 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.21033166551177345525061310445756942733117120366857932058619068491302781512781
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.86562086877631657710437678629438179226576555455862828246071096431297704088220
Short name T402
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.94 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 198700 kb
Host smart-1c036f35-145c-4cf8-9345-f3b9d31aeb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86562086877631657710437678629438179226576555455862828246071096431297704088220 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.86562086877631657710437678629438179226576555455862828246071096431297704088220
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.89448073939758309938657121240292843320575248896818866251320502464949681590322
Short name T284
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Nov 22 01:25:07 PM PST 23
Finished Nov 22 01:25:14 PM PST 23
Peak memory 201188 kb
Host smart-226da29b-baec-4d54-a56f-8dc71d9bb3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89448073939758309938657121240292843320575248896818866251320502464949681590322 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.89448073939758309938657121240292843320575248896818866251320502464949681590322
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.45608772567008491103906167901794490690552298409443750295206735773243677334338
Short name T580
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Nov 22 01:25:04 PM PST 23
Finished Nov 22 01:25:12 PM PST 23
Peak memory 201208 kb
Host smart-b9ac2c12-35dc-4295-8b54-9f13894dd25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45608772567008491103906167901794490690552298409443750295206735773243677334338 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.45608772567008491103906167901794490690552298409443750295206735773243677334338
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.85152782044685782830248854178972260408710433306912855552967673587623906140070
Short name T552
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.92 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 198424 kb
Host smart-bdcac8bb-5cd9-4ef2-abf8-a3efb79b7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85152782044685782830248854178972260408710433306912855552967673587623906140070 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sysrst_ctrl_smoke.85152782044685782830248854178972260408710433306912855552967673587623906140070
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.40985039445007254475537716776403786771529535136383182109293860131074801366203
Short name T515
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.6 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:27:26 PM PST 23
Peak memory 201476 kb
Host smart-f7968bcd-b53a-41e0-ae14-b3837ffb30dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985039445007254475537716776403786771529535136383182109293860131074801366203 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.40985039445007254475537716776403786771529535136383182109293860131074801366203
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.31737073681736932442838380948181110534193138787687322766012309246839949254180
Short name T426
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 22 01:25:09 PM PST 23
Finished Nov 22 01:25:16 PM PST 23
Peak memory 201004 kb
Host smart-2f3d849e-e301-489b-9b6f-dabf96045332
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737073681736932442838380948181110534193138787687322766012309246839949254180 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.317370736817369324428383809481811105341931387876873227660123
09246839949254180
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.2558186610316392103630794125120392415512885234851795253724553356690708708513
Short name T594
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:25:24 PM PST 23
Finished Nov 22 01:25:30 PM PST 23
Peak memory 201200 kb
Host smart-9f0ff8ca-7f8a-499c-8aa2-1e658752d8b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558186610316392103630794125120392415512885234851795253724553356690708708513 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.2558186610316392103630794125120392415512885234851795253724553356690708708513
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.75713312376914316627171470235168333145909337606741698240932916489896826757434
Short name T91
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 22 01:25:35 PM PST 23
Finished Nov 22 01:25:50 PM PST 23
Peak memory 201204 kb
Host smart-b4d5ac82-351f-4b57-a0bf-7c39f41404e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75713312376914316627171470235168333145909337606741698240932916489896826757434 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.75713312376914316627171470235168333145909337606741698240932916489896826757434
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.22624720595429393796395066575144308765079996854728861163752640202995275604515
Short name T221
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.63 seconds
Started Nov 22 01:25:36 PM PST 23
Finished Nov 22 01:28:47 PM PST 23
Peak memory 201452 kb
Host smart-e751a9ca-28ed-4cac-acaf-60e33cd8df82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22624720595429393796395066575144308765079996854728861163752640202995275604515 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.22624720595429393796395066575144308765079996854728861163752640
202995275604515
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.23873821207659531632130811689582791157539596587638426611310115103108372251624
Short name T553
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 22 01:25:22 PM PST 23
Finished Nov 22 01:25:30 PM PST 23
Peak memory 201228 kb
Host smart-655a0fce-995e-4563-80c3-e876c8ee9524
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873821207659531632130811689582791157539596587638426611310115103108372251624 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.238738212076595316321308116895827911575395965876384266113101
15103108372251624
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.66236345566471749325887820394147465946580520567473807988163691915162239691662
Short name T547
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 22 01:25:32 PM PST 23
Finished Nov 22 01:25:45 PM PST 23
Peak memory 201128 kb
Host smart-733dfa95-68a7-455e-b246-a4cf8d59cf33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66236345566471749325887820394147465946580520567473807988163691915162239691662 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.6623634556647174932588782039414746594658052056747380798816369191
5162239691662
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.12271519524578685260050110818980613744973297917304797537758444080287008902046
Short name T287
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.75 seconds
Started Nov 22 01:25:26 PM PST 23
Finished Nov 22 01:25:38 PM PST 23
Peak memory 201208 kb
Host smart-c5e522b2-71d8-4cba-bcea-eda9a5b1a0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12271519524578685260050110818980613744973297917304797537758444080287008902046 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.12271519524578685260050110818980613744973297917304797537758444080287008902046
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.88263939007883769233136302352262173127660899326770349474655110214531860882295
Short name T311
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 199296 kb
Host smart-00c9dbc6-e858-40a2-a1d8-71a3ab1237a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88263939007883769233136302352262173127660899326770349474655110214531860882295 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.88263939007883769233136302352262173127660899326770349474655110214531860882295
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.71855918414150974031787623987238321627967018885159969299972494357260794473896
Short name T370
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.86 seconds
Started Nov 22 01:25:54 PM PST 23
Finished Nov 22 01:26:04 PM PST 23
Peak memory 198724 kb
Host smart-08dead7d-33a6-4a26-a6fe-948814192c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71855918414150974031787623987238321627967018885159969299972494357260794473896 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.71855918414150974031787623987238321627967018885159969299972494357260794473896
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.99943521001818787040021356485825892082929735472309837749906704513377058035631
Short name T398
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:25:23 PM PST 23
Finished Nov 22 01:25:29 PM PST 23
Peak memory 201072 kb
Host smart-05792904-1734-4e5f-9a2e-b2013d584387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99943521001818787040021356485825892082929735472309837749906704513377058035631 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.99943521001818787040021356485825892082929735472309837749906704513377058035631
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.62491794251890097368892207081712837021882823347153315794480539747634102196223
Short name T388
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Nov 22 01:25:08 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 200940 kb
Host smart-e1613a2d-45ef-475d-a996-f88354f167bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62491794251890097368892207081712837021882823347153315794480539747634102196223 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_smoke.62491794251890097368892207081712837021882823347153315794480539747634102196223
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.40136626573448593466980870521435581318374785170871844784450602985657528079370
Short name T29
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.68 seconds
Started Nov 22 01:25:29 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201484 kb
Host smart-b7dc130f-fb2d-46d2-977b-458588bd6a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40136626573448593466980870521435581318374785170871844784450602985657528079370 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.40136626573448593466980870521435581318374785170871844784450602985657528079370
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.27179639143705069090607293938845951170667251632425030780930020893597115368262
Short name T616
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:25:34 PM PST 23
Finished Nov 22 01:25:47 PM PST 23
Peak memory 201200 kb
Host smart-3a7248c2-5f03-4d6a-a44e-5e344f1c7644
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179639143705069090607293938845951170667251632425030780930020893597115368262 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.271796391437050690906072939388459511706672516324250307809300
20893597115368262
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.46635664029606092351273664618891648177469822457799574828775484956585644842116
Short name T456
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.73 seconds
Started Nov 22 01:25:31 PM PST 23
Finished Nov 22 01:25:42 PM PST 23
Peak memory 201188 kb
Host smart-b1959f05-eb94-4662-8b17-f927f01c6312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46635664029606092351273664618891648177469822457799574828775484956585644842116 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.46635664029606092351273664618891648177469822457799574828775484956585644842116
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.109627820793531109951306141489824030577213162866256747478780957467596799006681
Short name T359
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Nov 22 01:25:19 PM PST 23
Finished Nov 22 01:25:26 PM PST 23
Peak memory 201260 kb
Host smart-0e75b30e-280f-4528-b379-d7362b1af909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109627820793531109951306141489824030577213162866256747478780957467596799006681 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.109627820793531109951306141489824030577213162866256747478780957467596799006681
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.57410273201020491597179081478791967360187329988633849501890127348866971915847
Short name T34
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.68 seconds
Started Nov 22 01:25:32 PM PST 23
Finished Nov 22 01:28:40 PM PST 23
Peak memory 201404 kb
Host smart-543e13cc-b526-43b6-93b4-2ac4aee6ddcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57410273201020491597179081478791967360187329988633849501890127348866971915847 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.57410273201020491597179081478791967360187329988633849501890127
348866971915847
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4485784382888963238917152853797540279963825379046038972138080760263400637005
Short name T376
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:25:46 PM PST 23
Peak memory 201216 kb
Host smart-232f15f9-8aca-4a69-9dc8-4e053e0dcde0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4485784382888963238917152853797540279963825379046038972138080760263400637005 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.4485784382888963238917152853797540279963825379046038972138080
760263400637005
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.71550722687015048813905533650517010402295124710430354693217644212321462542381
Short name T278
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Nov 22 01:25:19 PM PST 23
Finished Nov 22 01:25:26 PM PST 23
Peak memory 201164 kb
Host smart-80730954-12e9-475b-b858-57d879140f30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71550722687015048813905533650517010402295124710430354693217644212321462542381 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.7155072268701504881390553365051701040229512471043035469321764421
2321462542381
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.14126015372854856097509692349354932779596459887327555175562763893365176989469
Short name T512
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 22 01:25:12 PM PST 23
Finished Nov 22 01:25:17 PM PST 23
Peak memory 201216 kb
Host smart-b05b02e3-d8b9-4f77-8d4d-a661c9861606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14126015372854856097509692349354932779596459887327555175562763893365176989469 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.14126015372854856097509692349354932779596459887327555175562763893365176989469
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.37747954618048656766621014628692594799516268668052357382742395098504651598124
Short name T266
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 201100 kb
Host smart-643efee3-fd72-4a2a-aafe-927d27461001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37747954618048656766621014628692594799516268668052357382742395098504651598124 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.37747954618048656766621014628692594799516268668052357382742395098504651598124
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.11256914123929446508720392544103653354886814792160843475998040396444502834566
Short name T329
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:25:37 PM PST 23
Finished Nov 22 01:25:50 PM PST 23
Peak memory 201156 kb
Host smart-6486d9ae-0f70-4468-a645-d9ab5caba360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11256914123929446508720392544103653354886814792160843475998040396444502834566 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.11256914123929446508720392544103653354886814792160843475998040396444502834566
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1879274676377549588579908487410421924414415688954475542438778448347570510163
Short name T473
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Nov 22 01:25:16 PM PST 23
Finished Nov 22 01:25:22 PM PST 23
Peak memory 201096 kb
Host smart-68d8dd72-d2c8-4ad7-b645-ad77d14c659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879274676377549588579908487410421924414415688954475542438778448347570510163 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.1879274676377549588579908487410421924414415688954475542438778448347570510163
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.65873972078444413495872537572390016349166226408518673132340537249498076888708
Short name T432
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 22 01:25:31 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 201140 kb
Host smart-87945d74-7dd2-43b5-9a65-85140e4b18cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65873972078444413495872537572390016349166226408518673132340537249498076888708 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_smoke.65873972078444413495872537572390016349166226408518673132340537249498076888708
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.97551050243416826463700615046993965159813297982964161701765810068031477911837
Short name T21
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.19 seconds
Started Nov 22 01:25:34 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 201468 kb
Host smart-8a150221-4258-4772-b2c3-128f79c8c562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97551050243416826463700615046993965159813297982964161701765810068031477911837 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.97551050243416826463700615046993965159813297982964161701765810068031477911837
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.75378483182894952076622828731100817830450943145193490482557485010149461471403
Short name T575
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.94 seconds
Started Nov 22 01:25:22 PM PST 23
Finished Nov 22 01:25:29 PM PST 23
Peak memory 201020 kb
Host smart-bc021091-5aff-4d06-a14c-85aab86da654
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75378483182894952076622828731100817830450943145193490482557485010149461471403 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.753784831828949520766228287311008178304509431451934904825574
85010149461471403
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.6405985813899596658010716220844958426602499512706108702883556011751866256818
Short name T439
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Nov 22 01:25:31 PM PST 23
Finished Nov 22 01:25:42 PM PST 23
Peak memory 201032 kb
Host smart-23ac69f6-233d-4da5-868a-5980645fe109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6405985813899596658010716220844958426602499512706108702883556011751866256818 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.6405985813899596658010716220844958426602499512706108702883556011751866256818
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.6527043828531111346580226179686080880131149278866607833928128845137168382909
Short name T498
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:25:44 PM PST 23
Peak memory 201168 kb
Host smart-767717f0-fa5c-488f-b251-3c1d5dd11688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6527043828531111346580226179686080880131149278866607833928128845137168382909 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.6527043828531111346580226179686080880131149278866607833928128845137168382909
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.40914203604774771026466526550957025432383906622286776788717638786347469542156
Short name T520
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.36 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 201236 kb
Host smart-d9f1cb74-d225-4726-a4b1-492791f77470
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40914203604774771026466526550957025432383906622286776788717638786347469542156 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.40914203604774771026466526550957025432383906622286776788717638
786347469542156
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.108975670834549415839519549746600711963912618719021183519981377262084062786744
Short name T228
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:25:21 PM PST 23
Finished Nov 22 01:25:29 PM PST 23
Peak memory 201112 kb
Host smart-a762e437-818c-47a9-a313-c21da1a76410
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108975670834549415839519549746600711963912618719021183519981377262084062786744 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.10897567083454941583951954974660071196391261871902118351998
1377262084062786744
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.61263371223936996501738723540192034064861854428141583729389800101626787571015
Short name T24
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 22 01:25:22 PM PST 23
Finished Nov 22 01:25:29 PM PST 23
Peak memory 201072 kb
Host smart-0087099e-e574-45dd-a803-e9a0cc73f216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61263371223936996501738723540192034064861854428141583729389800101626787571015 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.6126337122393699650173872354019203406486185442814158372938980010
1626787571015
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.76710754046329362459810493733303521870336209961702275853740280928676790071822
Short name T414
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 201208 kb
Host smart-c7822908-0ee8-4a8f-9af7-0035877fc5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76710754046329362459810493733303521870336209961702275853740280928676790071822 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.76710754046329362459810493733303521870336209961702275853740280928676790071822
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.66572221612600986105605588739889634048555239221048764362612973202142719823620
Short name T420
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Nov 22 01:25:21 PM PST 23
Finished Nov 22 01:25:26 PM PST 23
Peak memory 201100 kb
Host smart-fbba53c1-d92f-4162-b22a-8d65d6d0cbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66572221612600986105605588739889634048555239221048764362612973202142719823620 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.66572221612600986105605588739889634048555239221048764362612973202142719823620
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.5579701609242425754324598283786146538923267391583684679787881823641481802608
Short name T330
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 22 01:25:35 PM PST 23
Finished Nov 22 01:25:47 PM PST 23
Peak memory 201060 kb
Host smart-056b385a-b923-409f-9d97-417900e87da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5579701609242425754324598283786146538923267391583684679787881823641481802608 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.5579701609242425754324598283786146538923267391583684679787881823641481802608
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.11027729331583630863775903830805968472729267329014773887823981475255403235497
Short name T244
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.64 seconds
Started Nov 22 01:25:21 PM PST 23
Finished Nov 22 01:25:27 PM PST 23
Peak memory 201180 kb
Host smart-cb67f27f-b664-4ddb-9be0-a1afd9f5c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11027729331583630863775903830805968472729267329014773887823981475255403235497 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.11027729331583630863775903830805968472729267329014773887823981475255403235497
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.49528087921854565695767826379312816766150140874668965752952710192428852634456
Short name T321
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Nov 22 01:25:48 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 201112 kb
Host smart-795109cf-ce30-43b2-b47b-09608a33818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49528087921854565695767826379312816766150140874668965752952710192428852634456 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_smoke.49528087921854565695767826379312816766150140874668965752952710192428852634456
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.80146127439534164773639867380854047216853547988228200386446065138536279189678
Short name T656
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.52 seconds
Started Nov 22 01:25:23 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 201452 kb
Host smart-3dd888dc-5b02-4227-90ed-1b68ac940a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80146127439534164773639867380854047216853547988228200386446065138536279189678 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.80146127439534164773639867380854047216853547988228200386446065138536279189678
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.89240846743475176365238750097383571949007325453666727826236539263482523646528
Short name T539
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 22 01:25:19 PM PST 23
Finished Nov 22 01:25:24 PM PST 23
Peak memory 201016 kb
Host smart-d550f9af-bb01-4360-b359-e2ca3e6de9fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89240846743475176365238750097383571949007325453666727826236539263482523646528 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.892408467434751763652387500973835719490073254536667278262365
39263482523646528
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.43263376598218432494889813353054565327229692152343398791002769517103708707126
Short name T529
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:25:42 PM PST 23
Peak memory 201160 kb
Host smart-287bee87-2fa3-44db-a204-dee10a331280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43263376598218432494889813353054565327229692152343398791002769517103708707126 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.43263376598218432494889813353054565327229692152343398791002769517103708707126
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.70524690901994058311547402931944679418699724275886184389894688476543068680108
Short name T436
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 22 01:25:34 PM PST 23
Finished Nov 22 01:25:48 PM PST 23
Peak memory 201236 kb
Host smart-3719b4bc-1de8-4577-8627-3b48344b9581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70524690901994058311547402931944679418699724275886184389894688476543068680108 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.70524690901994058311547402931944679418699724275886184389894688476543068680108
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1085301245318365008598542944413326293589295281497613154577795122430834559544
Short name T544
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.6 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:28:40 PM PST 23
Peak memory 201448 kb
Host smart-964f733d-620b-4382-a41f-e4c40e8eb6b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085301245318365008598542944413326293589295281497613154577795122430834559544 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.108530124531836500859854294441332629358929528149761315457779512
2430834559544
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.101960092246829892688682077970616336913833432581424080444086352095853733388669
Short name T581
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Nov 22 01:25:37 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 201268 kb
Host smart-ef80b261-f3ac-4484-bc6a-8c481939c52d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101960092246829892688682077970616336913833432581424080444086352095853733388669 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.10196009224682989268868207797061633691383343258142408044408
6352095853733388669
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.49991351467805827450738490607802793273950749526369523667632623891728571281888
Short name T661
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Nov 22 01:25:31 PM PST 23
Finished Nov 22 01:25:45 PM PST 23
Peak memory 201072 kb
Host smart-29f68388-3da6-425d-b33c-cb5291e4a222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49991351467805827450738490607802793273950749526369523667632623891728571281888 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.4999135146780582745073849060780279327395074952636952366763262389
1728571281888
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.63453389545541208558573527676478187607255828843218693403610834206404209414211
Short name T176
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 201188 kb
Host smart-1f467cab-2938-4ded-b15d-cf1067baac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63453389545541208558573527676478187607255828843218693403610834206404209414211 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.63453389545541208558573527676478187607255828843218693403610834206404209414211
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.88382700703949316062177528984464271145216372167022361624749872738968064347327
Short name T47
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 201084 kb
Host smart-ccd85810-2dbb-4648-81b2-1136b9daa1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88382700703949316062177528984464271145216372167022361624749872738968064347327 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.88382700703949316062177528984464271145216372167022361624749872738968064347327
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.25870847142546635490335190234854309980075923668269147083441244743061279036417
Short name T163
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.7 seconds
Started Nov 22 01:25:34 PM PST 23
Finished Nov 22 01:25:47 PM PST 23
Peak memory 200988 kb
Host smart-2a622dbe-d053-4690-bd09-46e8b894f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25870847142546635490335190234854309980075923668269147083441244743061279036417 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.25870847142546635490335190234854309980075923668269147083441244743061279036417
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.64395748842727993375156333217474168312985782489403149640319511900182369457235
Short name T247
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Nov 22 01:25:31 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 201172 kb
Host smart-57453d41-59ec-400c-a39e-6df9e9aa137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64395748842727993375156333217474168312985782489403149640319511900182369457235 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.64395748842727993375156333217474168312985782489403149640319511900182369457235
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.30242793246263392157901021474841802155580870970555620320251981269792365099397
Short name T120
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Nov 22 01:25:20 PM PST 23
Finished Nov 22 01:25:24 PM PST 23
Peak memory 201056 kb
Host smart-e273f5eb-f007-4805-8760-d91c52197e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30242793246263392157901021474841802155580870970555620320251981269792365099397 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_smoke.30242793246263392157901021474841802155580870970555620320251981269792365099397
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.26907335945644335509602327782695764747700457718141271066469315337926445493792
Short name T170
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.84 seconds
Started Nov 22 01:25:24 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 201356 kb
Host smart-81819348-97ee-4c37-9235-3812ac3277cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907335945644335509602327782695764747700457718141271066469315337926445493792 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.26907335945644335509602327782695764747700457718141271066469315337926445493792
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4791090851744489771194404929604190545574944284515932740079745931205021728289
Short name T590
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:25:29 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 201072 kb
Host smart-f4c823d5-29ab-4510-ae4b-533b94d31fc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4791090851744489771194404929604190545574944284515932740079745931205021728289 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.4791090851744489771194404929604190545574944284515932740079745
931205021728289
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.45348837849436756529258835173766837754945784199372838134032590671758549571824
Short name T339
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:01 PM PST 23
Peak memory 201100 kb
Host smart-a822c1ee-dbde-42c3-9764-72dc4c043d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45348837849436756529258835173766837754945784199372838134032590671758549571824 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.45348837849436756529258835173766837754945784199372838134032590671758549571824
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.63191782568194142743070362300823973945210437910063364148826165876942291242980
Short name T405
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 201276 kb
Host smart-6c36bf03-33ae-4bc7-aa71-4aac0a0e1590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63191782568194142743070362300823973945210437910063364148826165876942291242980 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.63191782568194142743070362300823973945210437910063364148826165876942291242980
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.93436870180741454211065702108746394482870429988866461662844555922100715386785
Short name T550
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.76 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:28:56 PM PST 23
Peak memory 201456 kb
Host smart-4cc81519-c17f-4b45-92ca-8744c9b92498
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93436870180741454211065702108746394482870429988866461662844555922100715386785 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.93436870180741454211065702108746394482870429988866461662844555
922100715386785
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.58764884307446221261237705097762409249597056274031077866009485853957628692213
Short name T253
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Nov 22 01:25:48 PM PST 23
Finished Nov 22 01:26:00 PM PST 23
Peak memory 201204 kb
Host smart-a3086541-24ce-4839-b800-ddc48ce3bb49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58764884307446221261237705097762409249597056274031077866009485853957628692213 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.587648843074462212612377050977624092495970562740310778660094
85853957628692213
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.39621001045403158593815692800293868625974993913202737445016282584608351978901
Short name T418
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:22 PM PST 23
Peak memory 201196 kb
Host smart-7881dd04-00b6-4625-959c-f6a4328b4eee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39621001045403158593815692800293868625974993913202737445016282584608351978901 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.3962100104540315859381569280029386862597499391320273744501628258
4608351978901
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.93866114048564411068104586002296594032700821267210583752258399085756549425184
Short name T245
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 201132 kb
Host smart-85390864-3579-411a-a654-4ce9fb7b12e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93866114048564411068104586002296594032700821267210583752258399085756549425184 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.93866114048564411068104586002296594032700821267210583752258399085756549425184
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.74133183634266708341120670603358561812023048971766906077425391449344038470565
Short name T612
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.94 seconds
Started Nov 22 01:25:29 PM PST 23
Finished Nov 22 01:25:44 PM PST 23
Peak memory 201232 kb
Host smart-b5215c13-8b98-4220-bd14-99bb1fa21b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74133183634266708341120670603358561812023048971766906077425391449344038470565 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.74133183634266708341120670603358561812023048971766906077425391449344038470565
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.32947027115834003012752650201453595230315843837239647093627170026259429694164
Short name T625
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 201100 kb
Host smart-ab0a47fb-31b4-4efb-b557-3b6420b9d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32947027115834003012752650201453595230315843837239647093627170026259429694164 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.32947027115834003012752650201453595230315843837239647093627170026259429694164
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.58604739635374791051987698718765723040409992758926793059986523327282428302454
Short name T641
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 201168 kb
Host smart-1719bf81-cf38-4ec7-aa91-61e15ed7fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58604739635374791051987698718765723040409992758926793059986523327282428302454 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.58604739635374791051987698718765723040409992758926793059986523327282428302454
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.48054839799905474150385252570419205406035659684561985609066093717148556406584
Short name T264
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 200956 kb
Host smart-4c03a991-4719-4dd2-a459-120780eee1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48054839799905474150385252570419205406035659684561985609066093717148556406584 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_smoke.48054839799905474150385252570419205406035659684561985609066093717148556406584
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.104838466316459968868213590625762072148766222417976004865705397931038477729396
Short name T274
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.72 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 201272 kb
Host smart-06131304-f917-49cd-a85c-ef1f43b4728a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104838466316459968868213590625762072148766222417976004865705397931038477729396 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.104838466316459968868213590625762072148766222417976004865705397931038477729396
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.26541273115334521702607939735847744856664472747509187192070552373631387766566
Short name T443
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 201024 kb
Host smart-856bd36d-8852-4b58-9839-0fb1ec7c727b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26541273115334521702607939735847744856664472747509187192070552373631387766566 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.265412731153345217026079397358477448566644727475091871920705
52373631387766566
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.58582714898917477358124415504508057345217758097734806313832811698272182493033
Short name T144
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:25:36 PM PST 23
Finished Nov 22 01:25:50 PM PST 23
Peak memory 201104 kb
Host smart-467264f8-1522-408e-8ad3-13e6fc1ae9aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58582714898917477358124415504508057345217758097734806313832811698272182493033 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.58582714898917477358124415504508057345217758097734806313832811698272182493033
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.17152532656198108932178118036960312300704766790877025620148362524553038625267
Short name T390
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 201272 kb
Host smart-8612b00d-78c5-427b-8436-8419ab419f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17152532656198108932178118036960312300704766790877025620148362524553038625267 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.17152532656198108932178118036960312300704766790877025620148362524553038625267
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.88767846026454054069123089683937816401053121935726184331598575431277175103422
Short name T360
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.22 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:29:13 PM PST 23
Peak memory 201432 kb
Host smart-d9690b96-31f0-48cd-8dd4-58344ca54a40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88767846026454054069123089683937816401053121935726184331598575431277175103422 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.88767846026454054069123089683937816401053121935726184331598575
431277175103422
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.73489063289709184230999574440263524920416196609657263117747547945532223698148
Short name T518
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 201220 kb
Host smart-c14e79fb-90fd-49a6-84ba-94bfdbca9bdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73489063289709184230999574440263524920416196609657263117747547945532223698148 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.734890632897091842309995744402635249204161966096572631177475
47945532223698148
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.5902237369616994959138414980455508682310837492020571064327528172979262433116
Short name T118
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Nov 22 01:26:11 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 201212 kb
Host smart-3701b589-d699-461c-ba83-6ea2ed0e4bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5902237369616994959138414980455508682310837492020571064327528172979262433116 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.5902237369616994959138414980455508682310837492020571064327528172979262433116
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.66180758241864397605579741589129853491539059398113433565236076007079203957684
Short name T355
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 201136 kb
Host smart-11d33db7-18f1-4a03-a81e-7c699272b3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66180758241864397605579741589129853491539059398113433565236076007079203957684 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.66180758241864397605579741589129853491539059398113433565236076007079203957684
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.101985454908693877623820566832325587042982948085367843163516952053269643973139
Short name T507
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 201224 kb
Host smart-69f017cd-7aa1-4e60-a87d-1a378ce2001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101985454908693877623820566832325587042982948085367843163516952053269643973139 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.101985454908693877623820566832325587042982948085367843163516952053269643973139
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.108050769127198865827002189897913895668504363065238788193136758515613633644236
Short name T143
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 201036 kb
Host smart-7af206b4-ffbd-4788-b073-03519d59b395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108050769127198865827002189897913895668504363065238788193136758515613633644236 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.108050769127198865827002189897913895668504363065238788193136758515613633644236
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.63671546182682806668016728779409321727967692136463468361529100624124237197847
Short name T162
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 201164 kb
Host smart-49b220a9-2f10-4a66-a3a7-8fa52b7987ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63671546182682806668016728779409321727967692136463468361529100624124237197847 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.63671546182682806668016728779409321727967692136463468361529100624124237197847
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.20255770119065704811305828608227531218033943579671298458094173812980184644756
Short name T356
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 201100 kb
Host smart-16f180b1-736c-418e-a005-f8bfece1a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20255770119065704811305828608227531218033943579671298458094173812980184644756 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_smoke.20255770119065704811305828608227531218033943579671298458094173812980184644756
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.48913111450921381057704128491687090740141669253543453383564278476047875945480
Short name T309
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.32 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:28:21 PM PST 23
Peak memory 201484 kb
Host smart-815dc7ff-1130-4b19-8b33-dee54e1696d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48913111450921381057704128491687090740141669253543453383564278476047875945480 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.48913111450921381057704128491687090740141669253543453383564278476047875945480
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.78613393729348767473683772476116387137633265937923021112058414082562508408748
Short name T43
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.82 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 201008 kb
Host smart-a4f17a90-ce34-4bff-ba3f-f737582969bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78613393729348767473683772476116387137633265937923021112058414082562508408748 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.786133937293487674736837724761163871376332659379230211120584
14082562508408748
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.59494013193230934563733931160052444112315202654379909740778829302224406078917
Short name T514
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:25:31 PM PST 23
Finished Nov 22 01:25:42 PM PST 23
Peak memory 201092 kb
Host smart-44344a79-eff5-4a11-9752-d5ed07372984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59494013193230934563733931160052444112315202654379909740778829302224406078917 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.59494013193230934563733931160052444112315202654379909740778829302224406078917
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3105991741197347385314741042534426176036385671833941665005279618169186072010
Short name T540
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 22 01:25:34 PM PST 23
Finished Nov 22 01:25:48 PM PST 23
Peak memory 201280 kb
Host smart-4fb8caf3-8a98-484f-a8aa-8c6157b47492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105991741197347385314741042534426176036385671833941665005279618169186072010 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3105991741197347385314741042534426176036385671833941665005279618169186072010
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.56557834069963750745290981116830315473021574897533798296658656776442655584426
Short name T216
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.43 seconds
Started Nov 22 01:25:35 PM PST 23
Finished Nov 22 01:28:47 PM PST 23
Peak memory 201388 kb
Host smart-59f0ff93-09dc-47b0-afae-0bce7a7e96ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56557834069963750745290981116830315473021574897533798296658656776442655584426 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.56557834069963750745290981116830315473021574897533798296658656
776442655584426
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.70223479035909625481429371875481666310705461778008772813507229852567853262988
Short name T494
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:26:00 PM PST 23
Peak memory 201204 kb
Host smart-ded45c4a-b972-47b1-a9da-61c86e9f8944
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70223479035909625481429371875481666310705461778008772813507229852567853262988 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.702234790359096254814293718754816663107054617780087728135072
29852567853262988
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.62980061282244199943135919982974022888032405409840405374043960483695095014975
Short name T346
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 22 01:25:45 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 201244 kb
Host smart-c94fa025-f703-4ab6-9796-c6d93a884946
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62980061282244199943135919982974022888032405409840405374043960483695095014975 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.6298006128224419994313591998297402288803240540984040537404396048
3695095014975
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.53608150284288323447692545952293919748125892711984354804074844069874210188045
Short name T489
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 201192 kb
Host smart-e0a5b704-0661-4c54-8f4d-78e834581f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53608150284288323447692545952293919748125892711984354804074844069874210188045 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.53608150284288323447692545952293919748125892711984354804074844069874210188045
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.113280665966727475742921476158796368246364484243953770658800733753608038825452
Short name T173
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Nov 22 01:25:59 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 201252 kb
Host smart-2393e848-2845-430b-8fc8-98d6ff9029f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113280665966727475742921476158796368246364484243953770658800733753608038825452 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.113280665966727475742921476158796368246364484243953770658800733753608038825452
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.60297149531538473484918858969506159651568462130300812343491138064770042976983
Short name T276
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 201080 kb
Host smart-e3555075-7696-47fe-a6b6-a901814d8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60297149531538473484918858969506159651568462130300812343491138064770042976983 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.60297149531538473484918858969506159651568462130300812343491138064770042976983
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.7592969421268172684599081771185231415816862665718684017969832646383896620401
Short name T299
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Nov 22 01:25:32 PM PST 23
Finished Nov 22 01:25:43 PM PST 23
Peak memory 201048 kb
Host smart-22fefcff-b317-4922-a3c6-2ed320807e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7592969421268172684599081771185231415816862665718684017969832646383896620401 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.7592969421268172684599081771185231415816862665718684017969832646383896620401
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3834333743940824159530310208371342255987755475834527838799202352507082598471
Short name T649
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Nov 22 01:25:35 PM PST 23
Finished Nov 22 01:25:50 PM PST 23
Peak memory 200980 kb
Host smart-f0f85954-e28d-4fca-a0b1-8b7dd9c250ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834333743940824159530310208371342255987755475834527838799202352507082598471 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sysrst_ctrl_smoke.3834333743940824159530310208371342255987755475834527838799202352507082598471
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.109671270775519350782141034263176513751261995885893713323836849261580885765974
Short name T471
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.01 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:28:23 PM PST 23
Peak memory 201476 kb
Host smart-142586a9-fc53-4639-95ac-bd445a6482d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109671270775519350782141034263176513751261995885893713323836849261580885765974 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.109671270775519350782141034263176513751261995885893713323836849261580885765974
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.35045857926831877263337272792596463036694446383147953928413170580334411902184
Short name T36
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 201196 kb
Host smart-4d07c231-8799-46e3-9fb2-b62cddcc256f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045857926831877263337272792596463036694446383147953928413170580334411902184 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.350458579268318772633372727925964630366944463831479539284131
70580334411902184
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.103473641078987097989953392042753005001891502069095280464440785950325305892270
Short name T595
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201224 kb
Host smart-11cf7225-c480-437e-85fd-27e8ea6efc3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103473641078987097989953392042753005001891502069095280464440785950325305892270 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.103473641078987097989953392042753005001891502069095280464440785950325305892270
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.114761684780798564050258356470716330826002394876750064320213909533051067536735
Short name T593
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 22 01:23:57 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 201220 kb
Host smart-2b8dd307-be49-4d0d-9adf-cdd829b80436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114761684780798564050258356470716330826002394876750064320213909533051067536735 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.114761684780798564050258356470716330826002394876750064320213909533051067536735
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.39337176905109183583249149441192930539673533931744439776156541798508708298272
Short name T397
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.17 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 201432 kb
Host smart-2ea3bec5-c5fe-409b-a766-a89f1ad94c71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39337176905109183583249149441192930539673533931744439776156541798508708298272 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.393371769051091835832491494411929305396735339317444397761565417
98508708298272
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.33065522390763772272799013137848395164237888906308251009064104187432080580472
Short name T328
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201056 kb
Host smart-71ebb8a6-2322-44ae-9e79-74c8a4df2dc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33065522390763772272799013137848395164237888906308251009064104187432080580472 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.3306552239076377227279901313784839516423788890630825100906410
4187432080580472
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.31364013077553123852521234128828378595866280179574248162200745523852511377470
Short name T121
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.58 seconds
Started Nov 22 01:24:18 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 201144 kb
Host smart-fd40b119-37bc-4bc9-af92-2490e014ea0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31364013077553123852521234128828378595866280179574248162200745523852511377470 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.31364013077553123852521234128828378595866280179574248162200745523852511377470
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.65378077824412920822642018888558390870883439170246410373026054006982592995782
Short name T493
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Nov 22 01:23:52 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 201032 kb
Host smart-59f06a59-b841-4fcb-b227-73df618da6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65378077824412920822642018888558390870883439170246410373026054006982592995782 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.65378077824412920822642018888558390870883439170246410373026054006982592995782
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.41491756747923873498491453206688598322601198051507452899247882434014866542476
Short name T249
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201220 kb
Host smart-116c2867-1170-48f3-8de3-a95d62d4c24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41491756747923873498491453206688598322601198051507452899247882434014866542476 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.41491756747923873498491453206688598322601198051507452899247882434014866542476
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.85337183160707060786502758843672541167789889635685254212412361757103964833913
Short name T296
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 201172 kb
Host smart-69b99363-3ff0-4cc8-9422-ea53f9aa641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85337183160707060786502758843672541167789889635685254212412361757103964833913 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.85337183160707060786502758843672541167789889635685254212412361757103964833913
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.48430032896804329783013290799298931832580639867048740502394771184841384599058
Short name T430
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:23:47 PM PST 23
Finished Nov 22 01:24:00 PM PST 23
Peak memory 201184 kb
Host smart-5f38098c-fca6-4acd-9b6f-516415ebe2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48430032896804329783013290799298931832580639867048740502394771184841384599058 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.48430032896804329783013290799298931832580639867048740502394771184841384599058
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.91409113391456218939214887067250198210351148096379608191810280022488379496777
Short name T96
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Nov 22 01:24:14 PM PST 23
Finished Nov 22 01:24:22 PM PST 23
Peak memory 200716 kb
Host smart-fb83422f-e694-4115-bf53-e9be505c66f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91409113391456218939214887067250198210351148096379608191810280022488379496777 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_smoke.91409113391456218939214887067250198210351148096379608191810280022488379496777
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.13466668293924552251075433401165803614398177090614279821155535581902265220062
Short name T343
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.91 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 201368 kb
Host smart-212b8452-53d5-4123-91d9-81078900ffaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13466668293924552251075433401165803614398177090614279821155535581902265220062 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.13466668293924552251075433401165803614398177090614279821155535581902265220062
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.55855184079307756397383116574677132593461820553796728186894382568711297150340
Short name T270
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:23:45 PM PST 23
Peak memory 201084 kb
Host smart-a8864d0f-b607-47b2-9126-a701fff19287
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55855184079307756397383116574677132593461820553796728186894382568711297150340 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.5585518407930775639738311657467713259346182055379672818689438
2568711297150340
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.53279968516591870724152309693670205096096862396961775291200927657036608472826
Short name T607
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 201204 kb
Host smart-ae7d656d-f875-46a0-8e95-7a5ab29af668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53279968516591870724152309693670205096096862396961775291200927657036608472826 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.53279968516591870724152309693670205096096862396961775291200927657036608472826
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.55243579378039336958124185590154282722191990717366139250554868875438629135698
Short name T454
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 201096 kb
Host smart-3280ea2c-e7c7-45ed-bfd4-b52c8ddfcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55243579378039336958124185590154282722191990717366139250554868875438629135698 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.55243579378039336958124185590154282722191990717366139250554868875438629135698
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.109234242668832565256876022251352994244117701567274568292879578834095382794055
Short name T533
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.12 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 201416 kb
Host smart-75ac1820-0793-4474-9561-b37df36ad122
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109234242668832565256876022251352994244117701567274568292879578834095382794055 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.10923424266883256525687602225135299424411770156727456829287957
8834095382794055
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.63632283801516925810612599282571160042773427720473605057557786789507526292472
Short name T610
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 201132 kb
Host smart-b1b616dd-a803-40e6-a729-596c2d9ec0f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63632283801516925810612599282571160042773427720473605057557786789507526292472 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.6363228380151692581061259928257116004277342772047360505755778
6789507526292472
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.8043586020876120346304464109521346423644606206078361784583112602732438302984
Short name T427
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Nov 22 01:23:36 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201072 kb
Host smart-5cfdbce4-17db-4753-b270-23bb02ebac00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8043586020876120346304464109521346423644606206078361784583112602732438302984 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.8043586020876120346304464109521346423644606206078361784583112602732438302984
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.92278649690460525193834606355064926729873347493018440830955615503175193022122
Short name T404
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Nov 22 01:23:34 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201160 kb
Host smart-a87292f1-e241-47d1-a556-e3e352f755db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92278649690460525193834606355064926729873347493018440830955615503175193022122 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.92278649690460525193834606355064926729873347493018440830955615503175193022122
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.58722530409382438667782606939541995320831726311887350487401437081946530200457
Short name T431
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:24:44 PM PST 23
Peak memory 201224 kb
Host smart-1c32df34-9ca4-46d4-be1b-cc8ea261d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58722530409382438667782606939541995320831726311887350487401437081946530200457 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.58722530409382438667782606939541995320831726311887350487401437081946530200457
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.91664882407472264910712893237006199540325540967771265679505767797617842357190
Short name T413
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:23:36 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 201176 kb
Host smart-6da966f5-676d-49b9-a129-a8060b875cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91664882407472264910712893237006199540325540967771265679505767797617842357190 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.91664882407472264910712893237006199540325540967771265679505767797617842357190
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.17546365205563020502843038775718093728956566393900803323849852795741461147485
Short name T285
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 01:23:39 PM PST 23
Peak memory 201216 kb
Host smart-edadb9aa-3472-4c83-9caf-7e221f3688e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17546365205563020502843038775718093728956566393900803323849852795741461147485 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.17546365205563020502843038775718093728956566393900803323849852795741461147485
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.5741046261789485177711293772482683177261951690072648476005597554590708985930
Short name T576
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Nov 22 01:23:33 PM PST 23
Finished Nov 22 01:23:50 PM PST 23
Peak memory 201148 kb
Host smart-5838ea9a-50ae-45bf-a86b-a9bb8787dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5741046261789485177711293772482683177261951690072648476005597554590708985930 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sysrst_ctrl_smoke.5741046261789485177711293772482683177261951690072648476005597554590708985930
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.44764666826593974675597510934512948640599785901052713218123313994320682385959
Short name T605
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.6 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 201476 kb
Host smart-f106bbb5-9d17-4307-befe-a8b9850bfe50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44764666826593974675597510934512948640599785901052713218123313994320682385959 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.44764666826593974675597510934512948640599785901052713218123313994320682385959
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.12477065321977873791262736167196833062594901052730424215322649446666421871311
Short name T326
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201192 kb
Host smart-367d08dc-39e0-4b15-83f0-42a35a1de16b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12477065321977873791262736167196833062594901052730424215322649446666421871311 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.1247706532197787379126273616719683306259490105273042421532264
9446666421871311
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.78436405706998547686034736047755474778305559427214723939014185521814588176632
Short name T444
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.6 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 200296 kb
Host smart-5c1cbb94-7ac2-4357-b351-1594c50e441c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78436405706998547686034736047755474778305559427214723939014185521814588176632 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.78436405706998547686034736047755474778305559427214723939014185521814588176632
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.15939678094432930987564591051977285272293383348671614729362501885947770479832
Short name T399
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 22 01:24:16 PM PST 23
Finished Nov 22 01:24:25 PM PST 23
Peak memory 201088 kb
Host smart-82db7686-4cf8-42ad-8977-7b30f8727d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15939678094432930987564591051977285272293383348671614729362501885947770479832 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.15939678094432930987564591051977285272293383348671614729362501885947770479832
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.56579222742053200241681946421446323613427465273935911556892407558188591829379
Short name T662
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.21 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:26:54 PM PST 23
Peak memory 201324 kb
Host smart-796f9f5b-c718-462e-9555-23d5e8d18505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56579222742053200241681946421446323613427465273935911556892407558188591829379 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.565792227420532002416819464214463236134274652739359115568924075
58188591829379
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.78827233887982534875847356876342151517572242278306548603382368114265123646324
Short name T347
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Nov 22 01:24:06 PM PST 23
Finished Nov 22 01:24:20 PM PST 23
Peak memory 201244 kb
Host smart-04db2a36-c75e-40f9-aed1-43d1695b2532
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78827233887982534875847356876342151517572242278306548603382368114265123646324 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.7882723388798253487584735687634215151757224227830654860338236
8114265123646324
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.39319017478040220875066508632986716426229721713065979215417212435463838030307
Short name T267
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:23:58 PM PST 23
Peak memory 201192 kb
Host smart-767654d2-ab86-41e0-adec-c709d8466ae8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39319017478040220875066508632986716426229721713065979215417212435463838030307 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.39319017478040220875066508632986716426229721713065979215417212435463838030307
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.33718879918992045151042661274219205225237417164116435908527650454873098213819
Short name T106
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201056 kb
Host smart-8eac1307-9078-4572-8daa-c756b2f4e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33718879918992045151042661274219205225237417164116435908527650454873098213819 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.33718879918992045151042661274219205225237417164116435908527650454873098213819
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.64877059450883518853986396576738647156702716679403571445104395957588970830773
Short name T269
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Nov 22 01:24:28 PM PST 23
Finished Nov 22 01:24:34 PM PST 23
Peak memory 201212 kb
Host smart-3053bd05-a612-4cc3-a22b-fbcf3d9e8d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64877059450883518853986396576738647156702716679403571445104395957588970830773 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.64877059450883518853986396576738647156702716679403571445104395957588970830773
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.62754167972358514022261820980618923207372094188010528450485281888013864162282
Short name T93
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 22 01:23:35 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 201236 kb
Host smart-5363841e-ee88-4878-bc2a-a5e919e6fce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62754167972358514022261820980618923207372094188010528450485281888013864162282 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.62754167972358514022261820980618923207372094188010528450485281888013864162282
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2800480394448615469086058354445490752805171467061549936704283348708840195879
Short name T209
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 200632 kb
Host smart-980ba2f6-5af5-4897-9960-c05dce5c991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800480394448615469086058354445490752805171467061549936704283348708840195879 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2800480394448615469086058354445490752805171467061549936704283348708840195879
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.6384762300625099376241960941562025299894465001587838121319354563682971743529
Short name T479
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201124 kb
Host smart-3a4b5778-4879-4501-9c9d-4551e3d620b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6384762300625099376241960941562025299894465001587838121319354563682971743529 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sysrst_ctrl_smoke.6384762300625099376241960941562025299894465001587838121319354563682971743529
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.20404767518250641067530821703473839967273061179725092483087668549081890236432
Short name T598
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.01 seconds
Started Nov 22 01:24:02 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 201512 kb
Host smart-41709535-1a84-40d1-a93d-cdd74e76b436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404767518250641067530821703473839967273061179725092483087668549081890236432 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.20404767518250641067530821703473839967273061179725092483087668549081890236432
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.42137864938584794799629867113248198957817621600090804091068988199774199864887
Short name T19
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:24:43 PM PST 23
Peak memory 201152 kb
Host smart-6bd57a05-236e-4332-81e1-87be0a770701
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137864938584794799629867113248198957817621600090804091068988199774199864887 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.4213786493858479479962986711324819895781762160009080409106898
8199774199864887
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.33375664918139655964933527688231377001548629713329630982391575696499039302187
Short name T257
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201192 kb
Host smart-504a0893-a094-4fb1-a88d-7036d145b955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375664918139655964933527688231377001548629713329630982391575696499039302187 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.33375664918139655964933527688231377001548629713329630982391575696499039302187
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.15027066053141436022123766765751810041092567838610212090397925262169037279677
Short name T87
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201128 kb
Host smart-b3da1c54-2f18-499f-ba0e-12c717f66f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15027066053141436022123766765751810041092567838610212090397925262169037279677 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.15027066053141436022123766765751810041092567838610212090397925262169037279677
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.36955568271229063668695457473226328994234847817522963372739664995639685728375
Short name T613
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.64 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 201444 kb
Host smart-8d10cb49-4c75-412b-8f6f-eb076b8f7773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955568271229063668695457473226328994234847817522963372739664995639685728375 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.369555682712290636686954574732263289942348478175229633727396649
95639685728375
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.42396748397597911688192241130122483509747204172827565352115670894253592960852
Short name T229
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.47 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:23:58 PM PST 23
Peak memory 201112 kb
Host smart-5f798d27-7274-443d-8743-f64e3b4ede11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42396748397597911688192241130122483509747204172827565352115670894253592960852 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.4239674839759791168819224113012248350974720417282756535211567
0894253592960852
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.80683851110409687413156045728428932215449502567683927116832334526034737413355
Short name T525
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201112 kb
Host smart-9030143e-4c3f-401b-a5cc-11422e8fe95f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80683851110409687413156045728428932215449502567683927116832334526034737413355 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.80683851110409687413156045728428932215449502567683927116832334526034737413355
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.89463976641910350305369858756549300367653611103397228067680310270596928566766
Short name T161
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.76 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201216 kb
Host smart-9fbf93ac-9fed-4160-a4f7-dfc2ea28664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89463976641910350305369858756549300367653611103397228067680310270596928566766 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.89463976641910350305369858756549300367653611103397228067680310270596928566766
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.61791214856070486574774679826832377903844658132173159345757210884188533005800
Short name T422
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Nov 22 01:23:55 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201228 kb
Host smart-b936d0ae-ad67-44df-8b0c-46eeff1feedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61791214856070486574774679826832377903844658132173159345757210884188533005800 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.61791214856070486574774679826832377903844658132173159345757210884188533005800
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.14061332554750755862797458991627406405100957010270015800306239249226457942996
Short name T190
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:01 PM PST 23
Peak memory 201160 kb
Host smart-34bdc846-a9c2-448f-a854-2de3ca71fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14061332554750755862797458991627406405100957010270015800306239249226457942996 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.14061332554750755862797458991627406405100957010270015800306239249226457942996
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.109846851922331873747436138851635289979258588206370255120056450635079651165170
Short name T178
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Nov 22 01:24:02 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 201216 kb
Host smart-4815656c-738f-450a-a654-7f61c9949b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109846851922331873747436138851635289979258588206370255120056450635079651165170 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.109846851922331873747436138851635289979258588206370255120056450635079651165170
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.42540233461057805355183669743327173827373851628824898205418140090388527204443
Short name T363
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 198568 kb
Host smart-9c95874f-6776-48fa-9495-051f29fdfe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42540233461057805355183669743327173827373851628824898205418140090388527204443 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_smoke.42540233461057805355183669743327173827373851628824898205418140090388527204443
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.90790212374897656640686710888796377800137698522931515708845686646416562305858
Short name T461
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.62 seconds
Started Nov 22 01:24:03 PM PST 23
Finished Nov 22 01:26:28 PM PST 23
Peak memory 201448 kb
Host smart-ce42a139-b1f5-4f6c-ae4d-e4fdd77335a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90790212374897656640686710888796377800137698522931515708845686646416562305858 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.90790212374897656640686710888796377800137698522931515708845686646416562305858
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.21179228892288200061896315496546238583582163209719260226932751775093053668020
Short name T486
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 22 01:24:03 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 201164 kb
Host smart-6df88d39-a71a-41a4-b8fa-e1cbc5c975f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179228892288200061896315496546238583582163209719260226932751775093053668020 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.2117922889228820006189631549654623858358216320971926022693275
1775093053668020
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.24900377675669583007325199402788870917021054429949284000294392302037079998557
Short name T531
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 201216 kb
Host smart-26311a47-9015-4516-ae22-9e61545bc383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900377675669583007325199402788870917021054429949284000294392302037079998557 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.24900377675669583007325199402788870917021054429949284000294392302037079998557
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.104197695987009516539714050662523839603143166220522573892026529659104035545506
Short name T83
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:23:57 PM PST 23
Peak memory 201240 kb
Host smart-1cca738d-1f49-4206-b026-62e84043c19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104197695987009516539714050662523839603143166220522573892026529659104035545506 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.104197695987009516539714050662523839603143166220522573892026529659104035545506
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.24305587144096442191784965890445763866511701204575396844381232518718713299331
Short name T304
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.57 seconds
Started Nov 22 01:24:00 PM PST 23
Finished Nov 22 01:27:07 PM PST 23
Peak memory 201316 kb
Host smart-8a3fcbe8-0e9f-4ac6-8c51-cc82d4d4e2c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305587144096442191784965890445763866511701204575396844381232518718713299331 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.243055871440964421917849658904457638665117012045753968443812325
18718713299331
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.7436515698746348999461870910607727903205444137775920009974537703139606424522
Short name T188
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 22 01:24:15 PM PST 23
Finished Nov 22 01:24:26 PM PST 23
Peak memory 201220 kb
Host smart-d618adef-fd02-425f-b5a5-e4bb801b8959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7436515698746348999461870910607727903205444137775920009974537703139606424522 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.74365156987463489994618709106077279032054441377759200099745377
03139606424522
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.69667161933493097941657332662923973790171719661560118223511945775731807160043
Short name T241
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.2 seconds
Started Nov 22 01:23:45 PM PST 23
Finished Nov 22 01:23:59 PM PST 23
Peak memory 201192 kb
Host smart-bd2af05c-12df-4f38-a912-f3ca38c8fc15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69667161933493097941657332662923973790171719661560118223511945775731807160043 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.69667161933493097941657332662923973790171719661560118223511945775731807160043
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.55304227221217291644626861303725068143764361721572917764188537672464249740720
Short name T148
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 201172 kb
Host smart-eaa06a7a-1868-45f9-91bb-73356c08e412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55304227221217291644626861303725068143764361721572917764188537672464249740720 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.55304227221217291644626861303725068143764361721572917764188537672464249740720
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.65615155537151667879572276089538961154437197318283924349272617862333428445145
Short name T505
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 199068 kb
Host smart-a91f676f-2b8d-44df-a481-a26f1ba1ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65615155537151667879572276089538961154437197318283924349272617862333428445145 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.65615155537151667879572276089538961154437197318283924349272617862333428445145
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.18979352936694390936453859534851292660684173841501170970518287196465421876162
Short name T291
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 201172 kb
Host smart-c4300f20-b3b8-49df-8859-6d9f162b0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18979352936694390936453859534851292660684173841501170970518287196465421876162 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.18979352936694390936453859534851292660684173841501170970518287196465421876162
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.7648997816593967468735553790122504264416632602180667289939725294568007164772
Short name T513
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.71 seconds
Started Nov 22 01:23:42 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 201148 kb
Host smart-cb50fd7b-7952-4996-9ab4-3f7bd5311d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7648997816593967468735553790122504264416632602180667289939725294568007164772 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.7648997816593967468735553790122504264416632602180667289939725294568007164772
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.72396052455785099426090533291921243414938468932009059851025025803467364361223
Short name T621
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 22 01:23:58 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 201148 kb
Host smart-01680069-cb19-41e6-9a8f-0dab871fbbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72396052455785099426090533291921243414938468932009059851025025803467364361223 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_smoke.72396052455785099426090533291921243414938468932009059851025025803467364361223
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.110236958106658381199993930738915618741785661053108707313250837572557643086377
Short name T318
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.76 seconds
Started Nov 22 01:24:13 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 201424 kb
Host smart-fd2a8a11-4289-4ea7-90ec-de2fefe74a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110236958106658381199993930738915618741785661053108707313250837572557643086377 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.110236958106658381199993930738915618741785661053108707313250837572557643086377
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.56127964375337824254634798745909746418116163876084768803858946831339094590289
Short name T338
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Nov 22 01:24:37 PM PST 23
Finished Nov 22 01:24:44 PM PST 23
Peak memory 201212 kb
Host smart-a05ae701-da4f-4d68-849f-13bb7005bf44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56127964375337824254634798745909746418116163876084768803858946831339094590289 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.5612796437533782425463479874590974641811616387608476880385894
6831339094590289
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%