SYSRST_CTRL Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.950s 2.117ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 5.130s 2.470ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.430s 2.399ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.610s 2.535ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 10.160s 6.031ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.110s 2.075ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.880m 41.048ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 8.910s 2.891ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.260s 2.142ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.110s 2.075ms 20 20 100.00
sysrst_ctrl_csr_aliasing 8.910s 2.891ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 3.087m 118.289ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.298m 49.085ms 0 100 0.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 5.590s 3.139ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 6.580s 4.089ms 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 4.850s 2.515ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.190s 2.075ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 7.750s 4.425ms 50 50 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 4.890s 2.620ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.970s 5.189ms 50 50 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.001m 38.606ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 2.302m 87.229ms 50 50 100.00
V2 alert_test sysrst_ctrl_alert_test 3.790s 2.015ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 3.790s 2.023ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.020s 2.187ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.020s 2.187ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 10.160s 6.031ms 5 5 100.00
sysrst_ctrl_csr_rw 4.110s 2.075ms 20 20 100.00
sysrst_ctrl_csr_aliasing 8.910s 2.891ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 25.450s 9.477ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 10.160s 6.031ms 5 5 100.00
sysrst_ctrl_csr_rw 4.110s 2.075ms 20 20 100.00
sysrst_ctrl_csr_aliasing 8.910s 2.891ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 25.450s 9.477ms 20 20 100.00
V2 TOTAL 592 692 85.55
V2S tl_intg_err sysrst_ctrl_sec_cm 1.089m 42.019ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.157m 42.511ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.157m 42.511ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 7.640s 6.010ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 782 932 83.91

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35

Failure Buckets

Past Results